Abstract: This disclosure relates to parity declustered storage device arrays having partition groups. In an exemplary embodiment, the storage system includes a storage device array, such as disk array. Each storage device is divided into partitions. Each partition includes stripe units, such as hundreds or thousands of stripe units in exemplary embodiments. The storage system also includes a physical array controller coupled to the storage device array. In an exemplary embodiment, the array controller includes a partition group lookup table and stores and retrieves data and parity in the storage devices based on the partition group lookup table. In this exemplary embodiment, the array controller also includes a stripe lookup table and/or a log. In an exemplary embodiment, the partition group lookup table and the stripe lookup table take up less memory (e.g., by an order of magnitude) than a single-level stripe map conveying the same information.

Abstract: A tracking buffer apparatus is disclosed. A tracking buffer apparatus includes lookup logic configured to locate entries having a transaction identifier corresponding to a received request. The lookup logic is configured to determine which of the entries having the same transaction identifier has a highest priority and thus cause a corresponding entry from a data buffer to be provided. When information is written into the tracking buffer, write logic writes a corresponding transaction identifier to the first free entry. The write logic also writes priority information in the entry based on other entries having the same transaction identifier. The entry currently being written may be assigned a lower priority than all other entries having the same transaction identifier. The priority information for entries having a common transaction identifier with one currently being read are updated responsive to the read operation.

Abstract: A communication apparatus has plural processors to perform pipeline processing on communication data. A first processor among the plural processors transfers information, used by a second processor to perform post-stage processing of the first processor, from a first memory to a second memory.

Abstract: A method for preloading into a hierarchy of memories, bitstreams representing the configuration information for a reconfigurable processing system including several processing units. The method includes an off-execution step of determining tasks that can be executed on a processing unit subsequently to the execution of a given task. The method also includes, during execution of the given task, computing a priority for each of the tasks that can be executed. The priority depends on information relating to the current execution of the given task. The method also includes, during execution of the given task, sorting the tasks that can be executed in the order of their priorities. The method also includes, during execution of the given task, preloading into the memory, bitstreams representing the information of the configurations for the execution of the tasks that can be executed, while favoring the tasks whose priority is the highest.

Abstract: In the computer system, a storage system provides a storage level virtual volume based on thin provisioning technology, to a physical server on which a virtual machine is defined. The storage system releases the area of the logical volume corresponding to the storage level virtual volume accessed by a virtual machine which is specified to be deleted, on the basis of storage level virtual volume conversion information which is managed by the storage system.

Abstract: A method for concurrently converting a standard volume to a thin-provisioned volume includes initially establishing metadata for a thin-provisioned volume. The method then updates the metadata for the thin-provisioned volume to point to extents residing in a standard volume. The method then suspends I/O to metadata for the standard volume. Upon suspending the I/O, the method migrates control of the extents in the standard volume from a standard-volume control algorithm to a thin-provisioned-volume control algorithm. The method then resumes the I/O to the metadata for the thin-provisioned volume. Using this technique, standard volumes may be rapidly converted to thin-provisioned volumes while minimally disrupting I/O to the volumes. A corresponding apparatus and computer program product are also disclosed and claimed herein.

Abstract: The present application is directed to a memory-access-multiplexing memory controller that can multiplex memory accesses from multiple hardware threads, cores, and processors according to externally specified policies or parameters, including policies or parameters set by management layers within a virtualized computer system. A memory-access-multiplexing memory controller provides, at the physical-hardware level, a basis for ensuring rational and policy-driven sharing of the memory-access resource among multiple hardware threads, cores, and/or processors.

Abstract: A mechanism is provided in a computing system for controlling virtualized storage operable to communicate with a host and with mapped and unmapped storage resource pools. A selection component selects a target for a destructive data storage operation from the mapped storage resource pool. Responsive to the selection of the target, a virtual targeting component creates a virtual target from the unmapped storage resource pool to represent the target. Responsive to the selection of the target, a storage move component moves the target to a protected storage resource pool. Responsive to the creation of the virtual target from the unmapped storage resource pool, storage move component, moves the virtual target to the used storage resource pool. The computing system then performs the destructive data storage operation on the virtual target.

Abstract: A virtual machine is suspended and quickly restarted while maintaining the VM's state. The method is quick enough so that network connections are maintained across the restart and the guest operating system and guest applications running in the VM are not aware of the restart. As a result, users and clients connected to the VM do not notice any downtime or disruption to the VM. After suspension and before the restart, VM configuration changes that would not be possible or be very difficult through code changes alone while the VM was running can be made.

Abstract: Techniques for optimizing data movement in electronic storage devices are disclosed. In one particular exemplary embodiment, the techniques may be realized as a method for optimizing data movement in electronic storage devices comprising maintaining, on the electronic storage device, a data structure associating virtual memory addresses with physical memory addresses. Information can be provided regarding the data structure to a host which is in communication with the electronic storage device. Commands can be received from the host to modify the data structure on the electronic storage device, and the data structure can be modified in response to the received command.

Abstract: A storage system includes a virtual volume, a plurality of RAID groups, a pool unit for managing a plurality of first real storage areas and a controller. If a write command related to the virtual volume is issued from a higher-level device, the controller selects a prescribed second real storage area from among respective second real storage areas included in a prescribed first real storage area, and associates this prescribed second real storage area with a prescribed area inside the virtual volume corresponding to the write command, and which associates one virtual volume with one first real storage area. A migration destination determination unit selects a migration-targeted second real storage area from among the respective second real storage areas associated with the virtual volume, and selects a migration-destination first real storage area, which is to become the migration destination of data stored in the migration-targeted second real storage area.

Abstract: A method for resource management of a data processing system is described herein. According to one embodiment, a token is periodically pushed into a memory usage queue, where the token includes a timestamp indicating time entering the memory usage queue. The memory usage queue stores a plurality of memory page identifiers (IDs) identifying a plurality of memory pages currently allocated to a plurality of programs running within the data processing system. In response to a request to reduce memory usage, a token is popped from the memory usage queue. A timestamp of the popped token is then compared with current time to determine whether a memory usage reduction action should be performed.

Abstract: A method and system manages memory in a network of virtual machines, including a copy of a master virtual machine (VM) memory system, the copy accessible to a memory server. The method includes determining whether a memory page requested by a clone VM memory system is fetchable from the memory server, the clone VM memory system hosted in a host memory system; if the memory page is fetchable from the memory server, fetching the memory page from the memory server; determining whether there is sufficient space in the host memory system to load the memory page; if there is insufficient space in the host memory system, evicting a selected memory page from the host memory system; and loading the memory page into the host memory system and the clone VM memory system.

Abstract: Extended translation look-aside buffers (eTLB) for converting virtual addresses into physical addresses are presented, the eTLB including, a physical memory address storage having a number of physical addresses, a virtual memory address storage configured to store a number of virtual memory addresses corresponding with the physical addresses, the virtual memory address storage including, a set associative memory structure (SAM), and a content addressable memory (CAM) structure; and comparison circuitry for determining whether a requested address is present in the virtual memory address storage, wherein the eTLB is configured to receive an index register for identifying the SAM structure and the CAM structure, and wherein the eTLB is configured to receive an entry register for providing a virtual page number corresponding with the plurality of virtual memory addresses.

Abstract: A system is used in caching with flash-based memory. First and second controllers communicate with a flash-based cache. A magnetic disk array is in communication with the flash-based cache. The flash-based cache has a dual ported link to the first and second controllers. The flash-based cache has flash-based memory components arranged in a RAID data protection scheme.

Abstract: Various embodiments for improving data storage and retrieval performance, for a tiered storage environment having levels corresponding to storage performance, are provided. In one embodiment, by way of example only, reference count information of at least one data segment maintained in the tiered storage environment is used to determine which of the levels in the tiered storage environment the at least one data segment is assigned. Those of the at least one data segment having higher reference counts are assigned to a higher performance level than those having lower reference counts.

Abstract: A method for concurrently converting a standard volume to a thin-provisioned volume includes initially establishing metadata for a thin-provisioned volume. The method then updates the metadata for the thin-provisioned volume to point to extents residing in a standard volume. The method then suspends I/O to metadata for the standard volume. Upon suspending the I/O, the method migrates control of the extents in the standard volume from a standard-volume control algorithm to a thin-provisioned-volume control algorithm. The method then resumes the I/O to the metadata for the thin-provisioned volume. Using this technique, standard volumes may be rapidly converted to thin-provisioned volumes while minimally disrupting I/O to the volumes. A corresponding apparatus and computer program product are also disclosed and claimed herein.

Abstract: A method for writing and reading data memory cells, comprising: defining in a first memory zone erasable data pages and programmable data blocks; and, in response to write commands of data, writing data in erased blocks of the first memory zone, and writing, in a second memory zone, metadata structures associated with data pages and comprising, for each data page, a wear counter containing a value representative of the number of times that the page has been erased.

Abstract: A sliding window policy is implemented to manage database objects. At a first time, a first portion of a database object is allocated to a first tier of a multi-tier storage system. The first portion corresponds to a first specified percentage of the size of the database object at the first time and is selected according to information associated with the database object. The remaining portion of the database object at the first time is allocated to one or more other tiers. At a second (later) time, a second portion of the database object is allocated to the first tier. The second portion corresponds to a second specified percentage of the size of the database object at the second time and is also selected according to information associated with the database object. The remaining portion of the database object at the second time is allocated to the other tier(s).

Abstract: Methods and apparatuses for adjusting the size of a virtual band or virtual zone of a storage medium are provided. In one embodiment, an apparatus may comprise a data storage device including a data storage medium having a physical zone; and a processor configured to receive a virtual addressing adjustment command, and adjust a number of virtual addresses in a virtual band mapped to the physical zone based on the virtual addressing adjustment command. In another embodiment, a method may comprise providing a data storage device configured to implement virtual addresses associated with a virtual band mapped to a physical zone of a data storage medium of the data storage device, receiving at the data storage device a virtual addressing adjustment command, and adjusting a number of virtual addresses in a virtual band based on the virtual addressing adjustment command.

Abstract: A storage system includes plural types of storage devices that define a plurality of virtual volumes and a plurality of logical volumes. A storage controller is configured to manage the plurality of virtual volumes and the plurality of logical volumes, the plurality of virtual volumes defining first storage areas and the plurality of logical volumes defining second storage areas. A second storage area of the plurality of logical volumes is allocated to a first storage area of the plurality of virtual volumes. The storage controller is configured to determine whether data of a first storage area of a swap file is to be stored in the first tier storage device or the second tier storage device based on access information from an application server that manages a swap file information of the swap file.

Abstract: Memory of a database management system (DBMS) that is running in a virtual or physical machine is managed using techniques that that reduce the effect of memory swaps on the performance of the physical or virtual machine. One such technique includes the steps of determining a swap rate while the database application is in an executing state, and decreasing the size of memory space available to the database application if the swap rate is above a threshold.

Abstract: Each level of cache within a memory hierarchy of a device is configured with a cache results register (CRR). The caches are coupled to a debugger interface via a peripheral bus. The device is placed in debug mode, and a debugger forwards a transaction address (TA) of a dummy transaction to the device. On receipt of the TA, the device processor forwards the TA via the system bus to the memory hierarchy to initiate an address lookup operation within each level of cache. For each cache in which the TA hits, the cache controller (debug) logic updates the cache's CRR with Hit, Way, and Index values, identifying the physical storage location within the particular cache at which the corresponding instruction/data is stored. The debugger retrieves information about the hit/miss status, the physical storage location and/or a copy of the data via direct requests over the peripheral bus.

Abstract: A memory management and writing method for managing a memory module is provided. The memory module has a plurality of memory units and a plurality of data input/output buses corresponding to the memory units. The method includes configuring a plurality of logical units, dividing each of the logical units as a plurality of logical parts, and mapping the logical parts of each of the logical units to physical blocks of the memory units. The method also includes respectively establishing mapping tables corresponding to the data input/output buses, and only using one of the data input/output buses to write data from a host system into the corresponding memory unit according to the mapping table corresponding to the data input/output bus. Accordingly, the method can effectively increase the speed of writing data into the memory module.

Abstract: In a nonvolatile memory array, blocks that contain only obsolete data are modified by adding charge to their cells, increasing the charge level from the programmed charge levels that represented obsolete data to elevated charge levels. The increase in overall charge in such blocks lessens the tendency of such blocks to impact data retention in neighboring blocks.

Abstract: A data protecting method for a rewritable non-volatile memory module having physical blocks is provided, a plurality of logical block addresses is mapped to a part of the physical blocks. The method includes, configuring a plurality of virtual block addresses to map to the logical block addresses, grouping at least one virtual block address into a virtual block address area, and allocating the virtual block address area to an application. The method also includes, receiving an access command which is configured to instruct accessing a first virtual block address from the application. The method also includes: determining whether the first virtual block address belongs to the virtual block address area, if not, sending an error message to the application. Accordingly, the method can effectively prevent an application from accessing the data which can not be accessed by the application program.

Abstract: A system and computer program product for mirroring virtual machines from a primary host to a secondary host. The system includes a processor tracking changes for each of a plurality of memory pages and processor states for one or more primary host virtual machines. Responsive to an occurrence of a checkpoint, the primary host virtual machines are stopped. A determination is made if each of the memory pages is frequently changed. In response to the memory page being frequently changed, the frequently changed memory page is marked as being writeable and copied to a buffer. In response to the memory page being infrequently changed, the infrequently changed memory page is marked as being read only. The one or more primary host virtual machines are resumed. A copy of the memory pages, the buffer and changes to the processor states are transmitted to the secondary host.

Abstract: A storage apparatus comprises storage devices of a plurality of types of varying performance, and a control unit which manages each of storage areas provided by the storage devices of the plurality of types by means of storage tiers of a plurality of different types, and assigns the storage areas in page units to a virtual volume from any of the storage tiers among the storage tiers of the plurality of types, wherein, if the data I/O request is received from the host, the control unit assigns storage areas in page units from the uppermost storage tier to the target areas of the virtual volume corresponding to the I/O request, and wherein the control unit changes the page unit storage area assignment to predetermined areas of the virtual volume from an upper storage tier to a lower storage tier in accordance with the speed of processing of the data I/O request from the host.

Abstract: One embodiment of the present invention is a technique to invalidate entries in a translation lookaside buffer (TLB). A TLB in a processor has a plurality of TLB entries. Each TLB entry is associated with a virtual machine extension (VMX) tag word indicating if the associated TLB entry is invalidated according to a processor mode when an invalidation operation is performed. The processor mode is one of execution in a virtual machine (VM) and execution not in a virtual machine.

Abstract: A method and system to refresh a data entry in a cache before the data entry expires. The system includes a client computing system coupled to a server via a network connection. In response to a request for data access, the client computing system locates a data entry in a cache and determines whether the data entry in the cache has exceeded a refresh timeout since a last update of the data entry. If the data entry in the cache has exceeded the refresh timeout, the client computing system retrieves the data entry found in the cache in response to the request without waiting for the data entry to be refreshed, and requests a refresh of the data entry from the server via the network connection.

Abstract: In a storage control apparatus, a first duplication control unit causes a logical volume in a disk array device to be copied to a secondary storage medium. A second duplication control unit causes the logical volume to be copied also to an export storage medium in a library device, in connection with the copying to the primary storage medium by the first duplication control unit, when export attributes indicate that the logical volume copied by the first duplication control unit is supposed to be exported. A medium ejection control unit causes the library device to eject the export storage medium, in response to an ejection request therefor.

Abstract: A method for enabling inter-process communication between a first application and a second application, the first application running within a first context and the second application running within a second context of a virtualization system is described. The method includes receiving a request to attach a shared region of memory to a memory allocation, identifying a list of one or more physical memory pages defining the shared region that corresponds to the handle, and mapping guest memory pages corresponding to the allocation to the physical memory pages. The request is received by a framework from the second application and includes a handle that uniquely identifies the shared region of memory as well as an identification of at least one guest memory page corresponding to the memory allocation. The framework is a component of a virtualization software, which executes in a context distinct from the context of the first application.

Abstract: A method for writing and reading data in memory cells, comprises the steps of: defining a virtual memory, defining write commands and read commands of data (DT) in the virtual memory, providing a first nonvolatile physical memory zone (A1), providing a second nonvolatile physical memory zone (A2), and, in response to a write command of an initial data, searching for a first erased location in the first memory zone, writing the initial data (DT1a) in the first location (PB1(DPP0)), and writing, in the metadata (DSC0) an information (DS(PB1)) allowing the first location to be found and an information (LPA, DS(PB1)) forming a link between the first location and the location of the data in the virtual memory.

Abstract: Reliable storage for database management systems (DBMS) running on memory devices such as NAND type flash memory utilizes minimum I/O overhead and provides maximum data durability. A virtual page map is utilized between the flash memory and a page access component to record changes to the DBMS pages and prevent overwriting or data loss. There is no need for journaling and logging, and performance is increased by reducing the write and erase counts on the flash memory. The logical page numbers of the DBMS are mapped to physical page numbers in the page map, such that the virtual page map allocates an available page from the physical pages when changes to a page occur, and the updated information is stored in the allocated page. The allocated page number is mapped to the logical page number of the original page, thus maintaining a modified page representation while preventing physical in-place updates.

Abstract: To improve the performance of a computer system and user-friendliness for an administrator. A storage system 30 provides a virtual volume 32 to a host computer 10. Based on an access frequency, the storage system rearranges data in a logical storage region of the virtual volume in any of a plurality of storage tiers. A management computer monitors statuses of resources (the host computer, a switch, a controller of the storage system) related to the virtual volume, and determines to permit or inhibit the execution of a rearrangement process on the virtual volume based on the monitoring result. The management computer notifies the storage system of the details of this determination.

Abstract: One or more embodiments provides a shadow page table used by a virtualization software wherein at least a portion of the shadow page table shares computer memory with a guest page table used by a guest operating system (OS) and wherein the virtualization software provides a mapping of guest OS physical pages to machine pages.

Abstract: A distributed shared memory multiprocessor that includes a first processing element, a first memory which is a local memory of the first processing element, a second processing element connected to the first processing element via a bus, a second memory which is a local memory of the second processing element, a virtual shared memory region, where physical addresses of the first memory and the second memory are associated for one logical address in a logical address space of a shared memory having the first memory and the second memory, and an arbiter which suspends an access of the first processing element, if there is a write access request from the first processing element to the virtual shared memory region, according to a state of a write access request from the second processing element to the virtual shared memory region.

Abstract: A physical host machine determines that a storage device from a network storage system is available to the host machine as a pass-through disk. Virtualization software running on the host machine assigns the pass-through disk to a temporary resource group on the host machine. The pass-through disk is logically attached to the virtual machine running on the host machine and made available to an operating system and application running on the virtual machine.

Abstract: Paging memory from random access memory (‘RAM’) to backing storage in a parallel computer that includes a plurality of compute nodes, including: executing a data processing application on a virtual machine operating system in a virtual machine on a first compute node; providing, by a second compute node, backing storage for the contents of RAM on the first compute node; and swapping, by the virtual machine operating system in the virtual machine on the first compute node, a page of memory from RAM on the first compute node to the backing storage on the second compute node.

Abstract: Methods and systems for the optimization of available computing resources within a virtual environment are disclosed. An exemplary method comprises determining the sizes of the computing resources available to the virtual machine and determining optimal data structures for the virtual machine based on the sizes of the computing resources. The optimal data structures may include an indexing data structure and a historic data. The method may further comprise allocating a Random Access Memory (RAM) and disk storage to the optimal data structures and configuring the optimal data structures within the RAM and the disk storage. The optimization of data structures involves balancing requirements of the indexing data structure and the historic data.

Abstract: An apparatus having a plurality of memory blocks and a circuit is disclosed. The circuit may be configured to (i) generate a second address by removing one or more first bits of a first address from one or more first locations defined by a first value, (ii) generate a third address by adding an offset value to the second address and (iii) generate a fourth address by inserting a selected one of a plurality of modifiers into the third address. The selected modifier may be inserted into the third address at the first locations. Each modifier is generally associated with a respective one of a plurality of buffers formed in the memory blocks. The circuit may also be configured to access the respective buffer of the fourth address.

Abstract: A system, method and computer program product for virtualizing a processor include a virtualization system running on a computer system and controlling memory paging through hardware support for maintaining real paging structures. A Virtual Machine (VM) is running guest code and has at least one set of guest paging structures that correspond to guest physical pages in guest virtualized linear address space. At least some of the guest paging structures are mapped to the real paging structures. A cache of connection structures represents cached paths to the real paging structures. The mapped paging tables are protected using RW-bit. A paging cache is validated according to TLB resets. Non-active paging tree tables can be also protected at the time when they are activated. Tracking of access (A) bits and of dirty (D) bits is implemented along with synchronization of A and D bits in guest physical pages.

Abstract: A technique for transferring data in a digital signal processing system is described. In one example, the digital signal processing system comprises a number of fixed function accelerators, each connected to a memory access controller and each configured to read data from a memory device, perform one or more operations on the data, and write data to the memory device. To avoid hardwiring the fixed function accelerators together, and to provide a configurable digital signal processing system, a multi-threaded processor controls the transfer of data between the fixed function accelerators and the memory. Each processor thread is allocated to a memory access channel, and the threads are configured to detect an occurrence of an event and, responsive to this, control the memory access controller to enable a selected fixed function accelerator to read data from or write data to the memory device via its memory access channel.

Abstract: Data is placed in tiered storage with a suitable granularity according to application characteristics. The storage apparatus comprises a controller for managing storage areas, provided by storage media of a plurality of types of varying performance, as pools, and for assigning the storage areas in page units to a virtual volume from any tiered storage among a plurality of types of tiered storage which the pool comprises in response to a data write request from the host computer, wherein, for specific data which is managed by the host computer, the controller specifies an area with a high referencing frequency among the specific data on the basis of organization information of the specific data, and moves this area to another of the tiered storage with a higher performance than an already assigned tiered storage.

Abstract: A system and method for providing high-speed memory operations is disclosed. The technique uses virtualization of memory space to map a virtual address space to a larger physical address space wherein no memory bank conflicts will occur. The larger physical address space is used to prevent memory bank conflicts from occurring by moving the virtualized memory addresses of data being written to memory to a different location in physical memory that will eliminate a memory bank conflict.

Abstract: The invention relates to a method for determining identifiers associated with segments of a document. Each segment consists of a series of individual elements such as images or sound sequences. Each segment of the document is subdivided into a determined number of portions comprising the same number of individual elements. An individual element is extracted from the most central portion of each segment and associated with the segment as identifier. The invention also relates to the receiver capable of implementing the method.

Abstract: A method for sharing memories of virtual machines is provided. The method is applied for a computer system configured to execute at least one virtual machine. The method includes the following steps. A memory map corresponding to the virtual machines is obtained, wherein usage states of memory pages of the virtual machine are stored in the corresponding memory map. Unused memory pages of the virtual machines are marked as free pages according to the corresponding memory map. The free pages of the virtual machines are shared. Therefore, the unused memory pages in the virtual machine can be shared. A computer system using the foregoing method is also provided.

Abstract: When a method for relocating data to a preferable storage area based on access frequency is applied to virtual machines, it takes a long time for determining volumes that are not accessed, and the access performance is deteriorated. The present invention provides a system and method in which a utilization status of a virtual machine is checked by the storage system, and pages used by virtual machines not being utilized are relocated promptly to lower tiers and pages used by virtual machines being utilized are relocated promptly to higher tiers, according to which the performance of the system is improved.

Abstract: A method for identifying memories of virtual machines is provided. The method is adapted to a computer system executing at least one virtual machine, and an operating system is executed on the virtual machine. The method includes the following steps. A kernel file of the operating system is obtained, and the kernel file includes version information of the operation system. A source code and a configuration file of the operating system are obtained according to the version information, and the versions of the source code and the configuration file are complied with the version of the operating system. An object file is generated by compiling a fixed interface function with the source code according to the configuration file. Memory pages of the virtual machine are identified according to the object file. Furthermore, a computer system using the foregoing method is also provided.

Abstract: A memory hierarchy in a computer includes levels of cache. The computer also includes a processor operatively coupled through two or more levels of cache to a main random access memory. Caches closer to the processor in the hierarchy are characterized as higher in the hierarchy. Memory management among the levels of cache includes identifying a line in a first cache that is preferably retained in the first cache, where the first cache is backed up by at least one cache lower in the memory hierarchy and the lower cache implements an LRU-type cache line replacement policy. Memory management also includes updating LRU information for the lower cache to indicate that the line has been recently accessed.