Abstract: A high efficiency portable archive (“HEPA”) implements a storage system running in a computer architecture to generate point-in-time versions of a raw data set. The HEPA can be implemented in a variety of computer architectures with the storage system being implemented as a conventional application on a host operating system or as a virtual system on a virtualization layer. In either case, the point-in-time versions and optionally the storage system itself can be archived on archive media. Alternately, the point-in-time versions and optionally the storage system itself can be replicated to a virtualized storage system first and then archived on archive media. The storage system and point-in-time versions of the raw data set can be restored into a virtual system on any hardware subsystem that supports the virtual system.

Abstract: A method is disclosed for dynamically allocating main memory among applications. The method includes maintaining a first list and a second list, each list having a plurality of pages, maintaining a cache memory module having a selected size, and resizing the selected size by adaptively selecting the first or second list and adding pages to the selected list to increase the selected size and subtracting pages from the selected list to decrease the selected size.

Abstract: A load instruction that accesses data cache may be off natural alignment, which causes a cache line crossing to complete the access. The illustrative embodiments provide a mechanism for loading data across multiple cache lines without the need for an accumulation register or collection point for partial data access from a first cache line while waiting for a second cache line to be accessed. Because the accesses to separate cache lines are concatenated within the vector rename register without the need for an accumulator, an off-alignment load instruction is completely pipeline-able and flushable with no cleanup consequences.

Abstract: A page table management circuit includes a memory control circuit including a memory unit that stores information used to convert a virtual address into a physical address with respect to each entry and designating the entry according to an input address value, and an address conversion circuit converting an input address value such that a total number of the entries to be designated by the memory control circuit is reduced and outputting the converted address value to the memory control circuit.

Abstract: An apparatus and method are provided for communicating with a plurality of physical memory circuits. In use, at least one virtual memory circuit is simulated where at least one aspect (e.g. power-related aspect, etc.) of such virtual memory circuit(s) is different from at least one aspect of at least one of the physical memory circuits. Further, in various embodiments, such simulation may be carried out by a system (or component thereof), an interface circuit, etc.

Abstract: Embodiments of the present invention are directed to enhancing VPAR monitors to allow an active VPAR to be moved from one machine to another, as well as to enhancing virtual-machine monitors to move active VPARs from one machine to another. Because traditional VPAR monitors lack access to many computational resources and to executing-operating-system state, VPAR movement is carried out primarily by specialized routines executing within active VPARs, unlike the movement of guest operating systems between machines carried out by virtual-machine-monitor routines.

Abstract: Exemplary embodiments of the invention provide a solution to deploy a virtual hard disk (VHD) to virtual device with maximizing capacity efficiency and data access performance by making the allocation unit size of virtual device the same as that of the VHD. In one embodiment, a method of deploying a VHD file to a storage apparatus comprises checking a block size of the VHD file received by the storage apparatus based on a header of the VHD file; creating a virtual volume to provide a page size which is same size as the block size of the VHD file; and performing one of (A) copying contents of the VHD file to the created virtual volume by allocating one page of the created virtual volume for each block of the VHD file; or (B) formatting the created virtual volume with a virtual volume file system, and copying the VHD file to the formatted virtual volume.

Abstract: A management includes an acquiring unit for acquiring information of specifying a target virtual storage in a target storage pool and an expansion storage capacity to be acquired from another storage pool other than the target storage pool, and a determining unit for determining the real storage to be used for the expansion storage capacity of the target virtual storage from candidate one of the real storages in the another storage pool, which are under the control of the controller in charge of the real storage that the target virtual storage is defined, on the basis of an occupied storage capacity defined as the virtual storage on the real storage in the another storage pool and a free storage capacity of the real storage in the another storage pool.

Abstract: A hierarchical memory storage using a concentrator device that is located between a processor and memory storage devices to provide a succession of memory devices and enable attachment of a memory depth to a processor controller with a limited pin count.

Abstract: Described embodiments provide a first-in, first-out (FIFO) buffer for packet switching in a crossbar switch with a speedup factor of m. The FIFO buffer comprises a plurality of registers configured to receive N-bit portions of data in packets and a plurality of one-port memories, each having width W segmented into S portions a width W/S. A first logic module is coupled to the registers and the one-port memories and receives the N-bit portions of data in and the outputs of the registers. A second logic module coupled to the one-port memories constructs data out read from the one-port memories. In a sequence of clock cycles, the N-bit data portions are alternately transferred from the first logic module to a segment of the one-port memories, and, for each clock cycle, the second logic module constructs the data out packet with output width based on the speedup factor of m.

Abstract: A storage system includes a storage medium configured to store data and a buffer memory configured to buffer data to be written to the storage medium. The storage system further includes a controller configured to selectively transfer the buffered data to the storage medium responsive to an invalidity indicator received from an external source. For example, the invalidity indicator may comprise unwrite information received from an external source, e.g., information that indicates that selected buffered data corresponds to deleted file data.

Abstract: A server power manager and method for dynamic server power management are generally described herein. The server power manager is configured to implement one or more server management policies that identify target server power consumption and/or target functionality for the server system. The server power manager determines an amount of excess processing capability and/or an amount of excess physical memory based on the target server power consumption and the target functionality. The server power manager may transition a processor core to a lower-operational state when at least a predetermined amount of excess processing capability is determined while maintaining server system functionality. The server power manager may transition a memory module to a lower-operational state when at least a predetermined amount of excess physical memory is determined while maintaining the server system functionality.

Abstract: Extended translation look-aside buffers (eTLB) for converting virtual addresses into physical addresses are presented, the eTLB including, a physical memory address storage having a number of physical addresses, a virtual memory address storage configured to store a number of virtual memory addresses corresponding with the physical addresses, the virtual memory address storage including, a set associative memory structure (SAM), and a content addressable memory (CAM) structure; and comparison circuitry for determining whether a requested address is present in the virtual memory address storage, wherein the eTLB is configured to receive an index register for identifying the SAM structure and the CAM structure, and wherein the eTLB is configured to receive an entry register for providing a virtual page number corresponding with the plurality of virtual memory addresses.

Abstract: A file access manager for scheduling of read/write operations and disk I/O operations for files that must be retrieved from disk storage. The file access manager schedules the operations such that a single file retrieval from disk is required for a plurality of processes to operate on the file. If any of the processes write to the file, a single disk write operation is then performed.

Abstract: A system to delete a data volume may include storage of a plurality of data pages of the data volume of a data area into a cache, prevention of writing of data pages to the data volume, and designation of each of the plurality of data pages in the cache as modified. The system may also include writing of all data pages in the cache that are designated as modified to a respective location in one or more other data volumes of the data area, and updating, for each of the written data pages, a converter page of the cache to associate the written data page with its respective location in the one or more other data volumes.

Abstract: A storage device that includes: a flash memory device being a main storage medium; a cache memory for use for the flash memory device; and a control circuit. In the storage device, based on a write command and address information provided from outside, the control circuit selects either the flash memory device or the cache memory as a writing destination of input data.

Abstract: The present invention describes improving the scheduling of read commands on a mirrored memory computer system by utilizing information about pending memory access requests. A conflict queue is configured to track a read/write queue associated with each of a plurality of memory ports on the mirrored memory system. The conflict queue determines a predicted latency on each memory port based on the contents of each of the read/write queues. A compare logic unit is coupled to the conflict queue, wherein the compare logic unit compares a predicted latency of a primary memory and a mirrored memory and schedules read commands to the memory port with the lowest predicted latency.

Abstract: A dynamic memory management method suitable for a memory allocation request of various applications can include predicting whether an object for which memory allocation is requested is a short-lived first type object or a long-lived second type object by using index information relating to the size of the object; determining whether a heap memory includes a free block that is to be allocated to the object by using a plurality of free lists that are classified as a plurality of hierarchical levels; and allocating the free block to the object if the heap memory is determined to include the free block, wherein, if the object is predicted to be the first type object, the free block is allocated to the object in a first direction in the heap memory, and, if the object is predicted to be the second type object, the free block is allocated to the object in a second direction in the heap memory.

Abstract: Disclosed is a memory device including a NVRAM and a page table, and a wear leveling method therefor. The page table includes mapping information which maps virtual addresses of the NVRAM with physical addresses of the NVRAM. A page table entry includes aging information which indicates the wear of a corresponding page. The aging information may be a remaining number of write operations allowed to the page. Whenever data is written in a page, a value indicating a remaining number of write operations allowed to that page is decremented.

Abstract: In the control of the number of program-erase cycles, physical blocks (PBs) are divided into plural groups on a basis of the number of program-erase cycles and a search for a free PB is performed in the groups when assigning a logical block (LB) to the free PB. In the search, a free PB among a group covering a small number of program-erase cycles precedes that among a group covering a large number of program-erase cycles. Further, when searching out a free PB in the search, data stored in a PB (source PB) included in a group covering a smaller number of program-erase cycles than that covered by a group including the free PB searched out are transferred to the free PB if there is the source PB. The source PB is a PB to which a LB is assigned earliest among a group including it.

Abstract: In one embodiment, a method for accessing a physical storage-device array comprising a plurality of storage devices. The method includes (1) obtaining at least one parameter from a profile selected from two or more profiles concurrently defining two or more virtual arrays, each profile defining (i) a different virtual array associated with a corresponding set of storage devices and (ii) a parameter set of one or more parameters used for accessing the virtual array; and (2) generating an instruction, based on the at least one parameter, for accessing information to the virtual array defined by the selected profile.

Abstract: A cache logically disposed in a communication path between a client and a server receives a request for a content item and, in response thereto, requests from the server header information concerning the content item and an initial portion of data that makes up the content item. The cache then computes a first hashing value from the header information and a second hashing value from the initial portion of data. A content identifier is created by combining the first hashing value and the second hashing value. Using the content identifier, the cache determines whether a copy of the content item is stored by the cache; and, if so provides same to the client. Otherwise, the requests the content item from the server and, upon receipt thereof, provides it to the client.

Abstract: A controller includes an inputting/outputting portion, which receives data from a field device and outputs operated data to the field device, a flash memory including a file system, and a file system driver, which reads data held on a shared memory and writes the read data into the file system to save the data in the file system. The file system driver has a power-failure-safe function.

Abstract: A virtual tape control method for controlling a virtual tape device includes performing a migration process for storing data stored in a logical volume to a physical volume of a library device belonging to the virtual tape device, and automatically extracting the data stored in the logical volume on which the migration process is completed at the performing, and exporting the data to a physical volume of a library device of a sub-center via a network.

Abstract: A network arrangement that employs a cache having copies distributed among a plurality of different locations. The cache stores state information for a session with any of the server devices so that it is accessible to at least one other server device. Using this arrangement, when a client device switches from a connection with a first server device to a connection with a second server device, the second server device can retrieve state information from the cache corresponding to the session between the client device and the first server device. The second server device can then use the retrieved state information to accept a session with the client device.

Abstract: A method and apparatus for monitoring memory accesses in hardware to support transactional execution is herein described. Attributes are monitor accesses to data items without regard for detection at physical storage structure granularity, but rather ensuring monitoring at least at data items granularity. As an example, attributes are added to state bits of a cache to enable new cache coherency states. Upon a monitored memory access to a data item, which may be selectively determined, coherency states associated with the data item are updated to a monitored state. As a result, invalidating requests to the data item are detected through combination of the request type and the monitored coherency state of the data item.

Abstract: Roughly described, a data processing system comprises a memory addressable by a range of physical memory addresses; a plurality of non-privileged software domains each having a virtual memory address space; a privileged software domain; a memory management unit operable to perform virtual address translation of a virtual memory address into a physical memory address; and an I/O device supporting virtualised interfaces each associated with a respective non-privileged software domain, the I/O device comprising an operation management unit operable to perform virtual address translation in one or more of the virtual memory address spaces; wherein, for I/O operations requested by a virtualised interface, the I/O device invokes the operation management unit to perform virtual address translation for those I/O operations meeting first criteria and to invoke the memory management unit to perform virtual address translation for those I/O operations which do not meet the first criteria.

Abstract: A Simulator and a simulating method for running a guest program in a host are disclosed. The simulator includes: an initialization device configured for setting content of a hypervisor page table in the host, the hypervisor page table mapping a guest physical address space to a host physical address space. The simulator further includes a binary translation device configured for employing a program logical address to perform a memory access in code translation. The simulator also includes a miss handling device configured for updating a guest translation look-aside buffer by treating a miss in a host translation look-aside buffer caused by the execution of the translated code as a miss in the guest translation look-aside buffer, wherein the host translation look-aside buffer is configured to buffer entries for mapping addresses in a guest program logical address space to addresses in the guest physical address space.

Abstract: An improved duty cycle, increased effective bandwidth, and minimized power consumption are attained in a system for data migration between a compute cluster and disk drives by inclusion of a buffer node coupled to the compute cluster to store data received therefrom in a random fashion. The buffer node signals the computer nodes to promptly return from the I/O cycle to the computing state to improve the duty cycle of the device. The system further includes a storage controller which is coupled between the buffer node and the disk drives to schedule data transfer activity between them in an optimal orderly manner. The data transfers are actuated in the sequence determined based on minimization of seeking time and tier usage, and harvest priority, when the buffer node either reaches a predetermined storage space minimal level or a predetermined time has elapsed since the previous I/O cycle. The storage controller deactivates the disk drives which are not needed for the data transfer.

Abstract: Methods and systems to selectively map higher-usage addresses to higher-endurance memory cells of a flash memory, and lower-usage addresses to lower-endurance memory cells of the flash memory. Address usage may be determined with respect to the most recent write operation corresponding to an address and/or with respect to a frequency of write operations corresponding to the address. Higher-endurance memory cells may include single level cells (SLCs). Lower-endurance memory cells may include multi-level cells (MLCs). Improved endurance may be obtained with a relatively small percentage of higher-endurance memory cells, at a relatively low cost.

Abstract: The present invention provides a memory controller which includes a host interface connected to a host apparatus and receives a first data write-in unit of reception data, a memory interface connected to nonvolatile semiconductor memory in which is written a second data write-in unit of data larger than the first data write-in unit of data, and transmits the first data write-in unit of write-in data, and a central processing unit, which writes the reception data in a temporary write-in block of the nonvolatile semiconductor memory via the memory interface, reads out from the temporary write-in block the write-in data corresponding to area data when a total amount of reception data received by the host interface has reached amount of the second data write-in unit of the area data, and writes the area data including the read-out write-in data in a target block different from the temporary write-in block.

Abstract: A mechanism is provided in a computing system for controlling virtualized storage operable to communicate with a host and with mapped and unmapped storage resource pools. A selection component selects a target for a destructive data storage operation from the mapped storage resource pool. Responsive to the selection of the target, a virtual targeting component creates a virtual target from the unmapped storage resource pool to represent the target. Responsive to the selection of the target, a storage move component moves the target to a protected storage resource pool. Responsive to the creation of the virtual target from the unmapped storage resource pool, storage move component, moves the virtual target to the used storage resource pool. The computing system then performs the destructive data storage operation on the virtual target.

Abstract: A virtualization method for a storage system recognizes one or more logical devices located in a first and second storage apparatus and defined in a host apparatus as being connected to a channel, based on an inquiry command sent from the host apparatus when the channel comes on-line; detects one or more logical devices among the one or more logical devices defined in the host apparatus as being connected to the channel and located in the first and second storage apparatus, based on the recognition result; sets, based on the detection result, one or more virtual volumes in the first storage apparatus, respectively corresponding to the one or more logical devices in the second storage apparatus; and sets a first logical path between each of the set one or more virtual volumes and each of the corresponding one or more logical devices in the second storage apparatus.

Abstract: A method for pre-staging data includes obtaining a DST configuration of a virtual volume at a first point in time. The method also includes creating a Point-in-Time copy (PiT) in a destination storage pool when the virtual volume includes at least one PiT, or reconfiguring at least one virtual volume segment to contain a hot-spot. The virtual volume may or may not have PiTs. The method further includes recording the DST configuration, specifying the DST configuration be applied to the storage array at a second point in time, and applying the DST configuration to the storage array at the second point in time.

Abstract: A method of communicating image capture commands is provided. The method includes receiving a user command to capture an image. The image to be captured is incorporated in multimedia content delivered by a multimedia distribution system via a network to an end-user device. The method further includes sending an image-capture command to the multimedia distribution system via the network in response to receiving the user command.

Abstract: A method includes provisioning a virtual volume from at least one storage pool of a storage array, designating at least one virtual volume segment of the virtual volume for mapping a virtual volume range to a virtual drive range, organizing the virtual volume range into a plurality of clusters, measuring a data load on each of the plurality of clusters and comparing the data load on each of the plurality of clusters to activity of the virtual volume, and reconfiguring the at least one virtual volume segment to contain a hot-spot.

Abstract: A secure storage appliance is disclosed, along with methods of storing and reading data in a secure storage network. The secure storage appliance is configured to present to a client a virtual disk, the virtual disk mapped to the plurality of physical storage devices. The secure storage appliance is capable of executing program instructions configured to generate a plurality of secondary blocks of data by performing splitting and encrypting operations on a block of data received from the client for storage on the virtual disk and reconstitute the block of data from at least a portion of the plurality of secondary blocks of data stored in shares on corresponding physical storage devices in response to a request from the client.

Abstract: An embodiment of a method of predicting response time for a storage request begins with a first step of a computing entity storing a training data set. The training data set comprises past performance observations for past storage requests of a storage array. Each past performance observation comprises an observed response time and a feature vector for a particular past storage request. The feature vector includes characteristics that are available external to the storage array. In a second step, the computing entity forms a response time forecaster from the training data set. In the third step, the computing entity applies the response time forecaster to a pending feature vector for a pending storage request to obtain a predicted response time for the pending storage request.

Abstract: This memory management system has: (a) a logical partition management unit that manages allocation and release of a virtual memory used by an application in a logical address space; (b) a physical partition management unit that manages allocation and release of small size parts into which a physical memory is divided in a physical address space; and (c) a converter unit that converts an address between the logical address space and the physical address space.

Abstract: A method and a processing device are provided for mapping a non-page aligned memory buffer to an address space of a process. A beginning portion of a non-page aligned memory buffer and an ending portion of the non-page aligned memory buffer may be copied from respective original memory pages to new memory pages. Unused portions of the new memory pages may be initialized to zeros, ones, or other values. A safe buffer may be created, which resides in the new memory pages and all original memory pages of the non-page aligned memory buffer, except for the original memory pages including either the beginning portion or the ending portion of the non-page aligned buffer. The safe buffer may then be mapped to an address space of a process while avoiding unintended information disclosure.

Abstract: A method is provided for storing and retrieving data in a network-attached data storage device by a cooperatively multitasking real time operating system configured to execute datapath routines and a general purpose operating system kernel configured to communicate with the network.

Abstract: Improved memory management is provided according to a Hierarchical Immutable Content Addressable Memory Processor (HICAMP) architecture. In HICAMP, physical memory is organized as two or more physical memory blocks, each physical memory block having a fixed storage capacity. An indication of which of the physical memory blocks is active at any point in time is provided. A memory controller provides a non-duplicating write capability, where data to be written to the physical memory is compared to contents of all active physical memory blocks at the time of writing, to ensure that no two active memory blocks have the same data after completion of the non-duplicating write.

Abstract: In a virtualized computer system, a network frame is transmitted from a virtual machine using a network interface device, possibly through a virtual switch, by copying only a part of the network frame to the transmit buffers that have pre-translated mappings from guest physical addresses to hypervisor virtual addresses and to machine addresses. The length of the part of the network frame that is copied to the transmit buffers may be variable.

Abstract: Various aspects are disclosed herein for bounding the behavior of a non-privileged virtual machine that interacts with a device by creating a description of the device which indicates to a privileged authority (1) which operations on the device may have system-wide effects and (2) which operations have effects local to the device. The privileged authority may then permit or deny these actions. The privileged authority may also translate these actions into other actions with benign consequences.

Abstract: In a computer system with a DBMS running thereon, management of the performance of a storage apparatus is executed by using a performance indicator provided by a user job so as to simplify the management of the performance. For this reason, a management server employed in the computer system monitors an operating state of each system element, a response time onto a job and other information. A method for estimating a processing time is given to the management server, which issues a setting modification command based on an estimated processing time.

Abstract: A storage system comprises a storage medium including a plurality of physical storage areas. The storage system controls a host computer to recognize a logical volume having a plurality of virtual storage areas, reads the data from the physical storage area assigned to the virtual storage area of the logical volume, determines whether or not the read data includes only the specific pattern data, and cancels the assignment of the physical storage area to the virtual storage area if the read data includes only the specific pattern data.

Abstract: Used is a nonvolatile memory such as a multi-level NAND flash memory having memory cells for holding data of a plurality of pages. When the data is to be written in the nonvolatile memory 110, a physical unit is consisted in units of a plurality of paired pages. When all the physical units cannot be written, the data is copied from an old physical block holding an already written effective data, and is written in a new physical block till the written, from the first section of a new physical unit, so that an error can be prevented.

Abstract: An electronic data flash card is accessible by a host computer, and includes a processing unit connected to a flash memory device that stores a data file, and an input-output interface circuit activated so as to establish a communication with the host computer. In an embodiment, the electronic data flash card uses a USB input/output interface circuit for communication with the host computer. A flash memory controller includes an index for converting logical addresses sent by the host computer into physical addresses associated with sectors of the flash memory device. The index is controlled by arbitration logic referencing to values from various look up tables and valid data stored in the flash memory device. The flash memory controller further includes a first-in-first-out unit (FIFO) for recycling obsolete sectors of the flash memory device in the background process so that they are available for reprogramming.

Abstract: The memory controller forms temporary virtual blocks each composed of a plurality of physical blocks, whose physical addresses are the same value, each of which is included in each of flash memories, extracts temporary virtual block to which at least one defective block belongs from the temporary virtual blocks, generates a second temporary virtual block to which a defective block does not belong by replacing a defective block belonging to one temporary virtual block with a normal block belonging to another temporary virtual block among temporary virtual blocks extracted, and allocates temporary virtual blocks not extracted and second temporary virtual blocks generated to available virtual blocks.

Abstract: A virtualization method for a storage system recognizes one or more logical devices located in a first and second storage apparatus and defined in a host apparatus as being connected to a channel, based on an inquiry command sent from the host apparatus when the channel comes on-line; detects one or more logical devices among the one or more logical devices defined in the host apparatus as being connected to the channel and located in the first and second storage apparatus, based on the recognition result; sets, based on the detection result, one or more virtual volumes in the first storage apparatus, respectively corresponding to the one or more logical devices in the second storage apparatus; and sets a first logical path between each of the set one or more virtual volumes and each of the corresponding one or more logical devices in the second storage apparatus.