Abstract: A method of testing a processing includes performing a test of at least one logic block of a processor of a data processing system; receiving an interrupt; stopping the performing the test for the processor to respond to the interrupt, wherein the stopping the performing the test includes storing test data of the test to a memory prior to the processor responding to the interrupt; and after the processor responds to the interrupt, resuming performing the test, wherein the resuming performing the test includes retrieving the test data from the memory and using the retrieved test data for the resuming performing the test.

Abstract: Direct injection of a data to be transferred in a hybrid computing environment that includes a host computer and a plurality of accelerators, the host computer and the accelerators adapted to one another for data communications by a system level message passing module. Each accelerator includes a Power Processing Element (‘PPE’) and a plurality of Synergistic Processing Elements (‘SPEs’). Direct injection includes reserving, by each SPE, a slot in a shared memory region accessible by the host computer; loading, by each SPE into local memory of the SPE, a portion of data to be transferred to the host computer; executing, by each SPE in parallel, a data processing operation on the portion of the data loaded in local memory of each SPE; and writing, by each SPE, the processed data to the SPE's reserved slot in the shared memory region accessible by the host computer.

Abstract: In a computer system that can configure a virtual machine being able to transit to a hibernation state data of a main memory of the virtual machine stored in an auxiliary storage device is reduced. At a point in time when the virtual machine has transitioned to a hibernation state, from consideration as to whether the data of the main memory of the virtual machine stored in the auxiliary storage device is unnecessary, data stored in the auxiliary storage device is rewritten in order to reduce the data.

Abstract: A context of a mobile device is determined. A context preference of a user associated with the mobile device is determined. The context of the mobile device and the user context preference is transmitted to another node and responsively returned data is received. Available free space in the mobile device is determined. All data whose timestamp is within a predetermined threshold is cached. The data is cached in at least a portion of the free space.

Abstract: A method for sharing memory locations in a virtual memory system is disclosed. The method can include processing instructions and accessing data utilizing a virtual memory system with a paging device that is accessible by multiple clients. The method can also include configuring a first client to access the paging device, configuring a second client to access the paging device and allowing the first and second client to access the paging device via a virtual input output server. Other embodiments are also disclosed.

Abstract: A Multi-Level Cell (MLC) memory device and method thereof are provided. The example MLC memory device may be configured to perform data operations, and may include an MLC memory cell, a first coding device performing a first coding function, the first coding function being one of an encoding function and a decoding function, a second coding device performing a second coding function, the second coding function being one of an encoding function and a decoding function and a signal module configured to perform at least one of instructing the MLC memory cell to store data output by the second coding device if the first and second coding functions are encoding functions, and generating a demapped bit stream based on data retrieved from the MLC memory cell if the first and second coding functions are decoding functions.

Abstract: A memory management and writing method for managing a memory module is provided. The memory module has a plurality of memory units and a plurality of data input/output buses corresponding to the memory units. The method includes configuring a plurality of logical units, dividing each of the logical units as a plurality of logical parts, and mapping the logical parts of each of the logical units to physical blocks of the memory units. The method also includes respectively establishing mapping tables corresponding to the data input/output buses, and only using one of the data input/output buses to write data from a host system into the corresponding memory unit according to the mapping table corresponding to the data input/output bus. Accordingly, the method can effectively increase the speed of writing data into the memory module.

Abstract: A mechanism for dynamic placement of virtual machines (VMs) during live migration based on memory is disclosed. A method of embodiments of the invention includes determining candidate target host machines capable of receiving a VM to be migrated, obtaining a hash value for memory pages of the VM to be migrated, obtaining for each candidate target host machine hash values for shared memory pages utilized by one or more VMs hosted by the candidate target host machine, comparing for each candidate target host machine the hash values for the memory pages of the VM to be migrated with the hash values for the shared memory pages, and adjusting a score in a general selection algorithm for the candidate target host machine with the most identical matches of the hash values for the shared memory pages with the hash values for the memory pages of the VM to be migrated.

Abstract: A method for operating a storage system, consisting of performing an allocation of respective partitions of a physical storage resource of the storage system to respective hosts of the storage system. The method also includes changing the allocation while permitting the respective hosts of the storage system to access the physical storage resource.

Abstract: Apparatus for data processing 2 is provided with processing circuitry 8 which operates in one or more secure modes 40 and one or more non-secure modes 42. When operating in a non-secure mode, one or more regions of the memory are inaccessible. A memory management unit 24 is responsive to page table data to manage accesses to the memory which includes a secure memory 22 and a non-secure memory 6. Secure page table data 36, 38 is used when operating in one of the secure modes. A page table entry within the hierarchy of page tables of the secure page table data includes a table security field 68, 72 indicating whether or not a further page table pointed to by that page table entry is stored within the secure memory 22 or the non-secure memory 6. If any of the page tables associated with a memory access are stored within the non-secure memory 6, then the memory access is marked with a table attribute bit NST indicating that the memory access should be treated as non-secure.

Abstract: A storage controller and a method for controlling a storage controller, including a plurality of nonvolatile memory modules having a plurality of nonvolatile memory chips for storing data from a host computer and a nonvolatile memory control unit for controlling data input to and output from the host computer by controlling a power source for the nonvolatile memory modules. The nonvolatile memory control unit, when reading or writing data from or to a designated nonvolatile memory module at a specified time in response to a data read/write request from the host computer, controls the power source for only the designated nonvolatile memory module to be turned on that can maintain its performance and reduce power consumption and thereby realize large capacity and low power consumption.

Abstract: According to one embodiment, a data storage control method, which is applied to a virtual memory that controls access to the data stored in each of the physical memory regions by the corresponding one of the virtual addresses on the basis of an address management table that manages the correspondence relationship between a plurality of virtual addresses corresponding to a plurality of virtual memory regions and a plurality of physical addresses corresponding to a plurality of physical memory regions of a first memory, includes writing the data stored in a specific number of nonconsecutive physical memory regions made to correspond to a specific number of virtual memory regions on the basis of the address management table to a specific number of consecutive physical memory regions.

Abstract: A memory device that includes an input interface that receives instructions and input data on a first plurality of serial links. The instructions and input data are deserialized on the memory device, and are provided to a memory controller. The memory controller initiates accesses to a memory core in response to the received instructions. The memory core includes a plurality of memory partitions, which are accessed in a cyclic and overlapping manner. This allows each memory partition to operate at a slower frequency than the serial links, while properly servicing the received instructions. Accesses to the memory device are performed in a synchronous manner, wherein each access exhibits a known fixed latency.

Abstract: In one embodiment, the present invention includes a method for associating a first identifier with data stored by a first agent in a cache line of a cache to indicate the identity of the first agent, and storing the first identifier with the data in the cache line and updating at least one of a plurality of counters associated with the first agent in a metadata storage in the cache, where the counter includes information regarding inter-agent interaction with respect to the cache line. Other embodiments are described and claimed.

Abstract: In a storage apparatus and its control method including multiple first virtual volumes to be provided to a host system and multiple pools each having a memory capacity, and equipped with a function of dynamically allocating a storage area to the first virtual volumes from the pools associated with the first virtual volumes in accordance with the usage status of the first virtual volumes, the unused capacity in each of the pools is managed, and, when the unused capacity of one of the pools falls below a predetermined threshold value, a part of the unused capacity of the other pools is allocated to the one pool. It is thereby possible to realize a highly reliable storage apparatus and its control method.

Abstract: The present invention is directed to a method for providing data element placement in a storage system via a Dynamic Storage Tiering (DST) mechanism, such that improved system efficiency is promoted. For example, the DST mechanism may implement an algorithm for providing data element placement. The data elements (ex.—virtual volume hot-spots) may be placed into storage pools, such that usage of higher performing storage pools is maximized. Hot-spots may be detected by dynamically measuring load on LBA ranges. Performance of the storage pools may be measured on an ongoing basis. Further, the hot-spots may be ranked according to load, while storage pools may be ranked according to measured performance. If a hot-spot's load decreases, the hot-spot may be moved to a lower performing storage pool. If a hot-spot's load increases, the hot-spot may be moved to a higher performing storage pool.

Abstract: A computing system includes a first virtual machine associated with a memory region readable by the first virtual machine, and a first private memory region. A data object is created by the first virtual machine in the sharable memory region, readable and writeable by the first virtual machine and a second virtual machine. A mapping is established between the first virtual machine and a particular area of the shareable memory region. The computing system includes the second virtual machine associated with a second private memory region, and a reference to the particular area of the shareable memory region. The mapping enables both the first virtual machine and second virtual machine to read and write second data in the shareable memory region without creating a copy of the second data in the first and second private memory regions.

Abstract: The invention is an improvement to a storage virtualization system that enables the system to determine a class of service for potential storage devices and allows a user, administrator, or application to select a minimum class of service for any given type of data. The class of service is based upon factors that reflect a potential storage device's reliability, such as the device type and historical uptime data. In a P2P environment, the class of service also includes additional factors, such as the type of attached processing unit and the type of operating system running the attached processing unit.

Abstract: A virtualization platform provides fault tolerance for a primary virtual machine by continuously transmitting checkpoint information of the primary virtual machine to a collector process, such as a backup virtual machine. When implemented on a hardware platform comprising a multi-processor that supports nested page tables, the virtualization platform leverages the nested page table support to quickly identify memory pages that have been modified between checkpoints. The backup virtual machine provides feedback information to assist the virtualization platform in identifying candidate memory pages for transmitting actual modifications to the memory pages rather than the entire memory page as part of the checkpoint information. The virtualization platform further maintains a modification history data structure to identify memory pages that can be transmitted simultaneous with the execution of the primary virtual machine rather than while the primary virtual machine has been stunned.

Abstract: Systems and methods are provided that utilize non-shared page tables to allow an accelerator device to share physical memory of a computer system that is managed by and operates under control of an operating system. The computer system can include a multi-core central processor unit. The accelerator device can be, for example, an isolated core processor device of the multi-core central processor unit that is sequestered for use independently of the operating system, or an external device that is communicatively coupled to the computer system.

Abstract: REUT (Robust Electrical Unified Testing) for memory links is introduced which speeds testing, tool development, and debug. In addition it provides training hooks that have enough performance to be used by BIOS to train parameters and conditions that have not been possible with past implementations. Address pattern generation circuitry is also disclosed.

Abstract: A binary memory image in system is modified. The system may or may not already have virtual memory management enabled. Virtual memory management is enabled and/or modified by inserting a sub-OS virtual memory management layer in the binary memory image. Part of the binary memory image may be compressed to make room for the sub-OS virtual memory management layer.

Abstract: Systems and methods are provided that utilize shared page tables to allow an accelerator device to share physical memory of a computer system that is managed by and operates under control of an operating system. The computer system can include a multi-core central processor unit. The accelerator device can be, for example, an isolated core processor device of the multi-core central processor unit that is sequestered for use independently of the operating system, or an external device that is communicatively coupled to the computer system.

Abstract: A system for allocating and de-allocating registers of a processor. The system includes a register file having plurality of physical registers and a first table coupled to the register file for mapping virtual register IDs to physical register IDs. A second table is coupled to the register file for determining whether a virtual register ID has a physical register mapped to it in a cycle. The first table and the second table enable physical registers of the register file to be allocated and de-allocated on a cycle-by-cycle basis to support execution of instructions by the processor.

Abstract: In one embodiment of the invention, the exit and/or entry process in a nested virtualized environment is made more efficient. For example, a layer 0 (L0) virtual machine manager (VMM) may emulate a layer 2 (L2) guest interrupt directly, rather than indirectly through a layer 1 (L1) VMM. This direct emulation may occur by, for example, sharing a virtual state (e.g., virtual CPU state, virtual Device state, and/or virtual physical Memory state) between the L1 VMM and the L0 VMM. As another example, L1 VMM information (e.g., L2 physical to machine address translation table) may be shared between the L1 VMM and the L0 VMM.

Abstract: A computer system may comprise a computer platform and input-output devices. The computer platform may include a plurality of heterogeneous processors comprising a central processing unit (CPU) and a graphics processing unit) GPU and a shared virtual memory supported by a physical private memory space of at least one heterogeneous processor or a physical shared memory shared by the heterogeneous processor. The CPU (producer) may create shared multi-version data and store such shared multi-version data in the physical private memory space or the physical shared memory. The GPU (consumer) may acquire or access the shared multi-version data.

Abstract: A method of managing a memory having stored elements that are organized in a hierarchy, each having a header containing individual identity information and a body containing data, the identity information of each element being encoded on a plurality of bits each of which can take a first value or a second value. The identity information of each element is obtained by repeating the identity information of an element constituting a direct antecedent of the element in question in the hierarchy, and in said identity information of the antecedent, by changing the value of a first value bit that follows the last second value bit in a direction for reading the identity information.

Abstract: In general, this disclosure describes techniques of storing data in and retrieving data from a cache of a computing device. More specifically, techniques are described for utilizing a “perfect hash” function to implement an associative cache within a computing device. That is, the associative cache implements a fully associative map between a predetermined set of addresses and data values, employing only a single tag fetch comparison.

Abstract: One embodiment includes a personal computer device comprising at least one machine to execute a primary user operating system, a first physical memory to be used by the primary user operating system, at least one appliance operating system that is independent from the primary user operating system, a second physical memory to be sequestered from the primary user operating system and an access violation monitor to restrict access from the at least one appliance operating system to the second physical memory, wherein the access violation monitor is to run only when the at least one appliance operating system is invoked and at least one appliance operating system is to be invoked only after the primary user operating system has been suspended to a standby state.

Abstract: Asynchronous file operations in a scalable multi-node file system cache for a remote cluster file system, is provided. One implementation involves maintaining a scalable multi-node file system cache in a local cluster file system, and caching local file data in the cache by fetching file data on demand from the remote cluster file system into the cache over the network. The local file data corresponds to file data in the remote cluster file system. Local file information is asynchronously committed from the cache to the remote cluster file system over the network.

Abstract: Techniques are disclosed for sharing programmatic modules among isolated virtual machines. A master JVM process loads data from a programmatic module, storing certain elements of that data into its private memory region, and storing other elements of that data into a “read-only” area of a shareable memory region. The master JVM process copies loaded data from its private memory region into a “read/write” area of the shareable memory region. Instead of re-loading the data from the programmatic module, other JVM processes map to the read-only area and also copy the loaded data from the read/write area into their own private memory regions. The private memory areas of all of the JVM processes begin at the same virtual memory address, so references between read-only data and copied data are preserved correctly. As a result, multiple JVM processes start up faster, and memory is conserved by avoiding the redundant storage of shareable data.

Abstract: System, method, computer program product embodiments and combinations and sub-combinations thereof for managing data storage as an in-memory database in a database management system (DBMS) are provided. In an embodiment, a specialized database type is provided as a parameter of a native DBMS command. A database hosted entirely in-memory of the DBMS is formed when the specialized database type is specified.

Abstract: A method for accessing data stored in a distributed storage system is provided. The method comprises determining whether a copy of first data is stored in a distributed cache system, where data in the distributed cache system is stored in free storage space of the distributed storage system; accessing the copy of the first data from the distributed cache system if the copy of the first data is stored in a first data storage medium at a first computing system in a network; and requesting a second computing system in the network to access the copy of the first data from the distributed cache system if the copy of the first data is stored in a second data storage medium at the second computing system. If the copy of the first data is not stored in the distributed cache system, the first data is accessed from the distributed storage system.

Abstract: According to one embodiment, a computer system is disclosed. The computer system includes a processor, a chipset coupled to the processor and a memory coupled to the chipset. The chipset translates partitioned virtual machine memory addresses received from the processor to page level addresses.

Abstract: A mechanism for live migration of virtual machines (VMs) with memory optimizations is disclosed. A method of embodiments of the invention includes receiving a hash value for each of one or more memory pages of a migrating VM from a source host machine, obtaining a hash value for each of one or more memory pages hosted by a target host machine, and comparing the received hash values with the obtained hash values for matches. The method further comprises for each of the received hash values that do not match any of the obtained hash values, sending a negative acknowledgment to the source host machine for that hash value, and for each of the received hash values that do match any of the obtained hash values, using a memory page associated with the matching hash value at the target host machine for the migrating VM.

Abstract: A volume manager I/O method and system. The method includes determining a storage extent mapping of storage functionality of a plurality of storage devices and generating a logical disk extent based on the storage extent mapping. The logical disk extent is exported to a volume device component that is communicatively coupled to implement I/O for an application. An I/O request from the application is received via the volume device component. The I/O request is executed in accordance with the logical disk extent.

Abstract: Embodiments of various systems, methods, and computer readable media are disclosed herein for a system for managing media content.

Abstract: A data storage method for storing data into a flash memory chip is provided. The flash memory chip has a plurality of physical addresses, and these physical addresses include a plurality of fast physical addresses and a plurality of slow physical addresses. In the data storage method, the usage rate of the physical addresses is monitored. When the usage rate is not larger than a usage rate threshold value, only the fast physical addresses are used for storing the data into the flash memory chip. When the usage rate is larger than the usage rate threshold value, the fast physical addresses and the slow physical addresses are used for storing the data into the flash memory chip. Thereby, the speed of storing data into the flash memory chip is effectively increased.

Abstract: A method for operating an electronic control unit during a calibration phase; the method contemplating the steps of: dividing an area of a FLASH storage memory connected to a microprocessor in two pages between them identical and redundant, each of which is aimed at storing all the calibration parameters used by a control software; and using the two pages alternatively so that a first page contains the values of the calibration parameters and is queried by the microprocessor, while a second page is cleared and made available to store the updated values of the calibration parameters.

Abstract: A system for managing network memory comprises a communication interface and a processor. The communication interface receives a status message from another appliance. The status message indicates an activity level of a faster memory and a slower memory associated with the other appliance. The communication interface also receives a data packet. The processor processes the status message to determine the activity level of the faster memory and the slower memory. The processor also processes the data packet to identify any matching data in the other appliance and estimate whether the matching data is stored in the faster memory based on the activity level. Based on the estimate, the processor determines whether to generate an instruction to retrieve the matching data.

Abstract: A queue descriptor including a head pointer pointing to the first element in a queue and a tail pointer pointing to the last element in the queue is stored in memory. In response to a command to perform an enqueue or dequeue operation with respect to the queue, fetching from the memory to a cache only one of either the head pointer or tail pointer and returning to the memory from the cache portions of the queue descriptor modified by the operation.

Abstract: A virtual system comprises hardware, a virtualization layer virtualizing the hardware, a virtual machine monitor, a user domain operating using the virtualized hardware, and a root domain operating using the virtualized hardware and managing the user domain. The virtual machine monitor analyzes an operation performed by the user domain in real time and stores resulting analysis information in the root domain.

Abstract: This invention provides a storage system to store data used by computers. A storage system coupled to a computer and a management apparatus, includes storage devices accessed by the computer and a control unit that controls the storage devices, in which the control unit performs the following operations: setting, in the storage devices, a first virtual device including a first logical device; setting a second virtual device which including a second logical device, which is a virtual volume accessed by the computer; allocating an address of the first logical device to the second logical device; and changing the allocation to change storage areas of the virtual volume.

Abstract: A cross-logical entity group is created that includes one or more accelerators to be shared by a plurality of logical entities. Instantiated on the accelerators are functions that are common across multiple logical entities. The functions to be instantiated are determined, for instance, dynamically during run-time.

Abstract: A method for managing memory in a nested virtualization environment is provided. The method comprises implementing a first virtual machine (VM) for a first software such that a first guest memory is allocated to the first software; maintaining a first data structure to translate one or more memory addresses in the first guest memory to corresponding memory addresses in a physical memory; maintaining a second data structure to translate one or more memory addresses in the second guest memory to corresponding memory addresses in the physical memory. The first software implements a second VM for a second software such that a second guest memory is allocated to the second software and maintains a third data structure to translate one or more memory addresses in the second guest memory to corresponding memory addresses in the first guest memory.

Abstract: A storage area network can include a storage virtualization entity—intelligent storage application resource (iSAR)—either as a separate device in the fabric, or as an integrated module in one or more switches within the fabric. All I/O operations can be re-directed to iSAR for processing. iSAR can segment virtual storage and physical storage into units, where each unit of the virtual storage is mapped to a single unit in physical storage. Data associated with incoming I/O operation can be compressed before being stored in physical storage. iSAR includes overflow reserve storage at the block, sub-page and page level to accommodate changes in compressed data size on subsequent I/O operations. These measures can improve I/O performance and reduce fragmentation. iSAR can also employ deduplication of incoming data stored on physical storage to improve storage efficiency.

Abstract: In a computer system including a plurality of data storage apparatuses and a management computer, a given data storage apparatus, upon receipt of a control request for a local data storage apparatus from a management computer, accesses the hierarchical relation information between the storage areas in the local data storage apparatus and the storage areas of the other data storage apparatuses, and in the case where a storage area in the local data storage apparatus is set to correspond to a level lower than the other data storage apparatuses, transmits an approval request to the other data storage apparatuses. The given data storage apparatus, upon receipt of the approval from the other data storage apparatuses, executes the control request of the management computer.

Abstract: An input-output memory management unit (IOMMU) and method for tracking memory pages during virtual-machine migration are generally described herein. The IOMMU includes an IOMMU manager to service address translation requests associated with memory pages received from a plurality of I/O devices, and a translation request filter to identify translations previously requested from a translation manager. The IOMMU also includes a device context table to identify whether virtual-machine migration is enabled for memory pages associated with virtual addresses identified in received address translation requests. Based on information in the device context table, the IOMMU manager may send a virtual page identifier to the translation manager identifying a virtual page when virtual-machine migration is enabled to indicate that the virtual page has been accessed. The IOMMU manager refrains from sending the virtual page identifier to the translation manager when the virtual page is listed in the translation request filter.

Abstract: A mobile communication terminal having a function of managing multimedia data is provided, including: a main memory including a multimedia database storing the multimedia data; a signal processor converting the multimedia data stored in the main memory into data of a format suitable to be output to a display of the mobile communication terminal; a back_end chip which processes the multimedia data outputted from the signal processor, stores digest information of multimedia data upon occurrence of an update event of the multimedia data, and provides the stored digest information upon receiving a signal of requesting the digest information to be synchronized; and a front_end chip including a controller which requests the digest information stored in the back_end chip, compares and synchronizes the digest information offered from the back_end chip and digest information stored in advance in the front_end chip.

Abstract: A three-tiered TLB architecture in a multithreading processor that concurrently executes multiple instruction threads is provided. A macro-TLB caches address translation information for memory pages for all the threads. A micro-TLB caches the translation information for a subset of the memory pages cached in the macro-TLB. A respective nano-TLB for each of the threads caches translation information only for the respective thread. The nano-TLBs also include replacement information to indicate which entries in the nano-TLB/micro-TLB hold recently used translation information for the respective thread. Based on the replacement information, recently used information is copied to the nano-TLB if evicted from the micro-TLB.