Abstract: One embodiment of the present invention sets forth a technique for computing virtual addresses for accessing thread data. Components of the complete virtual address for a thread group are used to determine whether or not a cache line corresponding to the complete virtual address is not allocated in the cache. Actual computation of the complete virtual address is deferred until after determining that a cache line corresponding to the complete virtual address is not allocated in the cache.

Abstract: A memory system includes a volatile memory and a non-volatile memory. The volatile memory is configured as a random access memory or cache for the nonvolatile memory. Wear concentration logic targets one or more selected devices of the nonvolatile memory for accelerated wear.

Abstract: Provided is an XML processing device capable of describing, using conventional XML processing language, a method of processing also an asynchronously inputted XML. The XML processing device converts, according to a predetermined rule, the XML inputted asynchronously from outside and outputs the XML. The XML processing device is characterized by including an XML conversion module which performs XML conversion of the XML inputted according to the rule, an output destination interpretation module which interprets an output destination described in the converted XML, and an output distribution module which allows the XML to be outputted to the output destination interpreted by the output destination interpretation module.

Abstract: Provided is a data acquisition method including the steps of selecting a link destination whose display is at least partially located in a region of a display screen corresponding to an operating tool, acquiring, before the link destination is selected, information relating to a layout of a display screen and display control data including at least a structural unit in which the information is written, the display control data and the information existing at the link destination, extracting structural units included in the display control data, in a case the prefetched link destination is selected, generating first structured data by linking the extracted structural units in which information involving script-process isn't written, generating second structured data by linking the extracted structural units, displaying a display screen using the first structured data, and redisplaying, at a stage the second structured data is generated, the display screen using the second structured data.

Abstract: In some embodiments, the invention involves utilizing a tree merge sort in a platform to minimize cache reads/writes when sorting large amounts of data. An embodiment uses blocks of pre-sorted data residing in “leaf nodes” residing in memory storage. A pre-sorted block of data from each leaf node is read from memory and stored in faster cache memory. A tree merge sort is performed on the nodes that are cache resident until a block of data migrates to a root node. Sorted blocks reaching the root node are written to memory storage in an output list until all pre-sorted data blocks have been moved to cache and merged upward to the root. The completed output list in memory storage is a list of the fully sorted data. Other embodiments are described and claimed.

Abstract: A virtual machine is suspended and quickly restarted while maintaining the VM's state. The method is quick enough so that network connections are maintained across the restart and the guest operating system and guest applications running in the VM are not aware of the restart. As a result, users and clients connected to the VM do not notice any downtime or disruption to the VM. After suspension and before the restart, VM configuration changes that would not be possible or be very difficult through code changes alone while the VM was running can be made.

Abstract: A memory and storage device includes a data management system for transferring data units referenced by logical addresses. The data management system maps the logical addresses to sequential virtual addresses according to the order the data units are received. The data management system also maps the sequential virtual addresses to sequential physical addresses in a memory block of a memory device. Additionally, the data management system can modify a data unit in the memory block by copying any other valid data units in the memory block to another memory block and writing the modified data unit into this other memory block. The data management system writes the valid data units and the modified data unit into sequential physical addresses of this other memory block.

Abstract: A cache memory has a set associative scheme and includes a plurality of ways made up of entries, each entry holding data and a tag; a first holding unit holds, for each way, a priority attribute that indicates a type of data to be preferentially stored in that way; a second holding unit, included in a first way among the ways, holds, for each entry of the first way, a data attribute that indicates a type of data held in that entry; and a control unit replaces control on the entries by prioritizing a way whose priority attribute held by the first holding unit matches a data attribute outputted from a processor, wherein the control unit is further operable to store data into the entry of the way other than the first way.

Abstract: A computer program communicates with a partition manager in the logical partition where the computer program is run. When resource allocation in the logical partition dynamically changes, the partition manager notifies the computer program of the configuration change. The computer program may autonomically adjust one or more configuration settings that affect performance of the computer program to dynamically tune the computer program to optimal performance each time the allocation of resources within the logical partition changes. The partition manager may notify the computer program of an impending change in resource allocation in the logical partition that runs the computer program, which allows the computer program to reconfigure its configuration setting(s) before the partition manager changes the resource allocation in the logical partition.

Abstract: A method for preloading into a hierarchy of memories, bitstreams representing the configuration information for a reconfigurable processing system including several processing units. The method includes an off-execution step of determining tasks that can be executed on a processing unit subsequently to the execution of a given task. The method also includes, during execution of the given task, computing a priority for each of the tasks that can be executed. The priority depends on information relating to the current execution of the given task. The method also includes, during execution of the given task, sorting the tasks that can be executed in the order of their priorities. The method also includes, during execution of the given task, preloading into the memory, bitstreams representing the information of the configurations for the execution of the tasks that can be executed, while favoring the tasks whose priority is the highest.

Abstract: A system and corresponding method virtualizes a real-time clock in the presence of a time-disrupting event. The real-time clock is used with physical machines and includes a single time source within each of the physical machines. The system is implemented in one or more programmable devices, which may be hardware and/or software devices, or a combination of hardware and software devices. The physical machines include one or more virtual machines. The system includes an offset module that determines a time difference offset between a virtual interrupt timer counter (ITCV) associated with a virtual machine and a physical interrupt timer counter (ITCP) associated with a physical machine. The system also includes a virtual machine monitor that computes one or more first time adjustments based on the offset and applies the adjustments to eliminate at least a first part of the offset.

Abstract: An apparatus for real-time performance management of a virtualized storage system operable in a network having managed physical storage and virtual storage presented by an in-band virtualization controller comprises: a monitoring component operable in communication with the network for acquiring performance data from the managed physical storage and the virtual storage; and a cache controller component responsive to the monitoring component for adjusting cache parameters for the virtual storage. The apparatus may further comprise a queue controller component responsive to the monitoring component for adjusting queue parameters for the managed physical storage. The monitoring component, the cache controller component and the queue controller component may be configured to operate periodically during operation of the virtualized storage system.

Abstract: A method in one example implementation includes identifying an address space in a memory element of a system configured to operate in a virtual environment. The address space includes at least one system address, and the address space is provided to a virtual machine monitor. The method also includes generating a page table entry for the system address in a shadow page table stored in the virtual machine monitor in response to a guest operating system initiating a process. The page table entry is marked as a page not being present in order to trigger a page fault for a system address access from the guest operating system. In more specific embodiments, the method may include evaluating a page fault to determine access to the address space, where access to a writeable area of the memory element is denied.

Abstract: Provided is a storage system having improved access performance. The storage system includes: a hard disk drive, and a storage controller for reading/writing data from/to the hard disk drive, the storage controller including: at least one interface connected to a host computer through a network; and a plurality of processors connected to the interface through an internal network. The storage system is characterized in that: the processor provides at least one logical access port to the host computer; and the interface stores routing information including a processor which processes an access request addressed to the logical access port, extracts an address from the received access request upon reception of the access request from the host computer, specifies the processor which processes the received access request based on the routing information and the extracted address, and transfers the received access request to the specified processor.

Abstract: A storage apparatus includes a storage unit and a controller, wherein control of inputting/outputting data from/to a device provided in said storage unit is executed in accordance with a request received by said storage apparatus. An actual device of the storage apparatus corresponds to a virtual device which is external to said storage apparatus. The controller operates to perform a process for mapping an actual device address corresponding to a virtual device address, in accordance with a specification of the actual device to be mounted or unmounted to correspond to the virtual device, and storing and retaining mapping information obtained from the mapping in a first table. The controller also performs data input/output process for receiving, an access request for data input/output in which said virtual device address is specified, obtaining the actual device address mapped to said specified virtual device address in said first table, and accessing the actual device by said obtained actual device address.

Abstract: A storage device that includes a flash memory device providing a storage medium, a cache memory for use with the flash memory device, and a control circuit. In the storage device, based on a write command and provided address information, the control circuit selects either the flash memory device or the cache memory as a writing destination of input data.

Abstract: A mechanism is provided for performing secure recursive virtualization of a computer system. A portion of memory is allocated by a virtual machine monitor (VMM) or an operating system (OS) to a new domain. An initial program for the new domain is loaded into the portion of memory. Secure recursive virtualization firmware (SVF) in the data processing system is called to request that the new domain be generated. A determination is made as to whether the call is from a privileged domain or a non-privileged domain. Responsive to the request being from a privileged domain, all access to the new domain is removed from any other domain in the data processing system. Responsive to receiving an indication that the new domain has been generated, an execution of the initial program is scheduled.

Abstract: A virtual memory system implementing the invention provides concurrent access to translations for virtual addresses from multiple address spaces. One embodiment of the invention is implemented in a virtual computer system, in which a virtual machine monitor supports a virtual machine. In this embodiment, the invention provides concurrent access to translations for virtual addresses from the respective address spaces of both the virtual machine monitor and the virtual machine. Multiple page tables contain the translations for the multiple address spaces. Information about an operating state of the computer system, as well as an address space identifier, are used to determine whether, and under what circumstances, an attempted memory access is permissible. If the attempted memory access is permissible, the address space identifier is also used to determine which of the multiple page tables contains the translation for the attempted memory access.

Abstract: A dispersed storage device within a dispersed storage network includes a processing module for determining whether to add a new generation for a vault, in which the vault identifies at least one user having data to be stored. When the new generation is to be added to the vault, the processing module further assigns a vault generation identifier to the new generation, assigns a virtual address range of a virtual memory associated with the dispersed storage network to the new generation and maps the virtual address range to a physical memory for storage of the data therein.

Abstract: Roughly described, a data processing system comprises a central processing unit and a split network interface functionality, the split network interface functionality comprising: a first sub-unit collocated with the central processing unit and configured to at least partially form a series of network data packets for transmission to a network endpoint by generating data link layer information for each of those packets; and a second sub-unit external to the central processing unit and coupled to the central processing unit via an interconnect, the second sub-unit being configured to physically signal the series of network data packets over a network.

Abstract: Disclosed is a method of operating a data storage system. The method comprises generating first metadata describing storage of a volume of data in a first storage volume, storing the volume of data within a second storage volume, generating second metadata describing storage of the volume of data in the second storage volume, and processing the first metadata and the second metadata to increase sparseness of the volume of data stored in the second storage volume.

Abstract: Embodiments of the present invention are directed to systems and methods of controlling data transfer between a host system and a plurality of storage devices. One embodiment is directed to a virtualization controller for controlling data transfer between a host system and a plurality of storage devices. The virtualization controller comprises a plurality of first ports for connection with the plurality of storage devices each having a storage area to store data; a second port for connection with the host system; a processor; and a memory configured to store volume mapping information which correlates first identification information used by the host system to access a first storage area in one of the storage devices, with second identification information for identifying the first storage area, the correlation being used by the processor to access the first storage area.

Abstract: An information processing apparatus includes: a memory that stores a process identifier for identifying a process uniquely, a virtual address which is an address of a memory space available in the process, a physical address corresponding to the virtual address, and a continuous memory capacity assigned to the process so as to be associated with each other; and a memory capacity setting section that, when changing a process to an executable state, sets the continuous memory capacity to be stored in the memory. The memory capacity setting section determines the continuous memory capacity based on a memory capacity that the process requires; a memory capacity of an unused continuous region in a physical memory; and a memory capacity based on restriction of memory size dependent on a central processing unit in a computer.

Abstract: Systems and methods are provided for testing a non-volatile memory, such as a flash memory. The non-volatile memory may be virtually partitioned into a test region and a general purpose region. A test application may be stored in the general purpose region, and the test application can be executed to run a test of the memory locations in the test region. The results of the test may be stored in the general purpose region. At the completion of the test, the test results may be provided from the general purpose region and displayed to a user. The virtual partitions may be removed prior to shipping the electronic device for distribution.

Abstract: Loading data from a computer memory system is disclosed. A memory system is provided, wherein some or all data stored in the memory system is organized as one or more pointer-linked data structures. One or more iterator registers are provided. A first pointer chain is loaded, having two or more pointers leading to a first element of a selected pointer-linked data structure to a selected iterator register. A second pointer chain is loaded, having two or more pointers leading to a second element of the selected pointer-linked data structure to the selected iterator register. The loading of the second pointer chain reuses portions of the first pointer chain that are common with the second pointer chain. Modifying data stored in a computer memory system is disclosed. A memory system is provided. One or more iterator registers are provided, wherein the iterator registers each include two or more pointer fields for storing two or more pointers that form a pointer chain leading to a data element.

Abstract: Methods and apparatus for controlling hierarchical cache memories permit controlling a first level cache memory including a plurality of cache lines and controlling a next lower level cache memory including a plurality of cache lines. An additional memory may be associated with the next lower level cache memory and include a plurality of memory lines, the number of memory lines corresponding to the number of cache lines in a way set of the first level cache memory. Alternatively, the memory lines may include L-flags for multiple cache lines of each way set of the next lower level cache memory. L-flags associated with a given index plus any index offset from the first level cache memory may be contained in a single memory line of the additional memory.

Abstract: A license managing device sets a security area for storing a license file, maintains the security area as an encoded file in an inactive state of the security area by encoding the security area, maintains the security area as a directory in an active state of the security area by decoding the security area, and encodes a license file by using a file encoding key according to the user's request and stores the same in a security area in an active state of the security area.

Abstract: Provided is a performance optimization system that can identify a case where the impact on performance is large even when the number of cache misses is small.

Abstract: Operating system virtual memory management for hardware transactional memory. A method may be performed in a computing environment where an application running on a first hardware thread has been in a hardware transaction, with transactional memory hardware state in cache entries correlated by memory hardware when data is read from or written to data cache entries. The data cache entries are correlated to physical addresses in a first physical page mapped from a first virtual page in a virtual memory page table. The method includes an operating system deciding to unmap the first virtual page. As a result, the operating system removes the mapping of the first virtual page to the first physical page from the virtual memory page table. As a result, the operating system performs an action to discard transactional memory hardware state for at least the first physical page. Embodiments may further suspend hardware transactions in kernel mode.

Abstract: A system and method is illustrated for identifying an Input/Output (I/O) driver module, using a hypervisor, to receive a read command to read a virtual memory page from a remote memory location. Further, the system and method includes reading the remote virtual memory page, using the I/O driver module, into a memory buffer managed by the I/O driver module. Additionally, the system and method includes storing the virtual memory page in the memory buffer to a persistent storage device. The system and method also includes identifying a remote super page, using a hypervisor, the remote super page including a remote sub page. Additionally, the system and method includes identifying a local super page, using the hypervisor, the local super page including a local sub page. Further, the system and method includes swapping the local sub page for the remote sub page, using the hypervisor, the swapping occurring over a network.

Abstract: Managing operations in a first compute node of a multi-computer system. A remote write may be received to a first address of a remote compute node. A first data structure entry may be created in a data structure, which may include the first address and status information indicating that the remote write has been received. Upon determining that the local cache of the first compute node has been updated with the remote write, the remote write may be issued to the remote compute node. Accordingly, the first data structure entry may be released upon completion of the remote write.

Abstract: Main memory is managed by receiving a command from an application to read data associated with a virtual address that is mapped to the main memory. A memory controller determines that the virtual address is mapped to one of the symmetric memory components of the main memory, and accesses memory use characteristics indicating how the data associated with the virtual address has been accessed, The memory controller determines that the data associated with the virtual address has access characteristics suited to an asymmetric memory component of the main memory and loads the data associated with the virtual address to the asymmetric memory component of the main memory. After the loading and using the memory management unit, a command is received from the application to read the data associated with the virtual address, and the data associated with the virtual address is retrieved from the asymmetric memory component.

Abstract: Provided are a data storage medium accessing method of accessing a data storage medium of a data storage device according to a virtual address (VA), the data storage device to access the data storage medium according to the VA, and a computer readable recording medium having recorded thereon a program to access the data storage medium accessing method.

Abstract: A multiprocessor computer system comprises a first node operable to access memory local to a remote node by receiving a virtual memory address from a requesting entity in node logic in the first node. The first node creates a network address from the virtual address received in the node logic, where the network address is in a larger address space than the virtual memory address, and sends a fast memory access request from the first node to a network node identified in the network address.

Abstract: A virtualization system is described herein that facilitates communication between a virtualized application and a host operating system to allow the application to correctly access resources referenced by the application. When the operating system creates a virtualized application process, the virtualization system annotates a data structure associated with the process with an identifier that identifies the virtualized application environment associated with the process. When operating system components make requests on behalf of the originating virtual process, a virtualization driver checks the data structure associated with the process to determine that the helper process is doing work on behalf of the virtualized application process. Upon discovering that the thread is doing virtual process work, the virtualization driver directs the helper process's thread to the virtual application's resources, allowing the helper process to accomplish the requested work with the correct data.

Abstract: A hierarchical memory device having multiple interfaces with different memory formats includes a Phase Change Memory (PCM). An input port and an output port connect the hierarchical memory device in a daisy-chain hierarchy or a hierarchical tree structure with other memories. Standard non-hierarchical memory devices can also attach to the output port of the hierarchical memory device.

Abstract: Several methods and a system of an extended virtual memory system in a computer cluster are disclosed. In one aspect, a method of computer network is disclosed. The method of a computer network includes generating a virtual address space associated with a data of a local computer, translating the virtual address space to a local physical address space with a page table entry of the local computer, and declaring, with a remote memory management module of a remote computer, a set of remote kernel data structures to a local memory management module. The method also includes translating the virtual address space to a remote address of a remote memory with the local memory management module. The method may also include communicating a piece of data to the remote memory management module according to a protocol. The piece of data may be any data available on the remote computer.

Abstract: A computing system stores a database comprising pages. Each of the pages is the same size. When a page is requested, a block of virtual memory addresses is associated with the page and a set of physical data storage locations is committed to the block of virtual memory addresses. A copy of the page is then stored into the set of physical data storage locations. Physical data storage locations committed to the virtual memory addresses associated with available free space in the copy of the page are deallocated, thereby allowing reuse of these physical data storage locations. A reference to the copy of the page is then returned.

Abstract: Systems and methods to manage database data are provided. A particular method includes automatically identifying a plurality of storage devices. The storage devices include a first device of a first type and a second device of a second type. The first type includes a solid state memory device. The method may further identify a high priority data set of the database. A rebalancing operation is conducted that includes moving the high priority data set to the solid state memory device and substantially evening distribution of other data of the database among the storage devices.

Abstract: Methods for updating and recovering user data of a non-volatile memory array such as a flash memory are disclosed. An indication for indicating a mapping relationship for a logical address is established when original user data of the logical addresses is updated into new user data. The indication records new pointers, which record the mapping relationships between logical addresses and physical addresses storing the new user data of the logical addresses. Alternatively, the indication records memory positions of the non-volatile memory array which are defined as designated memory positions and a sequence for using these designated memory positions.

Abstract: In one embodiment, a mechanism for virtual logical volume management is disclosed. In one embodiment, a method for virtual logical volume management includes writing, by a virtual machine (VM) host server computing device, a control block to each of a plurality of network-capable physical storage devices and mapping, by the VM host server computing device, physical storage blocks of the plurality of network-capable physical storage devices to virtual storage blocks of a virtual storage pool by associating the physical storage blocks with the virtual storage blocks in the control block of the network-capable physical storage device housing the physical storage blocks being mapped.

Abstract: Techniques for managing virtual machine (VM) states are provided. Applications executing within a processing context of a VM communicate outside that processing context with a hypervisor or VM Monitor (VMM) to have the hypervisor perform host operations for the VM.

Abstract: Read requests to a commonly accessed storage volume are conditionally issued, depending on whether or not a requested data block is already stored in memory from a prior access or to be stored in memory upon completion of a pending request. A data structure is maintained in memory to track physical memory pages and to indicate for each physical memory page the corresponding location in the storage volume from which the contents of the physical memory were read and the number of virtual memory pages that are mapped thereto.

Abstract: One embodiment of the present invention is a method of interposing operations in a computational system that includes a virtualization system executable on an underlying hardware processor that natively supports one or more instructions that transition between host and guest execution modes.

Abstract: A system for storing data from an industrial control system having an industrial controller including a communication module and first memory containing data for controlling an industrial process is provided. The system comprises a computer separate from the industrial controller and having a second memory and an application for automatically accessing the data from the first memory of the industrial controller via the communication module and storing the data on the second memory.

Abstract: Techniques are described herein for managing data in a block-based flash memory device which avoid the need to perform sector erase operations each time data stored in the flash memory device is updated. As a result, a large number of write operations can be performed before a sector erase operation is needed. In addition, the block-based flash memory can emulate both programming and erasing on a byte-by-byte basis, like that provided by an EEPROM.

Abstract: In one embodiment, a system, comprises a first computer system comprising at least a first diskless server, at least a first RAID controller coupled to the first diskless server, at least a first storage pool coupled to the RAID controller, and a remote management server coupled to the RAID controller via a an out-of-band communication link. The remote management server comprises a boot management module which, when executed, initiates a command to instruct the RAID controller to create at least a first logical volume in a memory module coupled to the RAID controller, transmits the command to the RAID controller via the out-of-band communication link, and transmits a boot image from the remote management server to the RAID controller via the out-of-band communication link. The RAID controller creates the first logical volume for the boot image in response to the command, and stores the boot image in the first logical volume.

Abstract: Example embodiments are directed to a method of writing an Operating System (OS) image to a semiconductor device having a data storage device, an Application Specific Integrated Circuit (ASIC), and a non-volatile memory. The method includes initializing a DRAM interface of the ASIC using a boot loader, receiving the OS image input from a data writer to the semiconductor device through the DRAM interface; and writing the OS image into the non-volatile memory of the semiconductor device using a Flash Translation Layer (FTL) code.

Abstract: Methods and systems are presented for constructing biological-scale hierarchically structured cortical statistical memory systems using currently available fabrication technology and meta-stable switching devices. Learning content-addressable memory and statistical random access memory circuits are detailed. Additionally, local and global signal modulation of bottom-up and top-down processing for the initiation and direction of behavior is disclosed.

Abstract: A programmable processing device comprises a plurality of universal digital blocks (UDBs) in a UDB linear array. Each register in each UDB is associated with a plurality of memory addresses, where each memory address is from each of the different memory address spaces associated with different access mode widths of different digital peripheral functions. A digital peripheral function of an access mode width is mapped to one or more contiguous UDBs starting with a first UDB in the UDB linear array. Based on the access mode width, one of the associated memory addresses is chosen for the first UDB.