Abstract: The semiconductor structure includes a substrate, a deep well, a first doped region, a source/drain region, and a first heavily doped region. The substrate has a first conductivity type. The deep well has a second conductivity type disposed on the substrate. The first doped region has the first conductivity type disposed on the deep well. The source/drain region has the second conductivity type disposed on the first doped region. The first heavily doped region has the second conductivity type disposed in a first top region of the source/drain region, in which the first conductivity type is opposite to the second conductivity type.

Abstract: A semiconductor device may include a substrate including first regions and a second region between the first regions. Active fins may protrude from the substrate in the first regions. Each of the active fins may extend in a first direction parallel to an upper surface of the substrate. The active fins may be regularly arranged and spaced apart from each other in a second direction. First trenches may be at both edges of the second region. A protrusion may be between the first trenches. An upper surface of the protrusion may be lower than a bottom of the active fins. A first width in the second direction of one of the first trenches may be greater than 0.7 times a first pitch of the active fins that is a sum of a width of one of the active fins and a distance between adjacent ones of the active fins.

Abstract: A transistor device formed on a semiconductor-on-insulator (SOI) substrate including a bulk semiconductor layer, a buried insulation (BOX) layer positioned on the bulk semiconductor layer, and an active semiconductor layer positioned on the BOX layer. The transistor device includes: a gate structure, a sidewall spacer, and a source/drain region; a plurality of distinct openings extending through the active semiconductor layer of the SOI substrate in the source/drain region adjacent the sidewall spacer, each opening of the plurality of openings extending to a respective recess formed in the BOX layer of the SOI substrate in the source/drain region adjacent the sidewall space, wherein each recess extends under a portion of the active semiconductor layer; and an epitaxial (epi) semiconductor material disposed in the recesses in the BOX layer, in the plurality of openings through the active semiconductor layer, and over a surface of the active semiconductor layer.

Abstract: A method of controlling a substrate treatment apparatus including a chamber, a stage having elevation pins, a gas introducer disposed above the stage and introducing a treatment gas into the chamber, a first heating source heating the gas introducer, a stage elevator moving the stage up/down, and an elevator for elevation pins moving the elevation pins up/down, is provided. The method includes supporting a substrate having an oxide on the stage; etching the oxide using a treatment gas by supplying the treatment gas from the gas introducer; moving down the stage while maintaining a position of the substrate using the elevation pins; and sublimating a reaction product produced in etching the oxide by the first heating source.

Abstract: A method comprises providing a semiconductor alloy layer on a semiconductor substrate, forming a gate structure on the semiconductor alloy layer, forming source and drain regions in the semiconductor substrate on both sides of the gate structure, removing at least a portion of the semiconductor alloy layer overlying the source and drain regions, and forming a metal silicide region over the source and drain regions.

Abstract: According to various embodiments, a transistor device may include a semiconductor structure having a trench formed therein. The semiconductor structure may include a buffer layer and a barrier layer arranged over the buffer layer. The trench may extend at least to the buffer layer. The transistor device may include a source terminal, a drain terminal, and a gate terminal arranged between the source terminal and the drain terminal. The gate terminal may extend into the trench. The transistor device may include an electrode component. The electrode component may include an electrode. The electrode component may extend into the trench where the electrode component is separated from the gate terminal. The electrode component may contact a side wall of the trench.

Abstract: Apparatuses and methods to provide a patterned substrate are described. A plurality of patterned and spaced first lines and carbon material lines and formed on the substrate surface by selectively depositing and etching films extending in a first direction and films extending in a second direction that crosses the first direction to pattern the underlying structures.

Abstract: Semiconductor devices and methods are provided to fabricate FET devices. For example, a semiconductor device can include a functional gate structure on a channel region of a fin structure; and a source/drain region on each side of the functional gate structure. The functional gate structure has an insulator material abutting a portion of the sidewalls of the functional gate structure and the source drain region and the top surface of the fin. The functional gate structure further includes a dielectric top layer. The dielectric top layer seals an air gap between the top surface of the insulator material and the dielectric top layer.

Abstract: The invention discloses a method for improving bonding of dangling bonds of silicon atoms. A surface of a wafer is oxidized to form a silicon oxide layer. The upper surface of the silicon oxide layer has a dangling bond. A dielectric layer is disposed on the upper surface of the silicon oxide layer, which is then subjected to an oxygen-enriched oxidation treatment at a preset first temperature. A protective layer is disposed on the upper surface of the dielectric layer. The wafer is then subjected to an annealing treatment. By passing oxidizing gas through the surface of the protective layer, oxygen ions in the oxidizing gas penetrate the dielectric layer to reach wafer surface. After high-temperature annealing treatment, the unsaturated bonds of the silicon atoms are bonded to the oxygen ions on the wafer surface, thereby improving the bonding of the dangling bonds on the wafer surface.

Abstract: A semiconductor structure is provided that includes a bulk semiconductor substrate of a first semiconductor material. The structure further includes a plurality of fin pedestal structures of a second semiconductor material located on the bulk semiconductor substrate of the first semiconductor material, wherein the second semiconductor material is different from the first semiconductor material. In accordance with the present application, each fin pedestal structure includes a pair of spaced apart semiconductor fins of the second semiconductor material.

Abstract: A manufacturing method of a semiconductor device includes the following steps. A semiconductor substrate including at least one fin structure is provided. A gate material layer is formed on the semiconductor substrate, and the fin structure is covered by the gate material layer. A trench is formed partly in the gate material layer and partly in the fin structure. An isolation structure is formed partly in the trench and partly outside the trench. At least one gate structure is formed straddling the fin structure by patterning the gate material layer after the step of forming the isolation structure. A top surface of the isolation structure is higher than a top surface of the gate structure in a vertical direction for enhancing the isolation performance of the isolation structure. A sidewall spacer is formed on sidewalls of the isolation structure, and there is no gate structure formed on the isolation structure.

Abstract: A semiconductor structure and a method for fabricating the same. The structure includes a substrate, active fin structures, and non-active fin structures. The structure further includes isolation regions in contact with the active fin structures, and isolation regions in contact with the non-active fin structures. A first gate structure is in contact with the active fin structures and the isolation regions that are in contact with the active fin structures. A second gate structure is in contact with the non-active fin structures. The method includes forming an isolation region between fin structures. A mask is formed over active fin structures and dummy fin structures are then removed to form a plurality of trenches between the isolation regions. A nitride-based layer is formed in contact with isolation regions corresponding to the dummy fin structures. The nitride-based layer forms a non-active fin structure within each trench of the trenches.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to faceted epitaxial source/drain regions and methods of manufacture. The structure includes: a gate structure over a substrate; an L-shaped sidewall spacer located on sidewalls of the gate structure and extending over the substrate adjacent to the gate structure; and faceted diffusion regions on the substrate, adjacent to the L-shaped sidewall spacer.

Abstract: The present disclosure provides a semiconductor structure comprising one or more fins formed on a substrate and extending along a first direction; one or more gates formed on the one or more fins and extending along a second direction substantially perpendicular to the first direction, the one or more gates including an first isolation gate and at least one functional gate; source/drain features formed on two sides of each of the one or more gates; an interlayer dielectric (ILD) layer formed on the source/drain features and forming a coplanar top surface with the first isolation gate. A first height of the first isolation gate is greater than a second height of each of the at least one functional gate.

Abstract: A method for manufacturing a semiconductor device includes forming a first high-k dielectric layer on a semiconductor substrate; forming a second high-k dielectric layer on the first high-k dielectric layer, in which the second high-k dielectric layer includes a material different from a material of the first high-k dielectric layer; annealing the first and second high-k dielectric layers, such that the first and second high-k dielectric layers are inter-diffused; and forming a gate electrode over the second high-k dielectric layer.

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate. The semiconductor device structure also includes a gate stack covering a portion of the fin structure, and the gate stack includes a work function layer and a metal filling over the work function layer. The semiconductor device structure further includes an isolation element over the semiconductor substrate and adjacent to the gate stack. The isolation element is in direct contact with the work function layer and the metal filling.

Abstract: A semiconductor device includes a PMOS FinFET and an NMOS FinFET. The PMOS FinFET includes a substrate, a silicon germanium layer disposed over the substrate, a silicon layer disposed over the silicon germanium layer, and a PMOS fin disposed over the silicon layer. The PMOS fin contains silicon germanium. The NMOS FinFET includes the substrate, a a silicon germanium oxide layer disposed over the substrate, a silicon oxide layer disposed over the silicon germanium oxide layer, and an NMOS fin disposed over the silicon oxide layer. The NMOS fin contains silicon. The silicon germanium oxide layer and the silicon oxide layer collectively define a concave recess in a horizontal direction. The concave recess is partially disposed below the NMOS fin.

Abstract: Semiconductor devices and methods of forming the same include forming a first channel region on a first semiconductor region. A second channel region is formed on a second semiconductor region. The second semiconductor region is formed from a semiconductor material that is different from a semiconductor material of the first semiconductor region. A semiconductor cap is formed on one or more of the first and second channel regions. A gate dielectric layer is formed over the nitrogen-containing layer. A gate is formed on the gate dielectric.

Abstract: A methodology for forming a fin field effect transistor (FinFET) includes the co-integration of various isolation structures, including gate cut and shallow diffusion break isolation structures that are formed with common masking and etching steps. Following an additional patterning step to provide segmentation for source/drain conductive contacts, a single deposition step is used to form an isolation dielectric layer within each of gate cut openings, shallow diffusion break openings and cavities over shallow trench isolation between device active areas.

Abstract: A fin field effect transistor (FinFET) device structure with dummy fin structures and method for forming the same are provided. The FinFET device structure includes an isolation structure over a substrate and a first fin structure extended above the isolation structure. The FinFET device structure includes a second fin structure embedded in the isolation structure and a liner layer formed on sidewalls of the first fin structures and sidewalls of the second fin structures. The FinFET device structure also includes a material layer formed over the second fin structures, and the material layer and the isolation structure are made of different materials.

Abstract: A 3-D flash memory device and its manufacturing method, relating to semiconductor technology. The manufacturing method comprises: providing a semiconductor structure comprising a substrate, a first insulation layer on the substrate, a fin structure comprising a first gate layer and a second insulation layer stacked alternately over each other on the first insulation layer, a third insulation layer on two sides of the fin structure, with the first gate layer being surrounded by the first, the second and the third insulation layers, and at least one channel layer covering the fin structure and the third insulation layer; and forming a groove by etching the channel layer, the second insulation layer and the first gate layer along an extension direction of the fin structure. This inventive concept improves the storage density of a 3-D flash memory device.

Abstract: A semiconductor structure and a method for fabricating the same. The structure includes a substrate, active fin structures, and non-active fin structures. The structure further includes isolation regions in contact with the active fin structures, and isolation regions in contact with the non-active fin structures. A first gate structure is in contact with the active fin structures and the isolation regions that are in contact with the active fin structures. A second gate structure is in contact with the non-active fin structures. The method includes forming an isolation region between fin structures. A mask is formed over active fin structures and dummy fin structures are then removed to form a plurality of trenches between the isolation regions. A nitride-based layer is formed in contact with isolation regions corresponding to the dummy fin structures. The nitride-based layer forms a non-active fin structure within each trench of the trenches.

Abstract: A semiconductor device includes a fin extending along a first direction over a substrate, and a gate structure extending in a second direction overlying the fin. The gate structure includes a gate dielectric layer overlying the fin, a gate electrode overlying the gate dielectric layer, and insulating gate sidewalls on opposing lateral surfaces of the gate electrode extending along the second direction. A source/drain region is formed in the fin in a region adjacent the gate electrode structure, and a stressor layer is between the source/drain region and the semiconductor substrate. The stressor layer includes GeSn or SiGeSn containing 1019 atoms cm?3 or less of a dopant, and a portion of the fin under the gate structure is a channel region.

Abstract: A manufacturing method of a semiconductor device includes the following steps. A semiconductor substrate including at least one fin structure is provided. A gate material layer is formed on the semiconductor substrate, and the fin structure is covered by the gate material layer. A trench is formed partly in the gate material layer and partly in the fin structure. An isolation structure is formed partly in the trench and partly outside the trench. At least one gate structure is formed straddling the fin structure by patterning the gate material layer after the step of forming the isolation structure. A top surface of the isolation structure is higher than a top surface of the gate structure in a vertical direction for enhancing the isolation performance of the isolation structure. A sidewall spacer is formed on sidewalls of the isolation structure, and there is no gate structure formed on the isolation structure.

Abstract: After forming a first functional gate stack located on a first body region of a first semiconductor material portion located in a first region of a substrate and a second functional gate stack located on a second body region of a second semiconductor material portion located in a second region of the substrate, a ferroelectric gate interconnect structure is formed connecting the first functional gate stack and the second functional gate stack. The ferroelectric gate interconnect structure includes a U-shaped bottom electrode structure, a U-shaped ferroelectric material liner and a top electrode structure.

Abstract: A method for fabricating a semiconductor structure includes providing a substrate including a device region, an isolation region, and a transition region between the device region and the isolation region, forming a plurality of fin structures on the device region of the substrate, forming a plurality of dummy fin structures on the transition region of the substrate, and forming an isolation structure on the device region, the isolation region, and the transition region of the substrate. The isolation structure further covers a portion of sidewall surfaces of the fin structures and the dummy fin structures. Moreover, the method includes forming a plurality of semiconductor devices on the fin structures in the device region after forming the isolation structure.

Abstract: The present disclosure provides a semiconductor structure comprising one or more fins formed on a substrate and extending along a first direction; one or more gates formed on the one or more fins and extending along a second direction substantially perpendicular to the first direction, the one or more gates including an first isolation gate and at least one functional gate; source/drain features formed on two sides of each of the one or more gates; an interlayer dielectric (ILD) layer formed on the source/drain features and forming a coplanar top surface with the first isolation gate. A first height of the first isolation gate is greater than a second height of each of the at least one functional gate.

Abstract: Methods form integrated circuit structures that include a semiconductor layer having at least one fin. At least three gate stacks contact, and are spaced along, the top of the fin. An insulator in trenches in the fin contacts the first and third of the gate stacks, and extends into the fin from the first and third gate stacks. Source and drain regions in the fin are adjacent a second of the gate stacks. The second gate stack is between the first and third gate stacks along the top of the fin. Additionally, a protective liner is in the trench between a top portion of the insulator a bottom portion of the insulator.

Abstract: A method of forming a vertical fin field effect transistor with a self-aligned gate structure, comprising forming a plurality of vertical fins on a substrate, forming gate dielectric layers on opposite sidewalls of each vertical fin, forming a gate fill layer between the vertical fins, forming a fin-cut mask layer on the gate fill layer, forming one or more fin-cut mask trench(es) in the fin-cut mask layer, and removing portions of the gate fill layer and vertical fins not covered by the fin-cut mask layer to form one or more fin trench(es), and two or more vertical fin segments from each of the plurality of vertical fins, having a separation distance, D1, between two vertical fin segments.

Abstract: A semiconductor device includes a FinFET component, a plurality of patterned dummy semiconductor fins arranged aside a plurality of fins of the FinFET component, an isolation structure formed on the patterned dummy semiconductor fins, and a tuning component formed on the patterned dummy semiconductor fins and electrically connected to the FinFET component. A height of the patterned dummy semiconductor fins is shorter than that of the fins of the FinFET component.

Abstract: A replacement gate structure (i.e., functional gate structure) is formed and recessed to provide a capacitor cavity located above the recessed functional gate structure. A ferroelectric capacitor is formed in the capacitor cavity and includes a bottom electrode structure, a U-shaped ferroelectric material liner and a top electrode structure. The bottom electrode structure has a topmost surface that does not extend above the U-shaped ferroelectric material liner. A contact structure is formed above and in contact with the U-shaped ferroelectric material liner and the top electrode structure of the ferroelectric capacitor.

Abstract: A semiconductor structure includes a substrate, at least two gate spacers, a gate stack, an insulating structure, and at least one sacrificial layer. The substrate has at least one semiconductor fin. The gate spacers are disposed on the substrate. The gate stack is disposed between the gate spacers and covers the semiconductor fin. The insulating structure is disposed between the gate spacers and adjacent to the gate stack. The sacrificial layer is disposed between at least one of the gate spacers and the insulating structure.

Abstract: The present invention provides a manufacture method of a TFT substrate and a manufactured TFT substrate. By locating the first channel region and the first lightly doped offset region between the first source and the drain, and locating the second channel region and the second lightly doped offset region between the second source and the drain, and forming the first overlapping region and the second overlapping region respectively between the drain and the gate and between the second source and the gate, thus, the paths of the current flowing from the first, the second sources to the drain and the current flowing from the drain to the first, the second sources are the same. Namely, the current path from source to the drain and the current path from the drain to the source are the same. According, the symmetry of the TFT structure is realized.

Abstract: A device includes a plurality of STI regions, a plurality of semiconductor strips between the STI regions and parallel to each other, and a plurality of semiconductor fins over the semiconductor strips. A gate stack is disposed over and crossing the plurality of semiconductor fins. A drain epitaxy semiconductor region is disposed on a side of the gate stack and connected to the plurality of semiconductor fins. The drain epitaxy semiconductor region includes a first portion adjoining the semiconductor fins, wherein the first portion forms a continuous region over and aligned to the plurality of semiconductor strips. The drain epitaxy semiconductor region further includes second portions farther away from the gate stack than the first portion. Each of the second portions is over and aligned to one of the semiconductor strips. The second portions are parallel to each other, and are separated from each other by a dielectric material.

Abstract: A semiconductor device includes a fin protruding from a substrate and extending in a first direction, first and second gate structures intersecting the fin, a recess formed in the fin between the first and second gate structures, a device isolation layer which fills the recess, and which has an upper surface protruded outwardly from the fin and disposed to be coplanar with upper surfaces of the first and second gate structures, a liner formed along a side walls of the device isolation layer protruded outwardly from the fin and a source/drain region disposed at both sides of the recess and spaced apart from the device isolation layer.

Abstract: The present invention provides a non-overlapped-extension-implantation (NOI) nonvolatile memory device capable of being treated with anti-fuse operation. Differing from conventional anti-fuse memory devices, the structure and fabrication of this NOI nonvolatile memory device are complied with currently-used standard COMS processes; that is, the NOI nonvolatile memory device provided by the present invention can be manufactured through the standard COMS processes, without using any additional masks for defining specific oxide layer. The most important is that, after the NOI nonvolatile memory device is treated with the anti-fuse operation, the Gate and Drain of the NOI nonvolatile memory device still propose the switching characteristic the same to the traditional MOSFET, resulting from the oxide breakdown caused by a high electric filed merely occur in an overlapped oxide segment of the gate oxide layer.

Abstract: A metal oxide semiconductor carbon nanotube thin film transistor circuit includes a p-type carbon nanotube thin film transistor and a n-type carbon nanotube thin film transistor stacked with each other. The p-type carbon nanotube thin film transistor includes a first semiconductor carbon nanotube layer, a first drain electrode, a first source electrode, a functional dielectric layer, and a first gate electrode. The n-type carbon nanotube thin film transistor includes a second semiconductor carbon nanotube layer, a second drain electrode, a second source electrode, a first insulating layer, and a second gate electrode. The first drain electrode and the second drain electrode are electrically connected with each other. The first gate electrode and the second gate electrode are electrically connected with each other.

Abstract: To provide a highly reliable semiconductor device manufactured by giving stable electric characteristics to a semiconductor device including an oxide semiconductor. In a manufacturing process of a transistor, an oxide semiconductor layer, a source electrode layer, a drain electrode layer, a gate insulating film, a gate electrode layer, and an aluminum oxide film are formed in this order, and then heat treatment is performed on the oxide semiconductor layer and the aluminum oxide film, whereby an oxide semiconductor layer from which an impurity containing a hydrogen atom is removed and which includes a region containing oxygen more than the stoichiometric proportion is formed. In addition, when the aluminum oxide film is formed, entry and diffusion of water or hydrogen into the oxide semiconductor layer from the air due to heat treatment in a manufacturing process of a semiconductor device or an electronic appliance including the transistor can be prevented.

Abstract: A method for fabricating semiconductor device includes the steps of: forming a fin-shaped structure on a substrate; forming a shallow trench isolation (STI) around the fin-shaped structure; forming a gate layer on the fin-shaped structure and the STI; removing part of the gate layer, part of the fin-shaped structure, and part of the STI to form a trench; and forming a dielectric layer into the trench to form a single diffusion break (SDB) structure.

Abstract: Disclosed is a semiconductor structure, including at least one fin-type field effect transistor and at least one single-diffusion break (SDB) type isolation region, and a method of forming the semiconductor structure. In the method, an isolation bump is formed above an isolation region within a semiconductor fin and sidewall spacers are formed on the bump. During an etch process to reduce the height of the bump and to remove isolation material from the sidewalls of the fin, the sidewall spacers prevent lateral etching of the bump. During an etch process to form source/drain recesses in the fin, the sidewalls spacers protect the semiconductor material adjacent to the isolation region. Consequently, the sides and bottom of each recess include semiconductor surfaces and the angle of the top surfaces of the epitaxial source/drain regions formed therein is minimized, thereby minimizing the risk of unlanded source/drain contacts.

Abstract: Methods of forming a diffusion break are disclosed. The method includes forming a diffusion break after source/drain formation, by removing a gate stack of the dummy gate to a buried insulator of an SOI substrate, creating a first opening; and filling the first opening with a dielectric to form the diffusion break. An IC structure includes the diffusion break in contact with an upper surface of the buried insulator. In an optional embodiment, the method may also include simultaneously forming an isolation in an active gate to an STI in the SOI substrate.

Abstract: A method for forming a semiconductor device. In this method, a semiconductor fin is formed on a semiconductor substrate. Two cells adjacent to each other are formed on the semiconductor fin. A gate conductor is formed on a top of the semiconductor fin at a common boundary that is shared by the two cells. A gate spacer is formed to peripherally enclose the gate conductor. The gate conductor and the semiconductor fin are etched to form an air gap, thereby dividing the semiconductor fin into two portions of the semiconductor fin. A dielectric cap layer is deposited into the air gap to cap a top of the air gap.

Abstract: An integrated circuit device includes a double-humped protrusion protruding from a surface of an inter-device isolation region. To manufacture the integrated circuit device, a plurality of grooves are formed in the inter-device isolation region of a substrate, a recess is formed by partially removing a surface of the substrate between the plurality of grooves, at least one fin-type active area is formed in a device region by etching the substrate in the device region and the inter-device isolation region, and the double-humped protrusion is formed from the surface of the substrate in the inter-device isolation region.

Abstract: Structures and fabrication methods for vertical-transport field-effect transistors. The structure includes a vertical-transport field-effect transistor having a source/drain region located in a semiconductor layer, a fin projecting from the source/drain region in the semiconductor layer, and a gate electrode on the semiconductor layer and coupled with the fin. The structure further includes an interconnect located in a trench defined in the semiconductor layer. The interconnect is coupled with the source/drain region or the gate electrode of the vertical-transport field-effect transistor, and may be used to couple the source/drain region or the gate electrode of the vertical-transport field-effect transistor with a source/drain region or a gate electrode of another vertical-transport field-effect transistor.

Abstract: A semiconductor device includes a semiconductor device and a semiconductor fin on the semiconductor substrate, in which the semiconductor fin has a fin isolation structure at a common boundary that is shared by the two cells. The fin isolation structure has a dielectric portion extending from a top of the semiconductor fin to a stop layer on the semiconductor substrate. The dielectric portion divides the semiconductor fin into two portions of the semiconductor fin.

Abstract: A method of depositing silicon nitride films on semiconductor substrates processed in a micro-volume of a plasma enhanced atomic layer deposition (PEALD) reaction chamber wherein a single semiconductor substrate is supported on a ceramic surface of a pedestal and process gas is introduced through gas outlets in a ceramic surface of a showerhead into a reaction zone above the semiconductor substrate, includes (a) cleaning the ceramic surfaces of the pedestal and showerhead with a fluorine plasma, (b) depositing a halide-free atomic layer deposition (ALD) oxide undercoating on the ceramic surfaces, (c) depositing a precoating of ALD silicon nitride on the halide-free ALD oxide undercoating, and (d) processing a batch of semiconductor substrates by transferring each semiconductor substrate into the reaction chamber and depositing a film of ALD silicon nitride on the semiconductor substrate supported on the ceramic surface of the pedestal.

Abstract: The present disclosure provides a semiconductor structure comprising one or more fins formed on a substrate and extending along a first direction; one or more gates formed on the one or more fins and extending along a second direction substantially perpendicular to the first direction, the one or more gates including an first isolation gate and at least one functional gate; source/drain features formed on two sides of each of the one or more gates; an interlayer dielectric (ILD) layer formed on the source/drain features and forming a coplanar top surface with the first isolation gate. A first height of the first isolation gate is greater than a second height of each of the at least one functional gate.

Abstract: A method of forming a transistor can include forming a gate mask on a substrate having a vertical location aligned with that of a transistor control gate; implanting first conductivity type dopants with the gate mask as an implant mask to form a first shallow halo region; implanting first conductivity type dopants with at least the gate mask as an implant mask to form a first deep halo region having a peak dopant concentration profile at a greater substrate depth than the first shallow halo region; forming an epitaxial layer on top of the substrate; forming a first control gate structure on the epitaxial layer; and forming a first source or drain region, of a second conductivity type, in at least the epitaxial layer to a side of the first control gate, and over the first shallow halo region and the first deep halo region.

Abstract: In one illustrative embodiment, the present disclosure is directed to a method involving fabricating an NMOS transistor device having a substrate and a gate structure disposed over the substrate, the substrate including a channel region underlying, at least partially, the gate structure, the fabricating including: forming a source and drain cavity in the substrate; with an in situ doped semiconductor material, epitaxially growing a source and drain region within the source and drain cavity; performing an amorphization ion implantation process by implanting an amorphization ion material into the source and drain region; forming a capping material layer above the NMOS transistor device; with the capping material layer in position, performing a stress forming anneal process to thereby form stacking faults in the source and drain region; and removing the capping material layer.

Abstract: A method of forming high germanium content silicon germanium alloy fins with controlled insulator layer recessing is provided. A silicon germanium alloy (SiGe) layer having a first germanium content is provided on a surface of an insulator layer using a first condensation process. Following the formation of a hard mask layer portion on the SiGe layer, a second condensation process is performed to convert a portion of the SiGe layer into a SiGe fin of a second germanium content that is greater than the first germanium content and other portions of the SiGe layer into a shell oxide structure located on sidewalls of the SiGe fin. After forming a fin placeholder material, a portion of each shell oxide structure is removed, while maintaining a lower portion of each shell oxide structure at the footprint of the SiGe fin.