Abstract: A stacked leadframe assembly is disclosed. The stacked leadframe assembly includes a first die having a surface that defines a mounting plane, a first leadframe stacked over and attached to the first die, a second die stacked over and attached to the first leadframe; and a second leadframe stacked over and attached to the second die. The leadframes have die paddles with extended side panels that have attachment surfaces in the mounting plane.

Abstract: A method of manufacturing a semiconductor package structure is provided. A supporting plate and multiple padding patterns on an upper surface of the supporting plate define a containing cavity. Multiple leads electrically insulated from one another are formed on the padding patterns, extend from top surfaces of the padding patterns along side surfaces to the upper surface and are located inside the containing cavity. A chip is mounted inside the containing cavity, electrically connected to the leads. A molding compound is formed to encapsulate at least the chip, a portion of the leads and a portion of the supporting plate, fill the containing cavity and gaps among the padding patterns, and exposes a portion of the leads on the top surface. The supporting plate is removed to expose a back surface of each padding pattern, a bottom surface of the molding compound and a lower surface of each lead.

Abstract: A package for a semiconductor die includes a die attach pad that provides an attachment surface area for the semiconductor die, and tie bars connected to the die attach pad. The die attach pad is disposed in a first general plane and the tie bars are disposed in a second general plane offset with respect to the first general plane. A molding compound encapsulates the semiconductor die in a form having first, second, third and fourth lateral sides, a top and a bottom. The tie bars are exposed substantially coincident with at least one of the lateral sides. The form includes a discontinuity that extends along the at least one of the lateral sides, the discontinuity increasing a creepage distance measured from the tie bars to the bottom of the package.

Abstract: A luminous body comprises a transparent plastic moulding with indentations, and LED DIEs disposed within the indentations. One side of each LED DIE lies approximately flush with an upper side of the moulding, and each LED DIE is connected to an electricity supply via electrical conductors disposed on the moulding. A method for producing such a luminous body is also disclosed.

Abstract: A semiconductor device has a base substrate with recesses formed in a first surface of the base substrate. A first conductive layer is formed over the first surface and into the recesses. A second conductive layer is formed over a second surface of the base substrate. A first semiconductor die is mounted to the base substrate with bumps partially disposed within the recesses over the first conductive layer. A second semiconductor die is mounted to the first semiconductor die. Bond wires are formed between the second semiconductor die and the first conductive layer over the first surface of the base substrate. An encapsulant is deposited over the first and second semiconductor die and base substrate. A portion of the base substrate is removed from the second surface between the second conductive layer down to the recesses to form electrically isolated base leads for the bumps and bond wires.

Abstract: A leadframe for a leadframe type package includes a chip base, and leads constituting lead lanes. One lead lane includes a pair of first differential signal leads, a pair of second differential signal leads, a pair of third differential signal leads between which and the pair of first differential signal leads is arranged the pair of second differential signal leads and a first power lead arranged between the pair of first and second differential signal leads. One of the pairs of differential signal leads has half-duplex transmission mode and two of the other pairs of differential signal leads have full-duplex transmission mode.

Abstract: Provided, in one embodiment, is an integrated circuit (IC) leadframe. In one example, the leadframe includes a paddle, wherein the paddle has a surface configured to accept an IC chip and has at least one edge, the at least one edge having one or more slots located therein. In this example, the leadframe may further include a plurality of lead fingers having ends extending toward the at least one edge, wherein the ends of ones of pairs of adjacent lead fingers extend into corresponding slots in the paddle.

Abstract: Provided is a light emitting diode package and a method of manufacturing the same. The light emitting diode package includes a package main body with a cavity, a plurality of light emitting diode chips, a wire, and a plurality of lead frames. The plurality of light emitting diode chips are mounted in the cavity. The wire is connected to an electrode of at least one light emitting diode chip. The plurality of lead frames are formed in the cavity, and at least one lead frame is electrically connected to the light emitting diode chip or a plurality of wires.

Abstract: A semiconductor composite wiring assembly includes a wiring assembly and a lead frame. A copper wiring layer of the wiring assembly includes first terminals, second terminals, and wiring sections connecting the terminals. The second terminals and the lead frame are electrically connected by connecting members. The lead frame includes a die pad for mounting the wiring assembly, and lead sections located at outer positions. The die pad includes a central area in which a semiconductor chip is mounted via the wiring assembly, and a peripheral area connected to the central area with spaces formed therebetween that serve as resin-seal inflow spaces. The wiring assembly is positioned over the central area and the peripheral area so as to cover the central area completely and the peripheral area partially, and at least the central area and the peripheral area of the die pad are glued to the wiring assembly by resin paste.

Abstract: A resin-sealed semiconductor device includes a power element (1), a control element (4), a first lead frame (3) having a first die pad (3A) which holds the power element (1), a second lead frame (5) having a second die pad (5A) which holds the control element (4), and a housing (6) made of a resin material and sealing the power element, the first die pad, the control element, and the second die pad. A lower surface of the second die pad is higher than an upper surface of the first element, and at least part of the first die pad and at least part of the second die pad overlap each other when viewed from the top. One of the first leads and one of the second leads are directly joined together by a joint portion (23) and electrically coupled together in the housing.

Abstract: A complete power management system implemented in a single surface mount package. The system may be drawn to a DC to DC converter system and includes, in a leadless surface mount package, a driver/controller, a MOSFET transistor, passive components (e.g., inductor, capacitor, resistor), and optionally a diode. The MOSFET transistor may be replaced with an insulated gate bipolar transistor, IGBT in various embodiments. The system may also be a power management system, a smart power module or a motion control system. The passive components may be connected between the leadframe connections. The active components may be coupled to the leadframe using metal clip bonding techniques. In one embodiment, an exposed metal bottom may act as an effective heat sink.

Abstract: A method of forming an electronic assembly includes attaching a backside metal layer the bottomside of a semiconductor die. An area of the backside metal layer matches an area of the bottomside of the die. A die pad and leads are encapsulated within the molding material. The leads include an exposed portion that includes a bonding portion. A gap exposes the backside metal layer along a bottom surface of the package. Bond wires couple the pads on the topside of the die to the leads and the bonding portions. Packaged semiconductor device is soldered to a printed circuit board (PCB). The backside metal layer and the bonding portions of the leads are soldered substrate pads on said PCB.

Abstract: Semiconductor chip stacks are provided. The semiconductor chip stack includes a semiconductor chip stack including a plurality of first semiconductor chips vertically stacked on a top surface of the interposer, a second semiconductor chip stacked on a bottom surface of the interposer opposite to the semiconductor chip stack, and an external electrode attached to a top surface of the second semiconductor chip opposite to the interposer. Electronic systems including the semiconductor chip stack and related methods are also provided.

Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a peripheral lead having a peripheral lead bottom side, a peripheral lead top side, a peripheral lead non-horizontal side, and a peripheral lead horizontal ridge protruding from the peripheral lead non-horizontal side; forming a first top distribution layer on the peripheral lead top side; connecting an integrated circuit to the first top distribution layer; and applying an insulation layer directly on a distribution layer bottom extent of the first top distribution layer and a peripheral lead ridge lower side of the peripheral lead horizontal ridge with a cavity in the portion of the insulation layer directly below the integrated circuit.

Abstract: In one embodiment, a leadframe for a semiconductor package includes a source connection area for one transistor and a drain connection point for a second transistor, and a common connection for using a connection clip to couple a drain of the first transistor to a source of the second transistor and to the common connection.

Abstract: The reliability of a semiconductor device is prevented from being reduced. A planar shape of a sealing body is comprised of a quadrangle having a pair of first sides, and a pair of second sides crossing with the first sides. Further, it has a die pad, a controller chip (first semiconductor chip) and a sensor chip (second semiconductor chip) mounted over the die pad, and a plurality of leads arranged along the first sides of the sealing body. The controller chip and the leads are electrically coupled to each other via wires (first wires), and the sensor chip and the controller chip are electrically coupled to each other via wires (second wires). Herein, the die pad is supported by a plurality of suspending leads formed integrally with the die pad and extending from the die pad toward the first sides of the sealing body. Each of the suspending leads has an offset part.

Abstract: An integrated circuit package structure includes a bottom portion having a cavity, an integrated circuit attached to a top surface of the stepped cavity, a leadframe attached to the bottom portion, wire bonding for electrically coupling the integrated circuit to the leadframe, and a top portion conformally covering the integrated circuit and the bottom portion.

Abstract: Multiple surface finishes are applied to a substrate for a microelectronics package by applying a first surface finish to connection pads of a first area of the substrate, masking the first area of the substrate without masking a second area of the substrate, applying a second different surface finish to connection pads of the second area of the substrate, and removing the mask.

Abstract: A packaging structure having an embedded semiconductor element includes: a substrate having opposite first and second surfaces and at least an opening penetrating the first and second surfaces; a first metallic frame disposed around the periphery of the opening on the first surface; a semiconductor chip received in the opening and having an active surface formed with a plurality of electrode pads and an opposite inactive surface; two first dielectric layers formed on the active surface and the inactive surface of the chip, respectively; a first wiring layer formed on the first dielectric layer of the first surface; and a first built-up structure disposed on the first dielectric layer and the first wiring layer. A shape of the opening is precisely controlled through the first metallic frame around the periphery of the predefined opening region, thereby allowing the chip to be precisely embedded in the substrate.

Abstract: A method of manufacturing a semiconductor package structure is provided. A heat-conductive block is adhered to a portion of a second surface of a conductive substrate via a first adhesive layer. An opening is formed by performing a half-etching process on a first surface of the conductive substrate. The remaining conductive substrate is patterned to form leads and expose a portion of the heat-conductive block. Each lead has a first portion and a second portion. A thickness of the first portion is greater than a thickness of the second portion. A first lower surface of the first portion and a second lower surface of the second portion are coplanar. A chip is disposed on the exposed portion of the heat-conductive block and electrically connected to the second portions of the leads. A first bottom surface of the heat-conductive block and a second bottom surface of a molding compound are coplanar.

Abstract: The electronic device includes a carrier, a semiconductor substrate attached to the carrier, and a layer system disposed between the semiconductor substrate and the carrier. The layer system includes an electrical contact layer disposed on the semiconductor substrate. A functional layer is disposed on the electrical contact layer. An adhesion layer is disposed on the functional layer. A solder layer is disposed between the adhesion layer and the carrier.

Abstract: A semiconductor device featuring a semiconductor chip having a first main surface and a second, opposing main surface and including a MOSFET having source and gate electrodes formed on the first main surface and a drain electrode thereof formed on the second main surface, first and second conductive members acting as lead terminals for the source and gate electrodes, respectively, are disposed over the first main surface, each of the first and second conductive members has a part overlapped with the chip in a plan view, a sealing body sealing the chip and parts of the first and second conductive members such that a part of the first conductive member is projected outwardly from a first side surface of the sealing body and parts of the first and second conductive members are projected outwardly from the opposing second side surface of the sealing body in a plan view.

Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a first lead adjacent and staggered to a second lead, the first lead having a first external connection portion with a first external conductive layer and a first internal connection portion, the first external connection portion oriented laterally outwards from the first internal connection portion, and the second lead having a second external connection portion with a second external conductive layer and a second internal connection portion; connecting an integrated circuit device with the first internal connection portion and with the second internal connection portion; forming an encapsulation over the integrated circuit device with the first lead and the second lead exposed; and forming a solder mask on the encapsulation, on the first lead, and on the second lead with the first external conductive layer and the second external conductive layer exposed from the solder mask.

Abstract: Disclosed herein is a semiconductor package. The semiconductor package includes: a substrate having a semiconductor device mounted on a top portion thereof; a housing surrounding the semiconductor device and the substrate so as to isolate them from the outside; at least one lead frame disposed on the top portion of the substrate while being spaced apart from one another; and a clip electrically connecting the substrate with at least one lead frame.

Abstract: The present invention relates to the field of semiconductor chip packages, and more specifically to a lead frame and flip chip package device thereof. In one embodiment, a lead frame for electrically connecting a chip to outside leads, can include a plurality of lead fingers, where each of the plurality of lead fingers comprises a plurality of outburst regions extending from an edge thereof. In one embodiment, a flip chip package device can include: a chip and a plurality of solder bumps, where one surface of the chip is connected to a first surface of each of the plurality of solder bumps; and the lead frame, where second surfaces of each of the plurality solder bumps are connected with corresponding outburst regions of the lead frame to connect the chip to the lead frame through the solder bumps.

Abstract: A method for manufacturing a package comprises a first step of forming a metal pattern including a frame and a plurality of leads extending inward from the frame, a second step of molding a resin pattern including a first resin portion which holds the plurality of leads from an inner side thereof, and second resin portions which cover bottom surfaces of peripheral portions, adjacent to portions to be removed, in the plurality of leads while exposing bottom surfaces of the portions to be removed in the plurality of leads, so as to hold the plurality of leads from a lower side thereof, and a third step of cutting the plurality of leads into a plurality of first leads and a plurality of second leads by removing the portions to be removed in the plurality of leads while the resin pattern keeps holding the peripheral portions in the plurality of leads.

Abstract: A semiconductor package which includes a generally planar die paddle defining multiple peripheral edge segments and a plurality of leads which are segregated into at least two concentric rows. Connected to the top surface of the die paddle is at least one semiconductor die which is electrically connected to at least some of the leads of each row. At least portions of the die paddle, the leads, and the semiconductor die are encapsulated by a package body, the bottom surfaces of the die paddle and the leads of at least one row thereof being exposed in a common exterior surface of the package body.

Abstract: A leadframe and semiconductor device package with multiple semiconductor device die paddles for accepting multiple semiconductor devices is disclosed, wherein the leadframe increases semiconductor device density and reduces cost by integrating the multiple dies into a semiconductor device package with a relatively small footprint. The leadframe may include at least one full-metal die paddle and at least one reduced-metal die paddle, which may form a unified or hybrid die paddle. The leadframe may enable electrical coupling of multiple semiconductor devices to a common leadfinger and/or die paddle, where internal leadfingers coupled to the common leadfingers and/or die paddles may receive the electrical coupling means from the semiconductor device. Surfaces of one or more die paddles of the leadframe may be exposed to the outside of the semiconductor device package to enable electrical testing of and/or provide heat dissipation from one or more of the semiconductor devices attached to the leadframe.

Abstract: A light emitting device package is provided. The light emitting device package comprises a package body comprising a first cavity, and a second cavity connected to the first cavity; a first lead electrode, at least a portion of which is disposed within the second cavity; a second lead electrode, at least a portion of which is disposed within the first cavity; a light emitting device disposed within the second cavity; a first wire disposed within the second cavity, the first wire electrically connecting the light emitting device to the first lead electrode; and a second wire electrically connecting the light emitting device to the second lead electrode.

Abstract: Disclosed herein is a power module package including: a substrate having a ceramic layer formed in one surface thereof; a circuit pattern formed on the ceramic layer; a first lead frame having one side contacting the circuit pattern and the other side protruding toward the outside; and a first semiconductor chip mounted on one side of the first lead frame.

Abstract: Some exemplary embodiments of a multi-chip module (MCM) power quad flat no-lead (PQFN) semiconductor package utilizing a leadframe for electrical interconnections have been disclosed. One exemplary embodiment comprises a PQFN semiconductor package comprising a leadframe, a driver integrated circuit (IC) coupled to the leadframe, a plurality of vertical conduction power devices coupled to the leadframe, and a plurality of wirebonds providing electrical interconnects, including at least one wirebond from a top surface electrode of one of the plurality of vertical conduction power devices to a portion of the leadframe, wherein the portion of the leadframe is electrically connected to a bottom surface electrode of another of the plurality of vertical conduction power devices. In this manner, efficient multi-chip circuit interconnections can be provided in a PQFN package using low cost leadframes.

Abstract: Disclosed herein is a semiconductor chip, including: a first substrate having a concave formed on one surface thereof and an opening formed on a bottom surface of the concave; a second substrate contacting the other surface of the first substrate; and a semiconductor chip mounted in the concave.

Abstract: Systems and methods for lead frame locking design features are provided. In one embodiment, a method comprises: fabricating a lead frame for a chip package, the lead frame having a paddle comprising a step-out bottom locking feature profile across at least a first segment of an edge of the paddle that provides an interface with a mold compound; etching the paddle to have at least a second segment of the edge having either an extended-step-out bottom locking feature profile or an overhanging top locking feature profile; and alternating first and second segments along the edge of the paddle.

Abstract: An apparatus for manufacturing a semiconductor package includes an index rail transferring a lead frame in forward and backward directions, the lead frame having a first surface and a second surface that is opposite to the first surface, a loader portion connected to an end portion of the index rail and supplying the lead frame to the index rail, a frame driving portion connected to the opposite end portion of the end portion of the index rail and rotating the lead frame around a normal to the first surface, and a die attach portion attaching a semiconductor chip on the lead frame supplied to the index rail.

Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a first terminal; connecting an integrated circuit to the first terminal; forming a second terminal connected over the first terminal and the integrated circuit by a vertical conductive post integral with the first terminal or the second terminal; and encapsulating the integrated circuit and the vertical conductive post leaving portions of the first terminal and the second terminal exposed.

Abstract: An integrated circuit package system includes: connecting an integrated circuit die and external interconnects; forming an encapsulation over the integrated circuit die and a portion of the external interconnects; and forming an isolation hole between the external interconnects and into a side of the encapsulation exposing the external interconnects.

Abstract: In one aspect of the present invention, an integrated circuit package with an exposed die and a protective housing will be described. The housing extends beyond the exposed back surface of the die to help protect it from damage. The integrated circuit package includes a lead frame and an integrated circuit die. The integrated circuit die is electrically and physically attached to the lead frame. The housing encapsulates the lead frame and the die. The housing also includes a recessed region at the bottom of the package where the back surface of the die is exposed. There is a protruding protective structure at the bottom of the package that helps to protect the die and prevent its exposed back surface from coming in contact with an external object.

Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a lead having an upper portion and a bottom portion with a first overhang portion from a top surface of the upper portion and the lead also having serrations along upper vertical sides intersecting the top surface; forming an upper contact plate on the top surface; forming a bottom contact plate on a bottom surface of the bottom portion; attaching an integrated circuit die over the upper portion; and encapsulating the upper portion and the integrated circuit die with an encapsulation leaving the bottom portion exposed.

Abstract: A non-leaded integrated circuit package system includes: a die paddle of a lead frame; a dual row of terminals including an outer terminal and an inner terminal; and an inner terminal and an adjacent inner terminal to form a fused lead.

Abstract: A semiconductor package includes a die pad, at least one semiconductor die mounted on the die pad, a plurality of leads disposed along peripheral edges of the die pad, at least one connecting bar for supporting the die pad, a first power bar disposed on one side of the connecting bar, a second power bar disposed on the other side of the connecting bar, and a connection member traversing the connecting bar and electrically connecting the first power bar with the second power bar.

Abstract: A semiconductor package includes a semiconductor component including a circuit carrier with a plurality of inner contact pads, a semiconductor chip, and a plurality of electrical connections. An adhesion promotion layer is disposed on at least areas of the semiconductor component and a plastic encapsulation material encapsulates at least the semiconductor chip, the plurality of electrical connections and the plurality of the inner contact pads. Surface regions of the semiconductor component are selectively activated.

Abstract: An integrated circuit package system includes a leadframe with leads configured to provide electrical contact between an integrated circuit chip and an external electrical source. Configuring the leads to include outer leads, down set transitional leads, and down set inner leads. Connecting the integrated circuit chip electrically to the down set inner leads. Depositing an encapsulating material to prevent exposure of the down set inner leads.

Abstract: A device including a power semiconductor chip. One embodiment provides a power semiconductor chip having a first electrode on a first surface and a second and a third electrode on a second surface opposite to the first surface. A leadframe includes a carrier and a first lead, the power semiconductor chip placed over the carrier with the first surface of the power semiconductor chip facing the carrier. A metallic layer includes a first surface and a second surface opposite to the first surface. The metallic layer is placed over the second surface of the power semiconductor chip with the first surface of the metallic layer facing the power semiconductor chip. The second surface of the metallic layer and a surface of the first lead lie within a common mounting plane.

Abstract: A packaging structure comprises a first leadframe, a second leadframe, two grounding pins, two first pins, a plurality of first wires, a plurality of second wires, and a package body. The second leadframe is coupled to the drains of a first power transistor and a second power transistor. The two grounding pins are adjacent together and coupled to the first leadframe. The two first pins are coupled to the source of the second power transistor. The two first pins are connected together through a conductive region for increasing capability of loading current. The plurality of first wires is coupled between the source of the second power transistor and the first pin to decrease the internal resistance of the second power transistor. The plurality of second wires is coupled between the first leadframe and the source of the first power transistor to decrease the internal resistance of the first power transistor.

Abstract: Disclosed is a memory card package with a small substrate by using a metal die pad having an opening to substitute the chip-carrying function of a conventional substrate so that substrate dimension can be reduced. A substrate is attached under the metal die pad. A first chip is disposed on the substrate located inside the opening. A second chip is disposed on the metal die pad without covering the opening. A card-like encapsulant encapsulates the metal die pad, the top surface of the substrate, the first chip, and the second chip. The dimension of the substrate is smaller than the dimension of the encapsulant. The substrate has a lumpy sidewall encapsulated by the encapsulant so that the bottom surface of the substrate is coplanar with a bottom side of the encapsulant to increase the adhesion between the substrate and the encapsulant.

Abstract: A semiconductor package method for co-packaging high-side (HS) and low-side (LS) semiconductor chips is disclosed. The HS and LS semiconductor chips are attached to two opposite sides of a lead frame, with a bottom drain electrode of the LS chip connected to a top side of the lead frame and a top source electrode of the HS chip connected to a bottom side of the lead frame through a solder ball. The stacking configuration of HS chip, lead frame and LS chip reduces the package size. A bottom metal layer covering the bottom of HS chip exposed outside of the package body provides both electrical connection and thermal conduction.

Abstract: A flip chip lead frame package includes a die and a lead frame having a die paddle and leads, and has a spacer to maintain a separation between the die and the die paddle. Also, methods for making the package are disclosed.

Abstract: A device including a semiconductor chip and metal foils. One embodiment provides a device including a semiconductor chip having a first electrode on a first face and a second electrode on a second face opposite to the first face. A first metal foil is attached to the first electrode of the semiconductor chip in an electrically conductive manner. A second metal foil is attached to the second electrode of the semiconductor chip in an electrically conductive manner.

Abstract: When a metal ribbon is ultrasonic-bonded, a peripheral area of an island and hanging pins provided in the periphery of the island need to be clamped by use of clampers of a bonder to prevent the island from being lifted up. However, if no sufficiently-wide peripheral area of the island can be secured or no hinging pins can be provided due to the miniaturization of the device, there arises a problem that the island cannot be clamped. A protrusion, which protrudes toward a lead and has the same height as an end portion of the lead, is provided to an edge of the island opposed to the lead. Accordingly, when the protrusion and the end portion of the lead are simultaneously pressed by the damper, it is possible to prevent the island from being lifted up even when no hanging pin or no clamp area around the island is provided.

Abstract: Disclosed herein is a power module package, including: a first substrate having one surface and the other surface; first vias formed to penetrate from one surface of the first substrate to the other surface thereof; a metal layer formed on one surface of the first substrate; semiconductor devices formed on the metal layer; and a metal plate formed on the other surface of the first substrate.