Abstract: In various embodiments, a chip module may include a first chip; and a leadframe with a first leadframe area and a second leadframe area, wherein the first leadframe area is electrically insulated from the second leadframe area; wherein the first chip is arranged at least partially on the first leadframe area and at least partially on the second leadframe area.

Abstract: A semiconductor device includes a lead frame 1 having a first lead 6, a second lead 7 and a third lead 8. A power transistor 2 is placed on the first lead 6, and the power transistor 2 is connected to the first lead 6. The power transistor 2 has a drain electrode on one side opposite to a first lead 6 side, and this drain electrode is connected to a Cu chip 3 on the power transistor 2. The Cu chip 3 is connected to the second lead 7 via Al wires 4. As a result, during wire bonding of the Al wires 4, it becomes possible to absorb shocks due to wire bonding by the Cu chip 3, or disperse pressure due to wire bonding by the Cu chip 3, or diffuse heat due to wire bonding by the Cu chip 3.

Abstract: A method of fabricating a leadframe-based semiconductor package, and a semiconductor package formed thereby, are disclosed. In embodiments, a semiconductor die having die bond pads along two adjacent edges may be electrically coupled to four sides of a four-sided leadframe. Embodiments relate to lead and no-lead type leadframe.

Abstract: An integrated circuit package to package stacking system is provided including providing a first integrated circuit package, having a configured leadframe, providing a second integrated circuit package, having the configured leadframe, and forming an integrated circuit package pair by electrically connecting the configured leadframe of the first integrated circuit package to the configured leadframe of the second integrated circuit package.

Abstract: A method of manufacturing an LED package includes mounting a large panel frame/substrate (LPF/S) having a substantially square shape to a ring. The LPF/S includes a plurality of die pads and a corresponding plurality of leads arranged in a matrix pattern. Each of the die pads includes a planar chip attach surface. An LED chip is attached to the planar chip attach surface of each of the die pads. An encapsulant material is applied overlaying the LED chips and at least a part of the LPF/S. Each die pad and corresponding leads are separated from the LPF/S to form individual LED packages. The steps of attaching the LED chips and applying the encapsulant material are performed while the LPF/S is mounted to the ring.

Abstract: A semiconductor memory device includes: a wiring board including an element mounting portion and connection pads; a first element group including a plurality of semiconductor elements each having electrode pads arranged along one of outer sides of the semiconductor element, the plurality of semiconductor elements being layered stepwise on the element mounting portion of the wiring board in a way that pad arrangement sides of the semiconductor elements face in the same direction, and that the electrode pads are exposed; a second element group including a plurality of semiconductor elements each having electrode pads arranged along one of outer sides of the semiconductor element, the plurality of semiconductor elements being layered stepwise on the first element group in a way that pad arrangement sides of the semiconductor elements face in the same direction as that of the first element group, and that the electrode pads are exposed, the second element group being disposed to be offset from the first element g

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a lead frame having a die attach paddle, an isolated pad, and a connector; attaching an integrated circuit die to the die attach paddle and the connector; forming an encapsulation over the integrated circuit die, the connector, the die attach paddle, and the isolated pad; and singulating the connector and the die attach paddle whereby the isolated pads are electrically isolated.

Abstract: A method of manufacture of an integrated circuit package system includes: providing a penetrable layer; partially immersing leads in the penetrable layer; coupling an integrated circuit die to the leads; molding a package body on the integrated circuit die, the leads, and the penetrable layer; and exposing stand-off leads from the leads by removing the penetrable layer including establishing a stand-off height between a bottom of the package body and the bottom of the stand-off leads.

Abstract: A module (1) includes a first functional device (2) and a second functional device (3). The first functional device (2) includes a base electrode, an emitter electrode and a collector electrode. The second functional device (3) includes at least one electrode. The module (1) further includes a conductive frame (4). One of the base electrode, the emitter electrode, and the collector electrode of the first functional device (2) is directly connected to the frame (4). The electrode of the second functional device (3) is also directly connected to the frame (4). The frame (4) includes a portion serving as a terminal for external connection.

Abstract: A lead frame substrate, including: a metal plate having a first surface and a second surface; a semiconductor element mount portion and a semiconductor element electrode connection terminal that are formed on the first surface; an external connection terminal formed on the second surface and electrically connected to the semiconductor element electrode connection terminal; a conducting wire that connects the semiconductor element electrode connection terminal and the external connection terminal to each other; a resin layer formed on the metal plate; a hole portion that is partly formed in the second surface of the metal plate and does not penetrate the metal plate; and a plurality of protrusions that are formed on a bottom surface of the hole portion and protrude in a direction away from the metal plate, the protrusions having a height lower than a position of the second surface, not being in electrical conduction with the conducting wire, and being dispersed separately.

Abstract: A microelectronic assembly includes a substrate, a first and second microelectronic elements, a lead finger, electrical connections extending between contacts of the second microelectronic element and the lead fingers, and an encapsulant overlying at least portions of the first and second microelectronic elements, lead finger and electrical connections. The substrate has contacts at a first surface and terminals at an opposed second surface that are electrically connected with the substrate contacts. The first microelectronic element has contacts exposed at its front face. The front face of the first microelectronic element is joined to the substrate contacts. The second microelectronic element overlies the first microelectronic element and has contacts at a front face facing away from the substrate. The lead frame has lead fingers, wherein the second surface of the substrate and the lead fingers define a common interface for electrical interconnection to a component external to the microelectronic assembly.

Abstract: A semiconductor device package having pre-formed and placed through vias and a process for making such a package is provided. One or more signal conduits are coupled to a lead frame that is subsequently embedded in an encapsulated semiconductor device package. The free end of signal conduits is exposed while the other end remains coupled to a lead frame. The signal conduits are then used as through package vias, providing signal-bearing pathways between interconnects or contacts on the bottom and top of the package and the leads.

Abstract: A field-effect transistor package includes a leadframe with a first linear thickness (150a) and a leadframe pad (151) of a reduced thickness; a first terminal of a field-effect transistor chip (140) attached to the pad and a second and a third terminal remote from the pad; a metal sheet (110) of a second linear thickness (110a) connecting the second transistor terminal to a package terminal; a metal sheet (112) of a third linear thickness (112a) connecting the third transistor terminal to a package terminal; the sum of the first linear thickness (about 0.125 mm) and the second linear thickness (about 0.125 mm) plus attach material (about 0.05 mm) comprising the package thickness (about 0.3 mm).

Abstract: A light emitting device package is provided. The light emitting device package comprises a package body comprising a first cavity, and a second cavity connected to the first cavity; a first lead electrode, at least a portion of which is disposed within the second cavity; a second lead electrode, at least a portion of which is disposed within the first cavity; a light emitting device disposed within the second cavity; a first wire disposed within the second cavity, the first wire electrically connecting the light emitting device to the first lead electrode; and a second wire electrically connecting the light emitting device to the second lead electrode.

Abstract: A power overlay (POL) packaging structure that incorporates a leadframe connection is disclosed. The a POL structure includes a POL sub-module having a dielectric layer, at least one semiconductor device attached to the dielectric layer and that includes a substrate composed of a semiconductor material and a plurality of connection pads formed on the substrate, and a metal interconnect structure electrically coupled to the plurality of connection pads of the at least one semiconductor device, with the metal interconnect structure extending through vias formed through the dielectric layer so as to be connected to the plurality of connection pads. The POL structure also includes a leadframe electrically coupled to the POL sub-module, with the leadframe comprising leads configured to make an interconnection to an external circuit structure.

Abstract: A semiconductor die is solder bump-bonded to a leadframe or circuit board using solder balls having cores made of a material with a melting temperature higher than the melting temperature of the solder to ensure that in the finished structure the die is parallel to the leadframe or circuit board.

Abstract: Embodiments disclosed herein provide for a circuit including first die having an active side and a backside, wherein the first die is flip-chip mounted to a carrier. The circuit also includes a second die stacked on the backside of the first die, wherein the second die is stacked on the first die such that a backside of the second die is facing the backside of the first die and an active side of the second die faces away from the first die.

Abstract: By increasing the area of a source electrode 3a of a semiconductor element 3 and the area of a source terminal 2b of a lead frame 2, it is possible to extend a joint 8a of the source electrode 3a bonded to a conductive ribbon 6 and a joint 8b of the source terminal 2b. Thus it is possible to reduce an on resistance and easily reduce the number of times a bonding tool comes into contact with the joints to reduce a stress on the semiconductor element 3.

Abstract: A method of making an IC device includes providing a stack of leadframe sheets each including a plurality of leadframes and an interleaf member interposed between adjacent ones of the leadframe sheets. The interleaf members include indicia that identifies the leadframes sheets. The stack of leadframe sheets is loaded onto an assembly machine. A first interleaf member is removed from the first leadframe sheet. The first leadframe sheet is transferred onto a mounting surface of the assembly machine. Semiconductor die are attached to leadframes on the first leadframe sheet. The method can include reading the indicia from the first interleaf member to determine a part number and lead finish for the first leadframe sheet, verifying the part number for the first leadframe sheet by comparing to a build list, and transferring the first leadframe sheet onto a mounting surface of the assembly machine only if the part number is verified.

Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a base structure having a die paddle, an outer lead, and an inner lead between the die paddle and the outer lead, with a pre-plated finish on a base structure system side of the base structure; mounting an integrated circuit device to a side of the die paddle opposite the paddle system side; attaching an interconnect to the integrated circuit device and a side of the inner lead opposite the inner lead system side; applying an encapsulation around the integrated circuit device, the interconnect, and the base structure with the pre-plated finish exposed from the encapsulation; and forming an inward channel in the encapsulation to electrically isolate the inner lead.

Abstract: A microelectronic assembly can include a microelectronic element and a lead frame having a first unit and a second unit overlying the first unit and assembled therewith. The first unit can have a first metal layer comprising a portion of the thickness of the lead frame and including terminals and first conductive elements extending away therefrom. The second unit can have a second metal layer comprising a portion of the thickness of the lead frame and including bond pads and second conductive elements extending away therefrom. The first and second units each can have an encapsulation supporting at least portions of the respective first and second conductive elements. At least some of the second conductive elements can overlie portions of corresponding ones of the first conductive elements and can be joined thereto. The microelectronic element can have contacts electrically connected with the bond pads of the lead frame.

Abstract: A lead carrier provides support for a semiconductor device during manufacture. The lead carrier includes a temporary support member with multiple package sites. Each site includes a die attach pad surrounded by terminal pads. The pads are formed of multiple materials including a lower layer and a body portion. An upper layer can also be provided over the body portion. A chip is mounted upon the die pad and wire bonds extend from the chip to the terminal pads. These parts are all encapsulated within a mold compound. The body portion is preferably formed by providing a matrix of metal powder and a suspension medium at locations where the pads are to be located. Heat is applied to disperse the suspension medium and sinter the metal powder to form the body portion. After encapsulation the temporary support member can be peeled away and the package sites isolated from each other.

Abstract: An object of the present invention is to improve the quality control of a semiconductor device. By forming an inscription comprising a culled or pixel skipping pattern of dimples on the upper surface of a die pad in a QFN, it is possible to confirm the inscription by X-ray inspection or the like even after individuation and specify a cavity of a resin molding die. Further, it is possible to specify the position of a device region in a lead frame. As a result, when a defect appears, it is possible to sort a defective QFN by appearance inspection and improve quality control in the assembly of a QFN.

Abstract: The present invention relates to an epoxy resin composition for an optical semiconductor device, including the following ingredients (A) to (E): (A) an epoxy resin; (B) a curing agent; (C) a white pigment; (D) an inorganic filler; and (E) a silane coupling agent, in which a total content of the ingredient (C) and the ingredient (D) is from 69 to 94% by weight of the whole of the epoxy resin composition, and the ingredient (E) is contained in an amount satisfying the specific conditions.

Abstract: A bonded wire semiconductor device includes a sub-assembly including a semiconductor die having an active face with a set of internal electrical contact elements and an externally exposed set of electrical contact elements. A set of bond wires make respective electrical connections between the internal electrical contact elements and the externally exposed set of electrical contact elements. A molding compound encapsulates the semiconductor die with the active face embedded in the molding compound. The bond wires have the same length. The bond wires are bonded to the internal electrical contact elements and to the externally exposed electrical contact elements at first and second curved arrays and of bond positions respectively. The first and second curved arrays and of bond positions have corresponding concentric shapes.

Abstract: Warpage and breakage of integrated circuit substrates is reduced by compensating for the stress imposed on the substrate by thin films formed on a surface of the substrate. Particularly advantageous for substrates having a thickness substantially less than about 150 ?m, a stress-tuning layer is formed on a surface of the substrate to substantially offset or balance stress in the substrate which would otherwise cause the substrate to bend. The substrate includes a plurality of bonding pads on a first surface for electrical connection to other component.

Abstract: A method for the assembly of a semiconductor package that includes cleaning a surface of a chip and a surface of a heat removal device by reverse sputtering is given. The method includes sequentially coating the surface of the chip and the surface of the heat removal device with an adhesive layer, a barrier layer, and a protective layer over a target joining area. The chip and the heat removal device are placed into carrier fixtures and preheated to a target temperature. Then a metallic thermal interface material (TIM) preform is mechanically rolled onto the surface of the chip and the first and the second carrier fixtures are attached together such that the metallic TIM layer on the surface of the chip is joined to the coated surface of the heat removal device through a fluxless process. The method includes heating the joined carrier fixtures in a reflow oven.

Abstract: A method of manufacture of a wire-on-lead package system includes: providing a die attach paddle with paddle extensions distributed along the periphery of the die attach paddle, providing leadfingers surrounding the die attach paddle, attaching a semiconductor die to the die attach paddle wherein the semiconductor die is larger than the die attach paddle, and connecting bond wires between the semiconductor die and the leadfingers and between the semiconductor die and the paddle extensions.

Abstract: Disclosed herein are a power module package and a method for manufacturing the same. The power module package includes first and second lead frames disposed to face each other; ceramic coating layers formed on a portion of a first surface of both or one of both of the first and second lead frames; and semiconductor devices mounted on second surfaces of the first and second lead frames.

Abstract: A chip package structure including a leadframe, a chip, bonding wires and an encapsulant is provided. The leadframe includes a die pad, leads and an insulating layer. The die pad includes a chip mounting portion and a periphery portion. At the periphery portion, the die pad has a second upper surface lying between a first upper surface and a lower surface of the die pad. Each lead includes a suspending portion and a terminal portion. The suspending portion connects to the terminal portion and extends from the terminal portion towards the die pad. The insulating layer is disposed on the second upper surface of the periphery portion and connects the suspending portions to the die pad. The chip is disposed on the chip mounting portion. The bonding wires electrically connect the chip to the suspending portions. The encapsulant covers the chip, the bonding wires, the insulating layer, and the leadframe.

Abstract: A package structure and a package process are provided. The package structure comprises a carrier having a carrying portion and a plurality of supporting bar remnants disposed around and extending outward from the carrying portion, a chip mounted to the carrying portion, and an encapsulant disposed on the carrier and covering the chip, wherein the supporting bar remnants are encapsulated by the encapsulant, and each of the supporting bar remnants has a distal end shrank from an outer surface of the encapsulant. A package process for fabricating the package structure is also provided.

Abstract: In a method of manufacturing a semiconductor package including a wire binding process, a first end of the bonding wire is bonded to a first pad so as to form a first bond portion. A second end of the bonding wire is bonded to a second pad, wherein an interface surface between the bonding wire and the second pad has a first connecting area. The bonded second end of the bonding wire is scrubbed so as to form a second bond portion, wherein a new interface surface between the bonding wire and the second pad has a second connecting area larger than the first connecting area. A remainder of the bonding wire is separated from the second bond portion.

Abstract: A system for assembling electronic chips in a package, including a first lead frame defining chip reception areas; and a second lead frame defining chip coverage areas, the frames including, at least at their periphery, pairs of mutually-cooperating elements for maintaining the frames together.

Abstract: A method for fabricating a semiconductor package is disclosed that includes providing a supply of lead elements, mounting a plurality of the lead elements on a lead frame until a predetermined number of lead elements are placed on the lead frame, and connecting other components on the lead frame to the lead elements.

Abstract: A method for manufacturing a thin semiconductor package includes providing a lead frame with a removable substrate that has an attaching surface attached to a first surface of the lead frame. The lead frame is formed from an electrically conductive sheet and has leads that extend inwardly from a lead frame boundary towards a central region of the lead frame. A semiconductor die is mounted on the removable substrate at the central region. The semiconductor die has a connection pad surface with die pads on it, and the connection pad surface is attached to the attaching surface of the removable substrate. The lead frame and die are encapsulated with a first encapsulant so that the lead frame is sandwiched between the first encapsulant and the removable substrate. The removable substrate is removed from the lead frame to expose the first surface of the lead frame and then the die pads are electrically connected to respective ones of the leads.

Abstract: According to an embodiment, a semiconductor device includes a first frame, a semiconductor element fixed to the first frame, a second frame, a third frame and a resin package. The second frame faces the first frame and is away from the first frame, the second frame being electrically connected to the semiconductor element via a metal wire. The resin package covers the semiconductor element, the first frame, and the second frame. The first frame and the second frame are exposed in one major surface of the resin package. The third frame juxtaposed to one of the first frame and the second frame, the third frame being continuously exposed from the major surface of the resin package to a side surface in contact with the major surface.

Abstract: A dug portion (50) in which a die-bonding material is filled is provided to a lower surface of a stamping nozzle (42) used in a step of applying the die-bonding material onto a chip mounting portion of a wiring board. Planar dimensions of the dug portion (50) are smaller than external dimensions of a chip to be mounted on the chip mounting portion. In addition, a depth of the dug portion (50) is smaller than a thickness of the chip. When the thickness of the chip is 100 ?m or smaller, a problem of crawling up of the die-bonding material to an upper surface of the chip is avoided by applying the die-bonding material onto the chip mounting portion using the stamping nozzle (42).

Abstract: A semiconductor module includes: an insulating plate; a plurality of metal patterns formed on the insulating plate and spaced apart from each other; a power device chip solder-joined on one the metal pattern; a lead frame solder-joined on the metal pattern to which the power device chip is not solder-joined, and on the power device chip; an external main electrode provided to an outer casing, and joined by wire bonding to the lead frame above the metal pattern to which the power device chip is not joined; and a sealing resin formed by potting to seal the power device chip, the lead frame, and the metal patterns.

Abstract: Disclosed is a multi-chip package having leadframe-type contact fingers, primarily comprising a leadframe, a non-conductive tape, a first chip and a second chip disposed on the first chip. The leadframe includes a die paddle on which the first chip is disposed and a plurality of first contact fingers, moreover, at least a second contact finger is integrally extended from the die paddle and is located among the first contact fingers so that the first and second contact fingers are arranged in a row. The non-conductive tape is attached onto the first and second contact fingers conforming to the arranging row of the first contact fingers so that the second contact finger is mechanically fastened with the first contact fingers. An encapsulant encapsulates the first chip, the second chip and the non-conductive tape with a plated metal layer formed on the bottom surfaces of the first and second contact fingers and exposed from the encapsulant.

Abstract: Disclosed herein are a power module package and a method for manufacturing the same. The power module package includes: a base substrate having grooves formed between a plurality of semiconductor device mounting areas; semiconductor devices mounted on the semiconductor device mounting areas of the base substrate; and a molding formed on the base substrate and in inner portions of the grooves.

Abstract: In order to remove plating burrs generated in etching step, there is provided a manufacturing method of semiconductor devices on each of unit leadframes in a leadframe material in which a plurality of the unit leadframes are arranged in plural rows or a single row, wherein at least two types of plating burr removals are conducted after a half-etching is performed onto a front surface side of the leadframe material, using a first plating layer as resist film.

Abstract: An electronic device includes at least one electronic component chip having a first conduction terminal and a control terminal on a first surface of the chip and a second conduction terminal on a second surface opposite the first surface of the chip. An insulating body embeds the chip. The insulating body includes a mounting surface and an electrically conductive heat-sink connected to the first conduction terminal on the first surface of the chip, but insulated from the control terminal. An opening in a first surface of the insulating body exposes a surface of the electrically conductive heat sink. The electrically conductive heat sink includes a perimeter cavity configured for alignment with an encircling configuration of the control terminal, wherein the perimeter cavity contains a material that insulates the control terminal from the heat sink.

Abstract: A microelectronic unit can include a lead frame and a device chip. The lead frame can have a plurality of monolithic lead fingers extending in a plane of the lead frame. Each lead finger can have a fan-out portion and a chip connection portion extending in the lead frame plane. The fan-out portions can have first and second opposed surfaces and a first thickness in a first direction between the opposed surfaces. The chip connection portions can have a second thickness smaller than the first thickness. The chip connection portions can define a recess below the first surface. The device chip can have a plurality of at least one of passive devices or active devices. The device chip can have contacts thereon facing the chip connection portions and electrically coupled thereto. At least a portion of a thickness of the device chip can extend within the recess.

Abstract: An apparatus for molding a semiconductor device includes an upper mold chase and a lower mold chase. The mold chases are capable of being aligned with each other, forming spaced cavities for receiving a lead frame array that includes semiconductor dies for encapsulation. The cavities are aligned in spaced, vertical columns and gates are provided at the opening of each column of cavities. A molding compound is passed through the gates and flows uninterrupted through each cavity and encapsulates the semiconductor dies.

Abstract: The present invention discloses a three-dimensional package structure. The first conductive element comprises a top surface, a bottom surface and a lateral surface. The conductive pattern disposed on the top surface of the first conductive element. A second conductive element is disposed on the conductive pattern. The first conductive element is electrically connected to the conductive pattern, and the second conductive element is electrically connected to the conductive pattern. In one embodiment, the shielding layer is a portion of the patterned conductive layer.

Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a lead array having an innermost space with an innermost lead having an inner lead profile different around an inner non-horizontal side of the innermost lead; forming a middle lead having a middle lead profile the same around a lead side of the middle lead; placing an integrated circuit in the innermost space adjacent to the innermost lead; and forming a package encapsulation over the integrated circuit, the innermost lead, and the middle lead.

Abstract: A method for attaching a metal surface to a carrier is provided, the method including: forming a first polymer layer over the metal surface; forming a second polymer layer over a surface of the carrier; and bringing the first polymer layer into physical contact with the second polymer layer such that at least one of an interpenetrating polymer structure and an inter-diffusing polymer structure is formed between the first polymer layer and the second polymer layer.

Abstract: A method of manufacture of an integrated circuit packaging system includes: removing a portion of a leadframe to form a partially removed region and an upper portion of a peripheral lead on the leadframe first side; mounting a first integrated circuit over the partially removed region with a first adhesive; forming a first molding layer directly on the first integrated circuit and the peripheral lead; removing a portion of a leadframe second side exposing the first adhesive; mounting a second integrated circuit on the first adhesive of the first integrated circuit; forming a first interconnection layer directly on the first integrated circuit with the first integrated circuit and the peripheral lead electrically connected; and forming a second interconnection layer directly on the second integrated circuit with the second integrated circuit and the peripheral lead electrically connected.

Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a package paddle; forming a lead adjacent to the package paddle; depositing a lead conductive cap on the lead, the lead conductive cap includes a nickel layer having a thickness between 2.55 ?m to 8.00 ?m deposited on the lead, a palladium layer deposited on the nickel layer, and a gold layer deposited on the palladium layer; mounting an integrated circuit over the package paddle; attaching an electrical connector between the lead conductive cap and the integrated circuit; and forming an encapsulation over the integrated circuit, a portion of the lead, and a portion of the package paddle.

Abstract: A lead frame for a light-emitting diode (LED). The lead frame includes a first lead and a second lead. Each lead includes a top portion and an integrated wire-clasping portion. The first and second top portions each angle away from the center of the lead frame to form an increasingly larger gap between the two leads. The wire-clasping portions of each lead initially lie in a common plane and are adjacent one another. After securing the wire to the wire-clasping portions of the lead frame, the leads of the lead frame are rotated or twisted approximately 90 degrees such that the wire-clasping portions of the leads are opposite one another, rather than lying in the same plane. The wires and attached lead frame are inserted into a lampholder, the lampholder recesses receiving the top tabs of the lead frame and holding the wires and lead frame in place.