Abstract: A semiconductor device including a semiconductor element, a die pad of a plane size smaller than that of the semiconductor element, a plurality of hanging leads extending from the die pad, and sealing resin for covering the semiconductor element, the die pad, and the hanging leads. The width of a first main surface of each hanging lead, integrated with the mounting surface of the die pad, is smaller than the width of a second main surface thereof, integrated with the opposite surface of the die pad.

Abstract: An integrated circuit packaging system, and a method of manufacture therefor, including: electrical terminals; circuitry protective material around the electrical terminals and formed to have recessed pad volumes; routable circuitry on the top surface of the circuitry protective material; and an integrated circuit die electrically connected to the electrical terminals.

Abstract: A circuit package includes: electronic circuitry, electrically conductive material forming multiple leads, and multiple connections between the electronic circuitry and the multiple leads. A portion of the electrically conductive material associated with the multiple leads (e.g., low impedance leads supporting high current throughput) is removed to accommodate placement of the electronic circuitry. Each of the multiple leads can support high current. The multiple connections between the multiple leads provide connectivity between circuit nodes on the electronic circuitry and pads disposed on a planar surface of the electronic circuit package.

Abstract: A method of manufacturing a lead frame, includes forming a rectangular first dimple includes, first inclined side surfaces inclined to a depth direction, and arranged in two opposing sides in one direction, and standing side surfaces standing upright to a depth direction, and arranged in two opposing sides in other direction, on a backside of a die pad by a first stamping, and forming a second dimple having second inclined side surfaces inclined on the backside of the die pad by a second stamping, such that a second inclined side surfaces of the second dimple are arranged in side areas of the standing side surfaces of the first dimple, wherein the standing side surfaces are transformed into reversed inclined side surfaces inclined to a reversed direction to the first inclined side surfaces, and a front side of the die pad is semiconductor element mounting surface.

Abstract: Embodiments provide provides a chip package. The chip package may include a leadframe having a die pad and a plurality of lead fingers; a first chip attached to the die pad, the first chip being bonded to one or more of the lead fingers via a first set of wire bonds; a second chip bonded to one or more of the lead fingers via flip chip; and a heat slug attached to the second chip.

Abstract: An optoelectronic component includes a circuit board having a top side with a chip connection region, an optoelectronic semiconductor chip fixed to the chip connection region, a housing body fixed to the circuit board at the top side of the circuit board and having a reflector region, wherein the reflector region includes an opening in the housing body, the optoelectronic semiconductor chip being arranged in the opening, and the housing body is formed with a plastics material which is metallized at least in selected locations in the reflector region.

Abstract: An electronic device assembly that includes a die and a substrate, and optionally a lead frame and a heat spreader. The die is characterized as an electronic device in die form, and has a polished die region. The substrate has a polished substrate region in direct contact with the polished die region. The polished die region and the polished substrate region have surface finishes effective to attach the die to the substrate by way of an atomic bond. The lead-frame has a polished lead-frame region, and the heat spreader has a polished heat spreader region. These polished regions may also be attached to the polished die region or the polished substrate region by way of an atomic bond.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a terminal having a top with a depression; applying a dielectric material in the depression, the dielectric material having a gap formed therein and exposing a portion of the top therefrom; forming a trace within the gap and in direct contact with the top, the trace extending laterally over an upper surface of the dielectric material; and connecting an integrated circuit to the terminal through the trace.

Abstract: Provided is a semiconductor package having a power device and methods of fabricating the same. The semiconductor package includes a lead frame, a polymer layer component on the lead frame, a metal layer component on the polymer layer component, and a semiconductor chip on the metal layer component. The polymer layer component may include a material formed by adding alumina Al2O3, an aluminum nitride (AlN), or a boron nitride BN to an epoxy resin. The polymer layer component may have high thermal conductivity and good electric insulating characteristics.

Abstract: A method of manufacturing a semiconductor package includes providing a carrier and attaching at least one semiconductor piece to the carrier. An encapsulant is deposited onto the at least one semiconductor piece to form an encapsulated semiconductor arrangement. The encapsulated semiconductor arrangement is then singulated in at least two semiconductor packages, wherein each package includes a semiconductor die separated from the semiconductor piece during singulation.

Abstract: A method and system for forming a thin semiconductor device are disclosed. In one embodiment, a lead frame is provided over a carrier. At least one semiconductor chip is provided on the lead frame and the at least one semiconductor chip is enclosed with an encapsulating material. The thickness of the at least one semiconductor chip and the encapsulating material are reduced. At least one through connection is formed in the encapsulating material and at least one electrical contact element is formed over the at least one semiconductor chip and the at least one through connection.

Abstract: A semiconductor encapsulation comprises a lead frame further comprising a chip carrier and a plurality of pins in adjacent to the chip carrier. A plurality of grooves opened from an upper surface of the chip carrier partially dividing the chip carrier into a plurality of chip mounting areas. A bottom portion of the grooves is removed for completely isolate each chip mounting area, wherein a width of the bottom portion of the grooves removed is smaller than a width of the grooves. In one embodiment, a groove is located between the chip carrier and the pins with a bottom portion of the groove removed for isolate the pins from the chip carrier, wherein a width of the bottom of the grooves removed is smaller than a width of the grooves.

Abstract: The multi-chip leadless module 200 has integrated circuit (IC) 150, dual n-channel mosfet 110, IC leads 210, 211, 212, gate leads 213, 213, and source leads 217-220 encapsulated in resin 250. The IC 150 and the dual n-channel mosfet 110 are mounted face down on the leads. IC leads 210, 211, 212 are made of planar metal and connect, respectively, to the electrodes TEST, VDD and VM on the IC 150 using a flip chip technique to assemble the leads on copper pillars or copper studs.

Abstract: A semiconductor device comprises an aluminum alloy lead-frame with a passivation layer covering an exposed portion of the aluminum alloy lead-frame. Since aluminum alloy is a low-cost material, and its hardness and flexibility are suitable for deformation process, such as punching, bending, molding and the like, aluminum alloy lead frame is suitable for mass production; furthermore, since its weight is much lower than copper or iron-nickel material, aluminum alloy lead frame is very convenient for the production of semiconductor devices.

Abstract: The invention relates to a power semiconductor device and a preparation method, particularly relates to preparation of stacked dual-chip packaging structure of MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) using flip chip technology with two interconnecting plates. The first chip is flipped and attached on the base such that the first chip is overlapped with the third pin; the back metal layer of the first chip is connected to the bonding strip of the first pin through a first interconnecting plate; the second chip is flipped and attached on a main plate portion of the first interconnecting plate such that the second chip is overlapped with the fourth pin; and the back metal layer of the second chip is connected to the bonding strip of the second pin through the second interconnecting plate.

Abstract: Using side-wall conductor leads insulated by side-wall insulators to form package level conductor leads for active circuits manufactured on silicon substrate, the preferred embodiments of the present invention significantly reduces the areas of surface mount package chips. Besides area reduction, these methods also provide significant cost saving and reduction in parasitic impedance.

Abstract: A semiconductor package includes a lead frame, at least one chip and a molding compound. The lead frame comprises a plurality of leads, each lead comprises a first end portion and at least one coupling protrusion, wherein the first end portion comprises a first upper surface, the coupling protrusion comprises a ring surface and is integrally formed as one piece with the first upper surface. The chip disposed on top of the leads comprises a plurality of bumps and a plurality of solders, the coupling protrusions embed into the solders to make the ring surfaces of the coupling protrusions cladded with the solders. The solders cover the first upper surfaces. The chip and the leads are cladded with the molding compound.

Abstract: Optical device packages and systems are disclosed. In one embodiment, a system may comprise first and second optical device packages. A respective first and second optical path length may be associated with the first and second optical device packages. The first and second optical path lengths may be adjusted differently. However, respective first and second sets of external dimensions of the first and second optical device packages may be the same or substantially the same. In one embodiment, one or more Quad Flat No Lead (QFN) packages may be employed.

Abstract: A semiconductor package and a fabrication method thereof are disclosed. The fabrication method includes the steps of providing a semiconductor chip having an active surface and a non-active surface opposing to the active surface, roughening a peripheral portion of the non-active surface so as to divide the non-active surface into the peripheral portion formed with a roughened structure and a non-roughened central portion, mounting the semiconductor chip on a chip carrier via a plurality of solder bumps formed on the active surface, forming an encapsulant on the chip carrier to encapsulate the semiconductor chip. The roughened structure formed on the peripheral portion of the non-active surface of the semiconductor chip can reinforce the bonding between the semiconductor chip and the encapsulant, and the non-roughened central portion of the non-active surface of the semiconductor chip can maintain the structural strength of the semiconductor chip.

Abstract: An integrated circuit package may be formed using a leadframe having an open space extending therethrough. A shunt is located within the open space such that it is not in contact with any portion of the leadframe. Tape may be applied to the lower surface of the leadframe to support the shunt and hold it in place relative to the leadframe until wirebonding and encapsulation have been completed. Thereafter, the tape may be removed.

Abstract: Embodiments of the present disclosure describe a packaged semiconductor device that reduces stress on a semiconductor device caused by thermal expansion of the insulating material used in the packaged semiconductor device. In one embodiment, an inactive semiconductor device is coupled to the top of active semiconductor device. Both the inactive and active devices are encapsulated by the insulating material. The configuration of the inactive device is selected based on its ability to absorb the expansion of the insulating material at operating temperature.

Abstract: A packaged semiconductor device may include a leadframe and a die carrier mounted to the leadframe. The die carrier is formed from an electrically and thermally conductive material. A die is mounted to a surface of the die carrier with die attach material having a melting point in excess of 240° C. A first electrical interconnect couples the die and the leadframe. A housing covers portions of the leadframe, die carrier, die and first electrical interconnect.

Abstract: A device including a semiconductor chip and metal foils. One embodiment provides a device including a semiconductor chip having a first electrode on a first face and a second electrode on a second face opposite to the first face. A first metal foil is attached to the first electrode of the semiconductor chip in an electrically conductive manner. A second metal foil is attached to the second electrode of the semiconductor chip in an electrically conductive manner.

Abstract: An embodiment includes a method that includes encapsulating a die and at least a portion of a lead-frame in a mold to form a package body. At least one primary lead attached to the lead-frame extends from the package body. The method includes etching a feature to within a threshold in an exposed die pad. The exposed die pad comprises a first surface that is prepared for etching and a second surface opposite to the first surface and attached to the die. The method includes positioning the die within a footprint of the exposed die pad, connecting the die to at least one primary lead, and connecting the feature to the die.

Abstract: A method of manufacturing an LED package includes mounting a large panel frame/substrate (LPF/S) having a substantially square shape to a ring. The LPF/S includes a plurality of die pads and a corresponding plurality of leads arranged in a matrix pattern. Each of the die pads includes a planar chip attach surface. An LED chip is attached to the planar chip attach surface of each of the die pads. An encapsulant material is applied overlaying the LED chips and at least a part of the LPF/S. Each die pad and corresponding leads are separated from the LPF/S to form individual LED packages. The steps of attaching the LED chips and applying the encapsulant material are performed while the LPF/S is mounted to the ring.

Abstract: A chip package is provided, the chip package including: a carrier including at least one cavity; a chip disposed at least partially within the at least one cavity; at least one intermediate layer disposed over at least one side wall of the chip; wherein the at least one intermediate layer is configured to thermally conduct heat from the chip to the carrier.

Abstract: An integrated circuit is provided. The integrated circuit includes: a chip and encapsulation material covering at least three sides of the chip, the encapsulation material being formed from adhesive material. The integrated circuit includes a carrier adhered to the chip by means of the encapsulation material.

Abstract: One embodiment is a packaged device having multiple layers. Another embodiment is a method of forming a packaged device having multiple layers. Conductive layers and insulating layers can be formed with openings exposing semiconductor devices. The semiconductor devices can be wire-bonded to the conductive layers. In some embodiments, parasitic effects and a relative footprint of the packaged device can be reduced.

Abstract: The present invention relates to structure and manufacture method for multi-row lead frame and semiconductor package, the method characterized by forming a pad portion on a metal material (first step); performing a surface plating process or organic material coating following the first pattern formation (second step); forming a second pattern on the metal material (third step); and packaging a semiconductor chip following the second pattern formation (fourth step), whereby an under-cut phenomenon is minimized by applying a gradual etching.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing an array of leads having a jumper lead and a covered contact; coupling an insulated bonding wire between the jumper lead and the covered contact; attaching an integrated circuit die over the covered contact; and coupling a bond wire between the integrated circuit die and the jumper lead including coupling the integrated circuit die to the covered contact through the insulated bonding wire.

Abstract: A plastic package includes a plurality of terminal members each having an outer terminal, an inner terminal, and a connecting part connecting the outer and the inner terminal; a semiconductor device provided with terminal pads connected to the inner terminals with bond wires; and a resin molding sealing the terminal members, the semiconductor device and the bond wires therein. The inner terminals of the terminal members are thinner than the outer terminals and have contact surfaces. The upper, the lower and the outer side surfaces of the outer terminals, and the lower surfaces of the semiconductor device are exposed outside. The inner terminals, the bond wires, the semiconductor device and the resin molding are included in the thickness of the outer terminals.

Abstract: A semiconductor device includes an electrically conducting carrier and a semiconductor chip disposed over the carrier. The semiconductor device also includes a porous diffusion solder layer provided between the carrier and the semiconductor chip.

Abstract: The multi-chip leadless module 200 has integrated circuit (IC) 150, dual re-channel mosfet 110, IC leads 210, 211, 212, gate leads 213, 213, and source leads 217-220 encapsulated in resin 250. The IC 150 and the dual n-channel mosfet 110 are mounted face down on the leads. IC leads 210, 211, 212 are made of planar metal and connect, respectively, to the electrodes TEST, VDD and VM on the IC 150 using a flip chip technique to assemble the leads on copper pillars or copper studs.

Abstract: This invention is directed to provide a method of manufacturing a resin molded semiconductor device with high reliability by preventing a resin leakage portion from occurring due to burrs on a lead frame formed by punching. The method of manufacturing the resin molded semiconductor device according to the invention includes bonding a semiconductor die on an island in a lead frame, electrically connecting the semiconductor die with the lead frame, resin-molding the lead frame on which the semiconductor die is bonded, and applying prior to the resin-molding a compressive pressure that is higher than a clamping pressure applied in the resin-molding to a region of the lead frame being clamped by molds in the resin-molding of the lead frame.

Abstract: Provided are a socket, a semiconductor package, a test device and a method of manufacturing a semiconductor package. A socket to test a semiconductor package comprising a housing, a trench receiving a semiconductor package in the housing, at least one probe connected to the semiconductor package at a bottom of the trench, and at least one connector electrically connecting a plurality of contact points exposed at a side of the semiconductor package when the semiconductor package is inserted into the trench. A semiconductor package with contacts exposed from a side of a package substrate, and a method of manufacturing such a semiconductor package are also disclosed.

Abstract: A process for assembling a semiconductor device includes providing a lead frame having a native plane and a plurality of leads having a native lead pitch. The process includes trimming and forming a first subset of the plurality of leads to provide a first row of leads. The process includes trimming and forming a second subset of the plurality of leads to provide a second row of leads. At least one subset of leads is formed with an obtuse angle relative to the native plane such that lead pitch associated with the first or second subset of leads is greater than the native lead pitch.

Abstract: A lead frame has a flag, a peripheral frame, and main tie bars coupling the flag to the peripheral frame. At least one cross tie bar extends between two of the main tie bars and an inner row of external connector pads extending from an inner side of the cross tie bar and an outer row of external connector pads extending from an outer side of the cross tie bar. Both an inner non-electrically conductive support bar and an outer non-electrically conductive support bar are attached across the two of the main tie bars. The inner non-electrically conductive support bar is attached to upper surfaces of the two of the main tie bars and to upper surfaces of the inner row of the external connector pads.

Abstract: A semiconductor package is assembled using first and second lead frames. The first lead frame includes a die flag and the second lead frame includes lead fingers. When the first and second lead frames are mated, the lead fingers surround the die flag. Side surfaces of the die flag are partially etched to form an extended die attach surface on the die flag, and portions of the top surface of each of the lead fingers also are partially etched to form lead finger surfaces that are complementary with the etched side surfaces of the die flag. A semiconductor die is attached to the extended die attach surface and bond pads of the semiconductor die are electrically connected to the lead fingers. An encapsulating material covers the die, electrical connections, and top surfaces of the die flag and lead fingers.

Abstract: Packages and methods for 3D integration are disclosed. In various embodiments, a first integrated device die having a hole is attached to a package substrate. A second integrated device die can be stacked on top of the first integrated device die. At least a portion of the second integrated device die can extend into the hole of the first integrated device die. By stacking the two dies such that the portion of the second integrated device die extends into the hole, the overall package height can advantageously be reduced.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a die attach pad integrally connected to a connector portion and a lead; attaching an integrated circuit die to the die attach pad; connecting an internal interconnect to the integrated circuit die and the lead; forming an encapsulation over the integrated circuit die; removing the connector portion to separate the die attach pad and the lead; and forming an isolation cover between the die attach pad and the lead.

Abstract: Packaging structures and methods for semiconductor devices are disclosed. In one embodiment, a substrate for packaging a semiconductor device includes a core substrate, an insulating material disposed over the core substrate, and conductive lines disposed in the insulating material. Contact pads are disposed over the insulating material and the conductive lines. The contact pads are disposed in an integrated circuit mounting region of the core substrate. A solder mask define (SMD) material is disposed over the insulating material. Portions of the contact pads are exposed through openings in the SMD material. A stress-relief structure (SRS) is disposed in the SMD material proximate the contact pads. The SRS is disposed entirely in the integrated circuit mounting region of the core substrate.

Abstract: A method of manufacture of an integrated circuit packaging system includes providing a lead-frame having an inner portion and a bottom cover directly on a bottom surface of the inner portion; forming an insulation cover directly on the lead-frame with the insulation cover having a connection opening; connecting an integrated circuit die to the lead-frame through the connection opening with the integrated circuit die over the insulation cover; forming a top encapsulation directly on the insulation cover; forming a routing layer having a conductive land directly on the bottom cover by shaping the lead-frame; and forming a bottom encapsulation directly on the conductive land with the bottom cover exposed from the bottom encapsulation.

Abstract: There is provided a semiconductor package capable of significantly reducing a size of a power semiconductor package including a power semiconductor device and a control device. The semiconductor package includes a lead frame including a first frame and a second frame; at least one first electronic device mounted on the first frame; a substrate engaged with the second frame and having one surface on which a wiring pattern is formed; and at least one second electronic device mounted on the substrate and electrically connected to the wiring pattern, a portion of the wiring pattern electrically connected to the at least one second electronic device being formed to have a line width smaller than an internal lead of the lead frame.

Abstract: A structure and method to improve saw singulation quality and wettability of integrated circuit packages (140) assembled with lead frames (112) having half-etched recesses (134) in leads. A method of forming a semiconductor device package includes providing a lead frame strip (110) having a plurality of lead frames. Each of the lead frames includes a depression (130) that is at least partially filled with a material (400) prior to singulating the strip.

Abstract: In accordance with an embodiment of the present invention, a semiconductor device includes a leadframe having a plurality of leads and a die paddle and a semiconductor module attached to the die paddle of the leadframe. The semiconductor module includes a first semiconductor chip disposed in a first encapsulant. The semiconductor module has a plurality of contact pads coupled to the first semiconductor chip. The semiconductor device further includes a plurality of interconnects coupling the plurality of contact pads with the plurality of leads, and a second encapsulant disposed at the semiconductor module and the leadframe.

Abstract: One embodiment is directed towards a method of manufacturing a packaged circuit. The method includes partially etching an internal surface of a lead frame at dividing lines between future sections of the lead frame as first partial etch. One or more dies are attached to the internal surface of the lead frame and encapsulated. The method also includes partially etching an external surface of the lead frame at the dividing lines to disconnect different sections of lead frame as a second partial etch, wherein the second partial etch removes a laterally wider portion of the lead frame than the first partial etch of the internal surface; and partially etching the external surface of the lead frame as a third partial etch, wherein the third partial etch overlaps a portion of the second partial etch and extends deeper into the lead frame than the second partial etch.

Abstract: In accordance with an embodiment of the present invention, a semiconductor device includes a semiconductor chip disposed over a lead frame, and a clip disposed over the semiconductor chip. A major surface of the semiconductor chip includes a contact pad and a control contact pad. The contact pad has a first portion along a first side of the control contact pad and a second portion along an opposite second side of the control contact pad. The clip electrically couples the first portion and the second portion with a first lead of the lead frame. A wire bond electrically couples the control contact pad with a second lead of the lead frame.

Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a lead having a lead overhang at an obtuse angle to a lead top side and having a lead ridge protruding from a lead non-horizontal side, the lead overhang having a lead overhang-undercut side at an acute angle to a lead overhang non-horizontal side; forming a lead conductive cap completely covering the lead overhang non-horizontal side and the lead top side; forming a package paddle adjacent the lead; mounting an integrated circuit over the package paddle; and forming an encapsulation over the integrated circuit, the package paddle, and the lead.

Abstract: An electric device and a method of making an electric device are disclosed. In one embodiment the electric device comprises a component comprising a component contact area and a carrier comprising a carrier contact area. The electric device further comprises a first conductive connection layer connecting the component contact area with the carrier contact area, wherein the first conductive connection layer overlies a first region of the component contact area and a second connection layer connecting the component contact area with the carrier contact area, wherein the second connection layer overlies a second region of the component contact area, and wherein the second connection layer comprises a polymer layer.

Abstract: A semiconductor package is provided, including: an insulating layer; a semiconductor element embedded in the insulating layer; an adhesive body embedded in the insulating layer, wherein a portion of the semiconductor element is embedded in the adhesive body; a patterned metal layer embedded in the adhesive body and electrically connected to the semiconductor element; and a redistribution structure formed on the insulating layer and electrically connected to the patterned metal layer. By embedding the semiconductor element in the adhesive body, the present invention can securely fix the semiconductor element at a predetermined position without any positional deviation, thereby improving the product yield.