Abstract: An integrated circuit structure includes an integrated circuit structure includes a substrate, insulation regions over the substrate, and a fin field-effect transistor (FinFET). The FinFET includes a plurality of fins over the substrate, wherein each of the plurality of fins comprises a first fin portion and a second fin portion, a gate stack on a top surface and sidewalls of the first fin portion of each of the plurality of fins, an epitaxial semiconductor layer comprising a portion directly over the second fin portion of each of the plurality of fins, and sidewall portions directly over the insulation regions, and a silicide layer on, and having an interface with, the epitaxial layer, wherein a peripheral ratio of a total length of an effective silicide peripheral of the FinFET to a total length of peripherals of the plurality of fins is greater than 1.

Abstract: A semiconductor device includes a semiconductor body having a compound semiconductor material on a substrate. The compound semiconductor material has a channel region. A source region extends to the compound semiconductor material. A drain region also extends to the compound semiconductor material and is spaced apart from the source region by the channel region. An insulating region is buried in the semiconductor body between the compound semiconductor material and the substrate in an active region of the semiconductor device. The active region includes the source, the drain and the channel region of the device. The insulating region is discontinuous over a length of the channel region between the source region and the drain region.

Abstract: Some embodiments relate to an integrated circuit (IC). The IC includes a semiconductor substrate having an upper surface with a source region and drain region proximate thereto. A channel region is disposed in the substrate between the source region and the drain region. A gate electrode is disposed over the channel region and separated from the channel region by a gate dielectric. Sidewall spacers are formed about opposing sidewalls of the gate electrode. Upper outer edges of the sidewall spacers extend outward beyond corresponding lower outer edges of the sidewall spacers. A liner is disposed about opposing sidewalls of the sidewall spacers and has a first thickness at an upper portion of liner and a second thickness at a lower portion of the liner. The first thickness is less than the second thickness. Other embodiments are also disclosed.

Abstract: A method of forming a device is disclosed. A substrate having a device region is provided. The device region comprises a source region, a gate region and a drain region defined thereon. A gate is formed in the gate region, a source is formed in the source region and drain is formed in the drain region. A trench is formed in an isolation region in the device region. The isolation region underlaps a portion of the gate. An etch stop (ES) stressor layer is formed over the substrate. The ES stressor layer lines the trench.

Abstract: A limited number of cycles of atomic layer deposition (ALD) of Hi-K material followed by deposition of an interlayer dielectric and application of further Hi-K material and optional but preferred annealing provides increased Hi-K material content and increased breakdown voltage for input/output (I/O) transistors compared with logic transistors formed on the same chip or wafer while providing scalability of the inversion layer of the I/O and logic transistors without significantly compromising performance or bias temperature instability (BTI) parameters.

Abstract: A MOS transistor includes a gate structure and a spacer. The gate structure is located on a substrate. The spacer is located on the substrate beside the gate structure, and the spacer includes an L-shaped inner spacer and an outer spacer, wherein the outer spacer is located on the L-shaped inner spacer, and the two ends of the L-shaped inner spacer protrude from the outer spacer. Moreover, the present invention also provides a MOS transistor process for forming the MOS transistor.

Abstract: Transistors, methods of manufacturing thereof, and image sensor circuits are disclosed. In one embodiment, a transistor includes a buried channel disposed in a workpiece, a gate dielectric disposed over the buried channel, and a gate layer disposed over the gate dielectric. The gate layer comprises an I shape in a top view of the transistor.

Abstract: A Metal-Oxide Semiconductor (MOS) transistor includes a substrate having a topside semiconductor surface doped with a first dopant type having a baseline doping level. A well is formed in the semiconductor surface doped with a second doping type. The well forms a well-substrate junction having a well depletion region. A retrograde doped region is below the well-substrate junction doped with the first dopant type having a peak first dopant concentration of between five (5) and one hundred (100) times above the baseline doping level at a location of the peak first dopant concentration, wherein with zero bias across the well-substrate junction at least (>) ninety (90) % of a total dose of the retrograde doped region is below the bottom of the well depletion region. A gate structure is on the well. Source and drain regions are on opposing sides of the gate structure.

Abstract: A transistor including a source; a drain; a gate region, the gate region including a gate; an island; and a gate oxide, wherein the gate oxide is positioned between the gate and the island; and the gate and island are coactively coupled to each other; and a source barrier and a drain barrier, wherein the source barrier separates the source from the gate region and the drain barrier separates the drain from the gate region.

Abstract: The present disclosure utilizes the MEMS (Micro Electro Mechanical Systems) process and packaging method to produce a microsystem for analyzing blood which is capable of detecting several kinds of ions. The microsystem for analyzing blood has a miniaturized reference electrode, so size of the microsystem can be greatly reduced. The microsystem further has a gate detecting area larger than a conventional planar ISE or a conventional ISFET does, so interference with signals can be avoided, and packaging difficulty and blood leakage can be reduced. Therefore, the microsystem is thin and small, reacts rapidly, and has a high accuracy, and a high compatibility with IC (integrated circuit) process. In addition, the microsystem has high stability of long-term potential, low offset-potential characteristics, low alternating current impedance, high stability of dynamic reference potential, low electrochemical noises and high reproducibility of the electrode.

Abstract: The present disclosure provides a FinFET element. The FinFET element includes a germanium-FinFET element (e.g., a multi-gate device including a Ge-fin). In one embodiment, device includes a fin having a first portion including Ge and a second portion, underlying the first portion and including an insulating material (e.g., silicon dioxide). A gate structure may be formed on the fin.

Abstract: An electronic device can include a gate electrode and a gate tap that makes an unlanded contact to the gate electrode. The electronic device can further include a source region and a drain region that may include a drift region. In an embodiment, the gate electrode has a height that is greater than its width. In another embodiment, the electronic device can include gate taps that spaced apart from each other, wherein at least some of the gate taps contact the gate electrode over the channel region. In a further embodiment, at a location where the gate tap contacts the gate electrode, the gate tap is wider than the gate electrode. A variety of processes can be used to form the electronic device.

Abstract: A method patterns at least one pair of openings through a protective layer and into a substrate. The openings are positioned on opposite sides of a channel region of the substrate. The method forms sidewall spacers along the sidewalls of the openings and removes additional substrate material from the bottom of the openings. The material removal process creates an extended bottom within the openings. The method forms a first strain producing material within the extended bottom of the openings. The method removes the sidewall spacers and forms a second material within the remainder of the openings between the first strain producing material and the top of the openings. The method removes the protective layer and forms a gate dielectric and a gate conductor on the horizontal surface on the substrate adjacent the channel region. The second material comprises source and drain regions.

Abstract: A semiconductor device includes an input/output pad, and a data transfer unit configured to form a parasitic diode between the input/output pad and a power supply terminal thereof to discharge an introduced electrostatic discharge (ESD), and form a data transfer path between the input/output pad and an internal circuit in response to a control signal.

Abstract: A semiconductor structure (1) comprises a dielectric layer (2) including a dielectric material having a dielectric constant higher than that of silicon oxide; a channel region (3) including a compound semiconductor material; a passivation layer (4) including a passivation material between the channel region (3) and the dielectric layer (2); and a barrier layer (5) including a barrier material between the dielectric layer (2) and the passivation layer (4) for reducing a chemical reaction of the dielectric material of the dielectric layer (2) with the passivation material of the passivation layer (4).

Abstract: A high voltage metal oxide semiconductor device with low on-state resistance is provided. A multi-segment isolation structure is arranged under a gate structure and beside a drift region for blocking the current from directly entering the drift region. Due to the multi-segment isolation structure, the path length from the body region to the drift region is increased. Consequently, as the breakdown voltage applied to the gate structure is increased, the on-state resistance is reduced.

Abstract: A device with reduced gate resistance includes a gate structure having a first conductive portion and a second conductive portion formed in electrical contact with the first conductive portion and extending laterally beyond the first conductive portion. The gate structure is embedded in a dielectric material and has a gate dielectric on the first conductive portion. A channel layer is provided over the first conductive portion. Source and drain electrodes are formed on opposite end portions of a channel region of the channel layer. Methods for forming a device with reduced gate resistance are also provided.

Abstract: The present invention provides a method for manufacturing a semiconductor structure. The method can effectively reduce the contact resistance between source/drain regions and a contact layer by forming two contact layers of different thickness on the surfaces of the source/drain regions. Further, the present invention provides a semiconductor structure, which has reduced the contact resistance.

Abstract: A merged fin finFET and method of fabrication. The finFET includes: two or more single-crystal semiconductor fins on a top surface of an insulating layer on semiconductor substrate, each fin of the two or more fins having a central region between and abutting first and second end regions and opposite sides, top surfaces and sidewalls of the two or more fins are (100) surfaces and the longitudinal axes of the two or more fins aligned with a [100] direction; a gate dielectric layer on each fin of the two or more fins; an electrically conductive gate over the gate dielectric layer over the central region of each fin of the of two or more fins; and a merged source/drain comprising an a continuous layer of epitaxial semiconductor material on ends of each fin of the two or more fins, the ends on a same side of the conductive gate.

Abstract: A method of forming a semiconductor structure may include preparing a continuous active layer in a region of the substrate and forming a plurality of adjacent gates on the continuous active layer. A first raised epitaxial layer may be deposited on a recessed region of the continuous active layer between a first and a second one of the plurality of gates, whereby the first and second gates are adjacent. A second raised epitaxial layer may be deposited on another recessed region of the continuous active layer between the second and a third one of the plurality of gates, whereby the second and third gates are adjacent. Using a cut mask, a trench structure is etched into the second gate structure and a region underneath the second gate in the continuous active layer. The trench is filled with isolation material for electrically isolating the first and second raised epitaxial layers.

Abstract: A device includes a conductive layer including a bottom portion, and a sidewall portion over the bottom portion, wherein the sidewall portion is connected to an end of the bottom portion. An aluminum-containing layer overlaps the bottom portion of the conductive layer, wherein a top surface of the aluminum-containing layer is substantially level with a top edge of the sidewall portion of the conductive layer. An aluminum oxide layer is overlying the aluminum-containing layer. A copper-containing region is over the aluminum oxide layer, and is spaced apart from the aluminum-containing layer by the aluminum oxide layer. The copper-containing region is electrically coupled to the aluminum-containing layer through the top edge of the sidewall portion of the conductive layer.

Abstract: Among other things, one or more techniques for enhancing device (e.g., transistor) performance are provided herein. In one embodiment, device performance is enhanced by forming an extended dummy region at an edge of a region of a device and forming an active region at a non-edge of the region. Limitations associated with semiconductor fabrication processing present in the extended dummy region more so than in non-edge regions. Accordingly, a device exhibiting enhanced performance is formed by connecting a gate to the active region, where the active region has a desired profile because it is comprised within a non-edge of the region. A dummy device (e.g., that may be less responsive) may be formed to include the extended dummy region, where the extended dummy region has a less than desired profile due to limitations associated with semiconductor fabrication processing, for example.

Abstract: A system includes a silicon carbide (SiC) semiconductor device and a hermetically sealed packaging enclosing the SiC semiconductor device. The hermetically sealed packaging is configured to maintain a particular atmosphere near the SiC semiconductor device. Further, the particular atmosphere limits a shift in a threshold voltage of the SiC semiconductor device to less than 1 V during operation.

Abstract: Techniques are disclosed for incorporating high mobility strained channels into fin-based transistors (e.g., FinFETs such as double-gate, trigate, etc), wherein a stress material is cladded onto the channel area of the fin. In one example embodiment, silicon germanium (SiGe) is cladded onto silicon fins to provide a desired stress, although other fin and cladding materials can be used. The techniques are compatible with typical process flows, and the cladding deposition can occur at a plurality of locations within the process flow. In some cases, the built-in stress from the cladding layer may be enhanced with a source/drain stressor that compresses both the fin and cladding layers in the channel. In some cases, an optional capping layer can be provided to improve the gate dielectric/semiconductor interface. In one such embodiment, silicon is provided over a SiGe cladding layer to improve the gate dielectric/semiconductor interface.

Abstract: Semiconductor devices and methods for manufacturing the same are disclosed. In one embodiment, the method comprises: forming a first shielding layer on a substrate, and forming a first spacer on a sidewall of the first shielding layer; forming one of source and drain regions with the first shielding layer and the first spacer as a mask; forming a second shielding layer on the substrate, and removing the first shielding layer; forming the other of the source and drain regions with the second shielding layer and the first spacer as a mask; removing at least a portion of the first spacer; and forming a gate dielectric layer, and forming a gate conductor in the form of spacer on a sidewall of the second shielding layer or on a sidewall of a remaining portion of the first spacer.

Abstract: A method of manufacturing a tunnel field effect transistor is disclosed. The method comprises forming a two-step profile in a silicon substrate (100) using a patterned hard mask (104) covering the higher steps of said profile; forming a gate stack (114, 116) against the side wall of the higher step; forming spacers (122) on either side of the gate stack (118); and implanting a first type impurity (124) in the higher step and an opposite type impurity in the neighboring lower step (120), wherein at least the first type impurity is implanted using an angled implanting step after removing the patterned hard mask (104). In a preferred embodiment, the method further comprises forming a sacrificial spacer (108) against a side wall of a higher step and the side wall of the hard mask (104); further etching the lower step (106, 110) next to said spacer (108) and subsequently growing a further semiconductor portion (112) on said lower step and removing the spacer (108) prior to forming the gate stack.

Abstract: Memory devices and methods of operating memory devices are shown. Configurations described include a memory cell string having an elongated n type body region and having select gates with p type bodies. Configurations and methods shown can provide a reliable bias to a body region for memory operations such as erasing.

Abstract: A semiconductor device (1000) includes a thin film transistor having a gate line (3a), source and drain lines (13as, 13ad), and an island-like oxide semiconductor layer (7), and a capacitor element (105) having a first electrode (3b) formed from the same conductive film as the gate line (3s), a second electrode (13b) formed from the same conductive film as the source line (13as), and a dielectric layer positioned between the first electrode and the second electrode. A gate insulating film (5) has a layered structure including a first insulating layer (5A) containing an oxide and a second insulating layer (5B) disposed on the side closer to the gate electrode closer than the first insulating film and having a higher dielectric constant than the first insulating film, the layered structure being in contact with the oxide semiconductor layer (7). The dielectric layer includes the second insulating film (5B) but does not include the first insulating film (5A).

Abstract: Semiconductor structures and methods of manufacture semiconductors are provided which relate to heterojunction bipolar transistors. The method includes forming two devices connected by metal wires on a same wiring level. The metal wire of a first of the two devices is formed by selectively forming a metal cap layer on copper wiring structures.

Abstract: The present disclosure discloses a high voltage semiconductor device and the associated methods of manufacturing. In one embodiment, the high voltage semiconductor device comprises: an epitaxial layer, a first low voltage well formed in the epitaxial layer; a second low voltage well formed in the epitaxial layer; a high voltage well formed in the epitaxial layer, wherein the second low voltage well is surrounded by the high voltage well; a first highly doping region formed in the first low voltage well; a second highly doping region and a third highly doping region formed in the second low voltage well, wherein the third highly doping region is adjacent to the second highly doping region; a field oxide formed in the epitaxial layer as a shallow-trench isolation structure; and a gate region formed on the epitaxial layer.

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a bulk, a gate, a source, a drain and a bulk contact region. The gate is on the bulk. The source and the drain are in the bulk on opposing sides of the gate respectively. The bulk contact region is only in a region of the bulk adjacent to the source. The bulk contact region is electrically connected to the bulk.

Abstract: A method including providing a semiconductor substrate including a first semiconductor device and a second semiconductor device, the first and second semiconductor devices including dummy spacers, dummy gates, and extension regions; protecting the second semiconductor device with a mask; removing the dummy spacers from the first semiconductor device; and depositing in-situ doped epitaxial regions on top of the extension regions of the first semiconductor device.

Abstract: One illustrative device disclosed herein includes at least one fin comprised of a semiconducting material, a layer of gate insulation material positioned adjacent an outer surface of the fin, a gate electrode comprised of graphene positioned on the layer of gate insulation material around at least a portion of the fin, and an insulating material formed on the gate electrode.

Abstract: A method for forming a DRAM memory with a two-sided transistor includes: providing a silicon finFET structure having at least two fins, and a trench between the fins; forming high ohmic gates on either side of the fins; forming a hole between each pair of high ohmic gates to enable connection between the pair of high ohmic gates; forming a gate on one side of the trench and underneath one of the pair of high ohmic gate; forming a layer of oxide over the gate; and depositing tungsten in the trench to form a thick layer of metal at the bottom to form a word line.

Abstract: Embodiments of the invention provide an asymmetrical transistor device comprising a semiconductor substrate, a source region, a drain region and a channel region. The channel region is provided between the source and drain regions, the source, drain and channel regions being provided in the substrate. The device has a layer of a buried insulating medium provided below the source region and not below the drain region thereby forming an asymmetrical structure. The layer of buried insulating medium is provided in abutment with a lower surface of the source region.

Abstract: A semiconductor device includes a substrate having first and second regions, a device isolation layer on the substrate defining an active region in each of the first and second regions, a gate pattern on the active region of each of the first and second regions, and a first dopant region and a second dopant region in each of the first and second regions of the substrate, the gate pattern in each of the first and second regions being between respective first and second dopant regions. At least one of upper surfaces of the first and second dopant regions in the second region is lower in level than an upper surface of the substrate under the gate pattern in the second region, the first and second dopant regions in the second region having an asymmetric recessed structure with respect to the gate pattern in the second region.

Abstract: A method includes performing a grinding on a backside of a semiconductor substrate. An image sensor is disposed on a front side of the semiconductor substrate. An impurity is doped into a surface layer of the backside of the semiconductor substrate to form a doped layer. A multi-cycle laser anneal is performed on the doped layer.

Abstract: A metal-oxide-semiconductor laterally diffused device (HV LDMOS), particularly a lateral insulated gate bipolar junction transistor (LIGBT), and a method of making it are provided in this disclosure. The device includes a silicon-on-insulator (SOI) substrate having a drift region, two oppositely doped well regions in the drift region, two insulating structures over and embedded in the drift region and second well region, a gate structure, and a source region in the second well region over a third well region embedded in the second well region. The third well region is disposed between the gate structure and the second insulating structure.

Abstract: semiconductor device comprises a semiconductor substrate; a channel layer of at least a first III-V semiconductor compound above the semiconductor substrate; a gate stack structure above a first portion of the channel layer; a source region and a drain region comprising at least a second III-V semiconductor compound above a second portion of the channel layer; and a first metal contact structure above the S/D regions comprising a first metallic contact layer contacting the S/D regions. The first metallic contact layer comprises at least one metal-III-V semiconductor compound.

Abstract: A semiconductor structure includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A source feature and a drain feature are disposed on the second III-V compound layer. A gate electrode is disposed over the second III-V compound layer between the source feature and the drain feature. A fluorine region is embedded in the second III-V compound layer under the gate electrode. A gate dielectric layer is disposed over the second III-V compound layer. The gate dielectric layer has a fluorine segment on the fluorine region and under at least a portion of the gate electrode.

Abstract: A method includes oxidizing a semiconductor fin to form an oxide layer on opposite sidewalls of the semiconductor fin. The semiconductor fin is over a top surface of an isolation region. After the oxidizing, a tilt implantation is performed to implant an impurity into the semiconductor fin. The oxide layer is removed after the tilt implantation.

Abstract: A trench isolation structure and method of forming the trench isolation structure are disclosed. The method includes forming a shallow trench isolation (STI) structure having an overhang and forming a gate stack. The method further includes forming source and drain recesses adjacent to the STI structure and the gate stack. The source and drain recesses are separated from the STI structure by substrate material. The method further includes forming epitaxial source and drain regions associated with the gate stack by filling the source and drain recesses with stressor material.

Abstract: The gate electrode of a metal oxide semiconductor field effect transistor (MOSFET) comprises a source side gate electrode and a drain side gate electrode that abut each other near the middle of the channel. In one embodiment, the source side gate electrode comprises a silicon oxide based gate dielectric and the drain side gate electrode comprises a high-k gate dielectric. The source side gate electrode provides high carrier mobility, while the drain side gate electrode provides good short channel effect and reduced gate leakage. In another embodiment, the source gate electrode and drain gate electrode comprises different high-k gate dielectric stacks and different gate conductor materials, wherein the source side gate electrode has a first work function a quarter band gap away from a band gap edge and the drain side gate electrode has a second work function near the band gap edge.

Abstract: A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a substrate including a first dielectric layer disposed over the substrate. The semiconductor device further includes a buffer layer disposed over the substrate and between first and second walls of a trench of the dielectric layer. The semiconductor device further includes an insulator layer disposed over the buffer layer and between the first and second wall of the trench of the dielectric layer. The semiconductor device also includes a second dielectric layer disposed over the first dielectric layer and the insulator layer. Further, the semiconductor device includes a fin structure disposed over the insulator layer and between first and second walls of a trench of the second dielectric layer.

Abstract: A method of manufacturing multiple finFET devices having different thickness gate oxides. The method may include depositing a first dielectric layer on top of the semiconductor substrate, on top of a first fin, and on top of a second fin; forming a first dummy gate stack; forming a second dummy gate stack; removing the first and second dummy gates selective to the first and second gate oxides; masking a portion of the semiconductor structure comprising the second fin, and removing the first gate oxide from atop the first fin; and depositing a second dielectric layer within the first opening, and within the second opening, the second dielectric layer being located on top of the first fin and adjacent to the exposed sidewalls of the first pair of dielectric spacers, and on top of the second gate oxide and adjacent to the exposed sidewalls of the second pair of dielectric spacers.

Abstract: A carbon-based semiconductor device includes a substrate, source/drain contacts, a graphene channel, a dielectric layer, and a gate. The source/drain contacts are formed on the substrate. The graphene channel is formed on the substrate connecting the source contact and the drain contact. The dielectric layer is formed on the graphene channel with a molecular beam deposition process. The gate contact is formed over the graphene channel and on the dielectric. The gate contact is in a non-overlapping position with the source and drain contacts leaving exposed sections of the graphene channel between the gate contact and the source and drain contacts.

Abstract: A semiconductor structure is provided. The structure includes a semiconductor substrate of a semiconductor material and a gate dielectric having a high dielectric constant dielectric layer with a dielectric constant greater than silicon. The gate dielectric is located on the semiconductor substrate. A gate electrode abuts the gate dielectric. The gate electrodes includes a lower metal layer abutting the gate dielectric, a scavenging metal layer abutting the lower metal layer, an upper metal layer abutting the scavenging metal layer, and a silicon layer abutting the upper metal layer. The scavenging metal layer reduces an oxidized layer at an interface between the upper metal layer and the silicon layer responsive to annealing.

Abstract: A fin is formed over a first barrier layer over a substrate. The first barrier layer has a band gap greater than the band gap of the fin. In one embodiment, a gate dielectric layer is deposited on the top surface and opposing sidewalls of the fin and is adjacent to a second barrier layer deposited on the first barrier layer underneath the fin. In one embodiment, the gate dielectric layer is deposited on the top surface and the opposing sidewalls of the fin and an isolating layer is formed adjacent to the first barrier layer underneath the fin. In one embodiment, the gate dielectric layer is deposited on the top surface and the opposing sidewalls of the fin, and an isolating layer is formed adjacent to the second barrier layer deposited between the fin and the first barrier layer.

Abstract: Techniques are disclosed for forming transistor devices having reduced parasitic contact resistance relative to conventional devices. The techniques can be implemented, for example, using a standard contact stack such as a series of metals on, for example, silicon or silicon germanium (SiGe) source/drain regions. In accordance with one example such embodiment, an intermediate boron-doped germanium-tin alloy layer is provided between the source/drain and contact metals to significantly reduce contact resistance. Numerous transistor configurations and suitable fabrication processes will be apparent in light of this disclosure, including both planar and non-planar transistor structures (e.g., FinFETs and nanowire transistors). The techniques are particularly well-suited for implementing p-type devices, but can be used for n-type devices if so desired.

Abstract: A semiconductor device includes a cell region and a contact region, the cell region including a functional unit including a gate electrode, a source and a drain electrode, and the contact region including a gate pad. The gate electrode, the gate pad and the source electrode are disposed on a first main surface of a semiconductor substrate, and the drain electrode is disposed on a second main surface of the semiconductor substrate, the second main surface being opposite to the first main surface. A shielding member is disposed between the gate pad and the drain electrode, the shielding member being electrically connected to the source electrode.