Abstract: An analog-to-analog converter uses programmable conversion arrays containing non-volatile memory cells to provide references that depend on the threshold voltages of the memory cells, with the type of conversion dependent on the threshold voltages of the cells. An analog input signal is applied to an analog-to-digital conversion array for conversion to a digital signal. The digital signal is applied to a digital-to-analog conversion array for conversion to an analog output signal. A memory cell in the digital-to-analog conversion array is selected corresponding to the digital signal and reads the memory cell to generate the analog output signal, which is equal to or has a one-to-one correspondence with the threshold voltage of the memory cell. The conversion arrays can be programmed with suitable threshold voltages to implement desired conversions, such as logarithmic conversion for voice applications or random conversions for signal encryption.

Abstract: Disclosed is an integrated circuit comprising a substrate having a plurality of digital signal processors, including at least one analog circuit block, and means on said substrate for programmably interconnecting said processors and said at least one analog circuit block together. Also disclosed is a programming system comprising means for converting a programmable analog array specification into one or more programs executable by one or more digital signal processors so as to perform the identical or substantially identical function or functions as the programmed analog array.

Abstract: A method and circuit, for use with a parallel data bus of defined width, which provide a parallel data transmission and reception rate which is greater than the defined width of the parallel data bus. With respect to improving transmission, provided is a width-reduction circuit element, having at least two inputs through which are received a first set of parallel digital data signals and having one or more outputs through which are transmitted a second set of parallel digital data signals where the second set is both smaller than the first set and representative of the information contained within the first set. The one or more outputs interface with a parallel connector which is sufficient to form an operable connection with the parallel data bus of defined width.

Abstract: An improved squelch circuit and methodology for a multi-level quantizer employing one or more amplifiers to amplify an input signal at different gains. Comparators coupled to corresponding amplifiers or amplifier stages produce pulses based on comparing the amplified signals with a common reference potential. Digital delay lines coupled to the comparators repeatedly delay the pulses.

Abstract: An apparatus for wide bandwidth analog to digital and digital to analog signal conversion is disclosed. An input/output stage (40) is coupled to an external analog system and includes reference voltages for calibration of the analog to digital (A/D) conversion process. A conversion stage (46), comprising a plurality of A/D converters (ADC) (48, 50) and a digital to analog converter (52), is coupled to the input/output stage and to a digital signal conditioning stage (54) which is coupled to an external digital system. Offset and gain errors in the outputs of each ADC are corrected by the application of appropriate correction parameters in the digital signal conditioning stage. The sampling intervals for each ADC are phased to allow the digital outputs of the ADCs to be interleaved and form a resulting digital data stream with a sampling rate a multiple of that of any one ADC.

Abstract: According to the present disclosure, aperiodic data is applied to parallel register (500). When a predetermined relationship between an aperiodic load signal and a periodic oversample clock signal occurs, the aperiodic data is latched to the output (506) of the parallel register as substantially periodic data. The substantially periodic data is loaded into a sigma-delta DAC (502) for processing. The sigma-delta DAC (502) is driven by a periodic oversample clock to produce a 1-bit oversampled, time averaged representation of the substantially periodic data.

Abstract: An IR keyboard 1 generates key code information corresponding to key operated to add break flag information indicating distinction between in-operation and operation release to the key code information as operation status information of the key to add terminator code information indicating that the key code information corresponding to key operation every once is completed to the last portion of the key code information to transmit, as key operation information, the key code information, the break flag information and the key code information by an infrared ray signal from a light emitting unit 11. Further, a light receiving unit 2 receives the infrared ray signal transmitted from the light emitting unit 11 to input key operation information of the IR keyboard 1 to a computer unit 3.

Abstract: A method for providing audio sample rate conversion within a data-processing system is disclosed. An audio data stream is first received. If the input sample rate of the audio data stream is not equal to a target sample rate, several frequency multiplications or frequency divisions are selectively performed until the target sample rate is reached. Then, the audio data stream is passed through a lowpass filter having a cutoff frequency that is less than half of the target sample rate. Finally, the audio data stream is output.

Abstract: A power control circuit and corresponding technique for controlling the reduction or augmentation of operating frequency and/or supply voltage utilized by an electronic device. Such control is based on the operating environment of the hardware product employing the electronic device by determining whether the hardware product is interconnected to an external source having at least one enhanced cooling mechanism. As a result, the hardware product is able to operate at full frequency and voltage during certain situations and to operate at a reduced frequency and/or voltage during other situations.

Abstract: A wide-band sigma-delta modulator is disclosed having a cascade of two moators or stages, the first stage being of third or greater order and the second being of second or greater order. Both stages utilize simple ternary quantizers to avoid linearity problems associated with the digital to analog converters in the feedback paths of the modulators and to maintain stable operation. Additional zeros are placed in the noise transfer functions of third or higher order stages by means of additional feedback loops between the output of the third integrator and the second summing junction to maximize the dynamic range. The new topology significantly enhances the dynamic range of the system while hardly affecting the circuit's sensitivity with regard to some non-idealities such as finite amplifier open-loop gains or capacitor ratio mismatches.

Abstract: Data representing an information signal are non-linearly quantized to generate respective quantized data that represent the information signal using fewer bits. Each of the data, when non-linearly quantized, is represented by a quantizing level selected from a number of quantizing levels. The data are non-linearly quantized according to a non-linear function, the decision levels being off-center between adjacent quantizing levels obtained thereby from the quantizing values. The data and word-length information indicating the number of quantizing levels are received. A quantizing value for each quantizing level in the number of quantizing levels is determined from the word-length information and the non-linear function. The quantizing values determined for all the quantizing levels in the number of quantizing levels are non-uniformly spaced. Finally, the quantizing level having the quantizing value closest in value to the data value of each of the data is selected as a respective one of the quantized data.

Abstract: A system and method for communicating information from a high speed digital device, such as a processor, to a high speed peripheral device over a bus which has a frequency capability materially lower than the clock rates of the respective sending and receiving devices. Multiple successive digital signals are latched, converted to analog format current source signals, transmitted over the bus in analog format, decoded into respective digital format signals at the receiving end of the bus, and sequentially provided to the peripheral device in the original order. Analog to digital and digital to analog conversion accuracy is maintained through the use of a linking current reference which defines at each end of the bus a reference signal suitable for mirrored replication. The current mirrors allow accurate integrated circuit device dimension controlled current generation and corresponding current level decoding.

Abstract: Gain correction for a digital filter is accomplished by multiplying each data value by a coefficient representing the impulse response of the filter to form a convolution of the data values; accumulating the sum of the product of each multiplication to obtain a complete convolution; determining the difference between the positive full scale output and the negative full scale output of the filter; combining this difference with the ideal full scale output value to obtain the gain error factor; dividing the gain error factor by the full scale ideal value to obtain the gain correction factor; multiplying the negated accumulated sum of the product of each multiplication by the gain correction factor to obtain the gain error adjustment factor and combining the gain error adjustment factor with the accumulated sum to compensate for gain errors in the filter output.

Abstract: An analog-to-digital converter has a conversion section that converts an external analog signal to an internal digital signal, a digital input port that receives an external digital signal, and a result register. A selector controlled by a selection signal selects either the internal digital signal or the external digital signal for storage in the result register. The external digital signal can be written into the result register for test purposes, or to use the result register for general-purpose data storage.

Abstract: A signal convertor comprising a pulse modulator, and a modifier for modifying the signal input thereto in dependence upon the error in previous values of the output thereof, to reduce the effects of said error within a desired signal band.

Abstract: A high speed analog to digital sampling system. The invention allows for decimation and optimal storage of samples from an interleaved analog to digital conversion system. The circuit architecture provides for switchable flip-flops at the outputs of a set of interleaved analog to digital converters. Decimation is accomplished by only activating a selection of the analog to digital converters within the set of interleaved analog to digital converters. The flip-flops associated with the inactive analog to digital converters are configured to form a shift register. The samples of the activated analog to digital converters are shifted into the shift register. When all the flip-flops of the shift register are full, the samples are written to memory of the system. The shift register configuration allows the samples to be stored so that the allocation of system memory is optimized and the number of system memory writes is reduced.

Abstract: A speech encoder converts analog speech signals into a stream of binary coded speech samples. A circuit for performing analog to digital conversion compares an input speech signal with a signal from a digital integrator. Based on the comparison a series of decisions are registered which indicate a step sign of the input signal. A syllabic filter generates a step magnitude according to the registered decisions. The step sign and step magnitude are combined providing a sign/magnitude representation of the input signal. When the sign/magnitude representation is integrated digitally in a decimation filter a digital representation of the analog signal is formed. A speech decoder, the antithesis of the encoder, converts binary coded speech samples into an analog waveform in a manner opposite to the A/D conversion method.

Abstract: Serial analog-to-digital converters (ADC) in which power down and power up modes are activated by two dual-purpose input signals are provided. The ADCs of the invention eliminate the need for a dedicated power down input line as found on typical serial ADCs. When commanded to do so, the ADC enters into one of two power down modes, NAP or SLEEP. In NAP mode, only those portions of the ADC circuit which consume current and which are capable of waking up almost instantaneously are powered down. In SLEEP mode, the entire ADC circuit is powered down. When commanded to do so, the ADC enters into a power up mode, applying current to every portion of the ADC circuit. Wake-up from the NAP mode takes place almost instantaneously. Wake-up from the SLEEP mode requires additional time. From either mode, a signal is generated when the ADC conversion circuit, which preferably includes a reference voltage generator, has stabilized sufficiently for the ADC to perform analog-to-digital conversion.

Abstract: In a ramp signal producing apparatus, a ramp signal is produced under low clock signal frequency in a compact circuit arrangement. Luminance control and a white balance control are carried out by the ramp signal in a liquid crystal display. The ramp signal producing apparatus is comprised of: an up/down counter for either counting up, or counting down a clock signal supplied thereto; amplitude amount converting means for converting the amplitude of the supplied clock signal into such an amplitude value corresponding to the count value of the up/down counter and for converting the amplitude value in such a manner that a change amount per one count value is increased during the count down operation by the up/down counter; and ramp signal producing means for producing such a ramp signal with an amplitude corresponding to the converted amplitude value.

Abstract: A waveform measuring apparatus having a dummy readout circuit which applies first read signals of a same period as sampling signals to a read clock terminal of a FIFO memory during an interval between a first moment that a trigger enable signal is outputted from a prepoint counter when digital samples have been stored in the FIFO memory up to a predetermined number (a prepoint value) and a second moment that a trigger signal is generated by a trigger signal generating circuit. Concurrent reading from and writing to the FIFO memory is thereby permitted with a difference between the write pointer value and the read pointer value kept equal to the prepoint value. When a trigger signal is generated, digital data are written into the FIFO memory until the write pointer value catches up with the read pointer value and digital data are read from the FIFO memory by second read signals applied to it by a control unit. A display unit displays the waveform of the measured signal.

Abstract: An improved method and apparatus for transmission of dual 4-wire analog data services between a telephone company location and a subscriber premises over a single twisted pair, providing a 4:1 pair gain. In a preferred embodiment the invention provides for method and apparatus for transmission of multiple analog data signals for dual 4-wire analog data services over a single twisted pair from telephone company equipment to a subscriber, using 2B1Q or 4B3T digital signals.

Abstract: An application programming interface for a digital disk recorder uses a port to link resources together to form a multimedia recorder that emulates a tape recorder while retaining the flexibility of the digital disk recorder. The port is a matrix of timelines for each resource, with each track in the port representing a media stream associated with a different one of the resources. A dynamic subsystem controls recording and playing back multimedia between the resources and a disk file system of the digital disk recorder using the port. A static subsystem maintains on the disk file system a database of movies recorded by the digital disk recorder from the resources according to the port, with each movie being a collection of media files for each resource that are independently accessible.

Abstract: In a quantization noise reduction circuit (200), a feedback signal (W)is added to an input signal (X) to the quantization circuit to reduce quantization noise. The feedback signal is generated as a filtered difference between a sample of a N bit signal (X') and a time coincident sample of a M bit quantized signal, where M<N. The feedback signal is subtracted from the input signal (X) prior to quantization thereby introducing out of band noise into the input signal for reducing in band noise in the quantized signal (Y).

Abstract: A hybrid filter bank analog-to-digital converter includes continuous-time analysis filters and discrete-time synthesis filters. The continuous-time analysis filters partition a continuous-time wideband input signal into continuous-time subband signals. An analog-to-digital converter bank quantizes the subband signals at a low data rate. A bank of upsamplers increases the data rate of the quantized subband signals. A bank of discrete-time synthesis filters processes the upsampled subband signals, generating signals which are the discrete-time approximation of the continuous-time subband signals. The subband signals may be recombined into a discrete-time wideband signal which is the discrete-time approximation of the continuous-time wideband input signal. The linearity errors, analog-to-digital converter mismatches and quantization noise are not compounded between the frequency bands, thereby increasing resolution.

Abstract: A switched-capacitor DAC system includes an integrator circuit including an op amp having an input lead, an output lead and an integrator capacitor connected between the input lead and the output lead. A sampling switch is operable to connect an input capacitor to be charged by an input voltage during at least one of first and second non-overlapping time intervals, wherein the first time interval is subdivided into first and second non-overlapping sub-intervals and the second time interval is subdivided into third and fourth non-overlapping sub-intervals. A transferring switch is operable to connect the input capacitor to transfer charge from the input capacitor to transfer charge from the input capacitor to the integrator capacitor during at least one of the first and third sub-intervals. A discharging switch is operable to connect the input capacitor to a discharge node during at least one of the second and fourth sub-intervals.

Abstract: In accordance with an embodiment of the invention, a data converter is disclosed employing at least one minimum phase FIR filter. The data converter includes an analog-to-digital converter for converting an incoming analog signal into a plurality of digital signal samples, followed by a minimum phase FIR filter to filter the digital signal samples. Alternatively, the data converter includes a digital-to-analog converter preceded by a minimum phase FIR filter to filter a plurality of digital signal samples that are converted into an analog signal by the digital-to-analog converter. The data converter may include both analog-to-digital and digital-to-analog conversion. In a preferred embodiment, the minimum phase FIR filter is an optimum minimum phase FIR filter. A method for precisely calculating the filter coefficients of an optimum minimum phase FIR filter is also disclosed.

Abstract: A signal convertor comprising a pulse modulator, and a modifier for modifying the signal input thereto in dependence upon the error in previous values of the output thereof, to reduce the effects of said error within a desired signal band.

Abstract: A method and apparatus for transmitting and receiving multiple telephone transmission signals over a single twisted pair. An analog signal from a local switching station is converted to an 80 kbits/sec signal for transmission over a twisted pair. A remote terminal converts the 80 kbits/sec signal back into a conventional analog signal for use in conventional telephone, facsimile or other related equipment.

Abstract: A method and apparatus for transmitting and receiving multiple telephone transmission signals over a single twisted pair. An analog signal from a local switching station is converted to an 80 kbits/sec signal for transmission over a twisted pair. A remote terminal converts the 80 kbits/sec signal back into a conventional analog signal for use in conventional telephone, facsimile or other related equipment.

Abstract: A mixed analog and digital integrated circuit with features which are especially useful for application as a front end for physiological signal instrumentation such as electrocardiographs, electromyographs, and electroencephalographs. The integrated circuit has 5 signal channels, each with analog amplification and analog to digital conversion. The channels can be configured for various combinations of input signal amplification, input signal summation, analog output driving, and AC impedance measurement. The integrated circuit has 2 digital serial input lines and 2 digital serial output lines, all designed for direct connection to optical couplers. Channel configuration, gain, and other parameters are externally controllable by a serial digital input signal. Up to 6 compatible devices can be serially connected in a chain.

Abstract: A circuit apparatus comprises interface circuitry between analog and digital circuitry. A multiple reference circuit provides a variety of reference voltage signals. The multiple reference circuitry is coupled to a selection circuit that selectively couples one of the reference voltage signals to a first reference input of the interface circuitry and selectively couples another of the reference voltage signals to a second reference input of the interface circuitry, whereby the first and second reference inputs may be selectively coupled to the reference voltages and the circuit maintains a ratiometric relationship between the digital and analog circuitry.

Abstract: An information processing system includes a digital computing system, an analog processing device with an arrangement for converting electrical information to information of analog form, and an arrangement responsive to the analog information energy for producing output electrical information. Output data from the digital computing system is applied to the analog processing system via a D/A converter, and an A/D converter applies the output electrical information to the digital computing system. Data modified by the analog processing system may be employed to supplement data applied thereto in a random manner, or in a manner with a known transfer function, in order to introduce perturbations in the data to aid in subsequent processing thereof in the digital computing system.

Abstract: A converter system is comprised of an analog-to-digital converter (1) and a digital-to-analog converter (2). A first base number of a number system used in the analog-to-digital converter is less than 2, and a second base number of a number system used in the digital-to-analog converter is less than two. The first base number does not equal the second base number. For example, both are within a range from 1.90 to 1.99. In a calibration method the output of the digital-to-analog converter is switched to the input of the analog-to-digital converter, and a controller (3) provides digital values to the input of the digital-to-analog converter, and receives corresponding digital values from the output of the analog-to-digital converter.

Abstract: A signal processing apparatus includes an electronic processor responsive to a context signal and operable in alternative processing contexts identified by the context signal. First and second registers are connected to the electronic processor to participate in one processing context while retaining information from another processing context until a return thereto. A context switching circuit is connected to the first and second registers and operates to selectively control input and output operations of the registers to and from the electronic processor depending on the processing context. Other devices, systems and methods are also disclosed.

Abstract: A microprocessor (8) controlled power-saving electronic measuring system is disclosed. A load cell (1) generates an output signal indicative of the magnitude of the load applied to the cell (1). A DC power supply (2) is switched to supply the load cell (1) with power pulses (10) at varying frequencies and duty cycles determinable by the microprocessor (8) to optimize battery life. The microprocessor (8) determines the optimal duty cycle and frequency for the power pulses responsive to desired parameters. The circuitry of the present invention is located in close proximity to a temperature sensor (34) which accurately reads the temperatures of all of the components and compensates for all heat related inaccuracies simultaneously. The microprocessor (8) determines a temperature corrected value for the load cell (1) output via a previously programmed table containing the temperature response characteristics for the load cell (1) and the circuitry.

Abstract: An analog-to-digital converter for a camera has a reference signal generating element, a measurement signal generating element, and pulse output means for generating pulses of pule durations corresponding respectively to signals from the generating elements. The generating elements are alternately selected to produce two pulse durations, and the ratio of these two durations is computed by pulse duration ratio computing means. Control information corresponding to the computed ratio is retrieved from memory means.

Abstract: A single-chip microcomputer is comprised of an analog to digital converter, a first external terminal which receives an analog signal which is to be converted by the analog to digital converter, and a second external terminal for receiving a signal indicating an operating condition of the analog to digital converter.

Abstract: A method for operating an apparatus for facilitating communications between an analog device and a digital device, which apparatus includes a plurality of signal processing circuits and a control circuit for controlling the signal processing circuits. Each of the signal processing circuits includes signal attenuators and signal burst discrimination circuitry. The apparatus is operable in a plurality of stable states, preferably in an idle stable state, a transmit stable state, and a receive stable state. The apparatus also is operable in a plurality of transitional states, including up-transition states and down-transition states.

Abstract: The invention relates to a phase-locked loop comprising a phase detector (PD), an analog-to-digital converter (ADC), a loop filter (LF), a digital-to-analog converter (DAC) and a voltage-controlled oscillator (VCO). The phase jitter that occurs in such a hybrid phase-locked loop is reduced without enhancing the requirements as to the resolution of the digital-to-analog converter (DAC), in that a fractionizer (FR) is inserted after the loop filter (LF) that is operating at a first clock (TL), which fractionizer produces a main value (HW) and a residual value (RW), and the sum (SW) of the main value (HW) and a correction bit (KB) derived from the residual value (RW) is applied to the digital-to-analog converter (DAC) that is operating at a second clock (TA).

Abstract: An apparatus adaptable for use with an analog-digital conversion device for effecting communications between an analog device and a digital device, the analog-digital conversion device converting incoming analog signals received from the analog device to incoming digital signals. The apparatus has a digital signal processing circuit for decimating the incoming digital signals and providing a decimated incoming digital signal to the digital device.The digital signal processing circuit is comprised of a plurality of modules which are configured so that a specified set of the plurality of modules effects a specified number of iterations of decimation. The modules are further designed so that additional modules may be added to the specified set of modules to increase the iterations of decimation.

Abstract: An image signal binarization system for documents containing a mixture of two level and multiple level tone areas, such as characters and photographs, would provide an improved output if the system could distinguish between the two areas and respond accordingly. The proposed system distinguishes between the two types of areas by examining the density of a target point in relation to the average density of the surrounding points. If the density of the target point falls within a predetermined range the area is determined to be a multi-tone section otherwise the area is determined to be a two-tone section. The binarization system upon determining a given section to be a two tone section forces the output to one or zero. For a multi-tone section the output is based upon the mean density.

Abstract: A digital to analog signal converter apparatus for converting digital signals to analog signal outputs. The converter apparatus includes a microprocessor, a low pass filter portion for converting a digital output signal from the microprocessor to an analog output signal, and an analog to digital converter portion for sampling and converting the analog output signal to provide a digital input to the microprocessor, permitting control of the analog output signal.

Abstract: Digital circuit for shunting a ground separation plane, formed, for example, by a transformer, and present in a digital signal path. In this circuit a long sequence of equal bits offered to one side of such a ground separation plane must be conveyed further at the other side as a replica of said first bit sequence. Such sequences in essence represents a direct current. According to the invention, there is provided at the ingoing end of such a ground separation plane a modulator for up-modulating a bit stream applied thereto on a carrier frequency for which the ground separation plane is transparent. At the discharge end of the ground separation plane a demodulator is provided for down-modulation in such manner that a replica is obtained of the bit stream applied to the digital modulator. For such a modulator and such a demodulator use can be made of an XOR-gate or a D-flip-flop, respectively.A preferred use of the invention relates to a video circuit with A/D and D/A conversion, respectively.

Abstract: A means for correction for DC offset in an analog-to-digital converter which utilizes a hardware implemented iterative digital integration process. During the off time of an analog-to-digital converter thermal noise is digitized by the analog-to-digital converter and a specific number of least significant bits which are sufficient to handle the thermal noise levels are accumulated for a given number of samples. The accumulated sum of thermal noise samples is then converted into an analog signal and scaled by the number of samples taken so as to effectively find the average value from the sample collected. This scaled analog signal is then added to the thermal noise input signal wherein the process is repeated a predetermined number of times. Upon completion of the last iteration, the scaled analog signal which is representative of the DC offset inherent in the particular analog-to-digital converter is added to the true analog signal to be digitized.

Abstract: A dual channel A/D and D/A converter includes a first channel converter, a second channel converter, and a reference generator all formed on a single semiconductor substrate. The reference generator is disposed intermediate the first channel converter and the second channel converter for effecting crosstalk isolation therebetween. The dual channel converter is formed of a unique differential structure having "coaxial" isolation of bus lines and interconnections, thereby achieving a higher degree of unwanted channel-to-channel crosstalk.

Abstract: In a pulse-density D/A or A/D converter, improved averaging of a pulse-density-modulated (PDM) signal in the presence of a jittering clock signal is achieved by applying the PDM signal to the serial input of an n-stage shift register whose parallel output serves to control n state signals. The shift register is driven by the clock signal. The n state signals are combined into a sum signal which feeds a low-pass filter. In preferred embodiments, the n state signals are weighted and/or isolated from the respective previous state and the following state by means of gate circuits.

Abstract: A dither circuit including an adder for receiving an input signal and a dither signal which is generated by a dither signal generator, a level detection circuit for detecting the signal level of the input signal, and a dither control circuit for stopping the feeding of the dither signal to the adder when the level detection circuit detects that the signal level of the input signal is zero.

Abstract: A digital to analog data demodulating circuit adapted for selectively demodulating analog data from a plurality of digital data each having a different sampling frequency. The circuit includes an input terminal provided for selectively receiving the plurality of digital data, a digital filter coupled to the input means for shifting higher the sampling frequency of the digital data applied from the input terminal, a D/A converter coupled to the digital filter for generating first and second analog conversion data separated into a lower frequency band and a higher frequency band, the lower frequency band being alsmost conicident with the frequency band of the analog data digitized to the corresponding digital data and the higher frequency band having a center frequency coincident with the shifted sampling frequency and an LPF coupled to the D/A converter for removing the second analog conversion data from the output of the D/A converter.

Abstract: A digital-to-analog converter for converting a digital signal having a word length n into an analog signal. The converter includes at least two switched capacitor integrators (1, 2) arranged in series and a control unit (18) for applying control signals to the integrators which perform an integration step under the influence of the control signal. Each integrator is provided with a capacitor network (11, 12) having at least two capacitors (27.1, 27.2, . . . ; 28.1, 28.2, . . . ) coupled between the input (13; 4) of the integrator and the inverting input (-) of an associated amplifier stage (5; 6). A capacitor (9; 10) is coupled between the inverting input (-) and the output (7; 8) of this amplifier stage. The control unit is adapted to apply, in this order, a first control signal to the first integrator (1), a second control signal to the second integrator (2), a third control signal to the first integrator and a fourth control signal to the second integrator.

Abstract: A data limiter in a paging receiver for converting an analog signal to a digital signal, the data limiter having a variable time constant. The data limiter includes an amplifying circuit and an integrating circuit. The amplifying circuit, being responsive to the analog input signal generated from a receiving circuit of the paging receiver, generates a reference signal depending upon a variable bias current input to the amplifying circuit. The integrating circuit, being responsive to the reference signal, generates a comparison signal depending upon a variable gain input. The amplifying circuit responsive to the comparison signal compares the comparison signal to the input signal for generating a digital output signal. A processing circuit of the paging receiver generates a first control signal for modifying the variable bias current input and a second output signal for modifying the variable gain input.