Abstract: A data center for data backup and replication, including a pool of multiple storage units for storing a journal of I/O write commands issued at respective times, wherein the journal spans a history window of a pre-specified time length, and a journal manager for dynamically allocating more storage units for storing the journal as the journal size increases, and for dynamically releasing storage units as the journal size decreases.

Abstract: A storage system 100, which has a plurality of flash packages 230, has a function for minimizing the imbalance of the number of deletions of each block inside the flash package 230 and a block-unit capacity virtualization function, and efficiently manifests lessening of the imbalance of the number of deletions and reduction in the data storage capacity for the entire storage system 100 by having functions for calculating the number of deletions and the data occupancy of each flash package 230, and for transferring data between the flash packages 230 on the basis of the values of these number of deletions and data occupancy.

Abstract: A system and method for offset protection data in a RAID array. A computer system comprises client computers and data storage arrays coupled to one another via a network. A data storage array utilizes solid-state drives and Flash memory cells for data storage. A storage controller within a data storage array is configured to store user data in a first page of a first storage device of the plurality of storage devices; generate intra-device protection data corresponding to the user data, and store the intra-device protection data at a first offset within the first page. The controller is further configured to generate inter-device protection data corresponding to the first page, and store the inter-device protection data at a second offset within a second page in a second storage device of the plurality of storage devices, wherein the first offset is different from the second offset.

Abstract: Provided is a hybrid RAID controller coupled to a system control board. Coupled to the hybrid RAID controller are a DDR RAID controller, a RAM RAID controller, and a HDD/Flash RAID controller. A DDR RAID control block is coupled to the DDR RAID controller and includes (among other things) a set of DDR memory disks. Further, a RAM control block is coupled to the RAM RAID controller and includes a set of RAM SSDs. Still yet, a HDD RAID control block is coupled to the HDD/Flash RAID controller and includes a set of HDD/Flash SSD Units.

Abstract: A method, apparatus, and electronic device with secure operation based on geography are disclosed. A positioning mechanism 404 may determine a geographic location of the apparatus or electronic device. A processor 104 may identify a secure domain for a virtual machine application. The processor 104 may determine an availability of an application programming interface for the virtual machine application based on the geographic location.

Abstract: A method is provided for performing memory operations in response to instructions to perform a double data rate (DDR) memory reference voltage training in the voltage domain by a processing device and determining a DDR memory reference voltage and a DDR memory delay time based upon the memory operation. Computer readable storage media are also provided. A circuit is provided that includes a communication interface portion coupled to a memory and to a processing device. The circuit also includes a circuit portion, coupled to the communication interface portion that has a hardware state machine or an algorithm. The state machine or algorithm provides instructions to the processing device to perform a double data rate (DDR) reference voltage training in the voltage domain.

Abstract: A data processing system having a processor and a target device processes decorated instructions (i.e. an instruction having a decoration value). A device of the data processing system such as the processor sends transactions to the target device over a system interconnect. A decorated storage notify (DSN) transaction includes an indication of an instruction operation, an address associated with the instruction operation, and a decoration value (i.e. a command to the target device to perform a function in addition to a store or a load). The transaction on the system interconnect includes an address phase and no data phase, thereby improving system bandwidth. In one form the target device (e.g. a memory with functionality in addition to storage functionality) performs a read-modify-write operation using information at a storage location of the target device.

Abstract: A data storage device includes a data storage medium; a micro control unit (MCU) connected to a host through a first interface method and configured to control the data storage medium in response to a request of the host; and a buffer memory connected to the host through a second interface method, connected to the MCU, and controlled by the MCU and the host, respectively.

Abstract: An example method includes providing at least two data storage areas in a memory, providing a first amount of over-provisioning for a first of the at least two data storage areas and a second amount of over-provisioning for a second of the at least two data storage areas, categorizing data based on a characteristic of the data, and storing the data in one of the at least two data storage areas based on the categorization.

Abstract: An apparatus includes a controller capable of being coupled to a magnetic data storage media and a cache. The cache includes non-volatile, solid-state memory. The controller is configured to detect a defect in the data storage media requiring a recovery operation and allocate a portion of the cache for storage of a journal to be used in the recovery operation. The controller is further configured to log steps of the recovery operation to the journal.

Abstract: A system, processor and method to reduce the overall detectable unrecoverable FIT rate of a cache by reducing the residency time of dirty lines in a cache. This is accomplished through selectively choosing different replacement policies during execution based on the DUE FIT target of the system. System performance and power is minimally affected while effectively reducing the DUE FIT rate.

Abstract: A cluster file system comprises storage server units each configured for communication with a plurality of clients over a network. At least one of the storage server units comprises an object storage server, an object storage target associated with the object storage server, a metadata server, a metadata target associated with the metadata server, and a scale-out network attached storage cluster. The scale-out network attached storage cluster comprises storage directories corresponding to respective ones of the object storage and metadata targets. The object storage server and its associated object storage target may form part of a first storage tier of the storage server unit, and a plurality of nodes of the scale-out network attached storage cluster may form part of a second storage tier of the storage server unit. Parallel log-structured file system (PLFS) middleware may be used to control movement of data between the first and second storage tiers.

Abstract: Embodiments of the invention are directed to optimizing the selection of memory blocks for garbage collection in solid state devices to efficiently maximize the amount of memory freed by garbage collection operations. The systems and methods disclosed herein provide for the efficient selection of optimal or near-optimal garbage collection candidate blocks, with the most optimal selection defined as block(s) with the most invalid pages. In one embodiment, a controller classifies memory blocks into various invalid block pools by the amount of invalid pages each block contains. In one embodiment, the controller selects for garbage collection a block from a non-empty pool of blocks with the highest minimum amount of invalid pages. One or more of the pools have minimum thresholds that can be dynamically adjusted according to an observed usage condition, such as a change of an over-provisioning amount in the storage state device.

Abstract: A method of mapping m individual objects to source symbols for delivering data from a transmitter to a receiver in a communication system, the m individual objects ordered from object 1 to object m, wherein m>1, includes: aggregating the m individual objects into an aggregate object, including for each individual object j, calculating a number of source symbols S(j) for containing data of the individual object j; and partitioning the aggregate object into Z source blocks, including for each source block k and each individual object j, calculating a number of source symbols NSS(j, k) of individual object j in source block k, wherein the S(j) source symbols for each individual object j are arranged consecutively within consecutive source blocks, starting from a first source block for which NSS(j, k)>0 to a last source block for which NSS(j, k)>0.

Abstract: An exemplary embodiment extended peripheral component interconnect express (PCIe) device includes a host PCIe fabric comprising a host root complex. The host PCIe fabric has a first set of bus numbers and a first memory mapped input/output (MMIO) space on a host CPU. An extended PCIe fabric includes a root complex endpoint (RCEP) as part of an endpoint of the host PCIe fabric. The extended PCIe fabric has a second set of bus numbers and a second MMIO space separate from the first set of bus numbers and the first MMIO space, respectively.

Abstract: A solid state storage device and sensing voltage setting method thereof are provided, and the method includes following steps. A predetermined read voltage of the memory cells is adjusted to obtain a plurality of detection read voltages. The predetermined read voltage and the detection read voltages are respectively applied to a plurality of memory cells in order to read a plurality of verification bit data. A plurality of statistical parametric values between the predetermined read voltage and the detection read voltages adjacent to each other is calculated and recorded according to the verification bit data corresponding to the predetermined read voltage and the detection read voltages. An optimized read voltage is obtained according to the statistical parametric values.

Abstract: In one embodiment, a particular field area router (FAR), in a local computer network (e.g., a mesh network) having a plurality of FARs, advertises a common subnet prefix assigned to the local computer network into a global computer network. Each of the plurality of FARs of the local computer network is configured to accept any traffic destined to the local computer network, and a tunnel overlay is built among the plurality of FARs. Upon receiving a packet at the particular FAR destined to a particular device in the local computer network, and in response to the particular FAR not having a host route to the particular device, it forwards the packet on the tunnel overlay to another of the plurality of FARs of the local computer network.

Abstract: A system and method for generating synthetic data to simulate backing up data between a primary storage system and a protection storage system is presented. In one embodiment, a first track in a set of tracks is selected at random. Having selected a first track, at least a first block in the first track is modified. Subsequently, it is determined, based on a track run probability, whether to modify a second track that is consecutive to the first track or a third track that is selected randomly. Depending on the determination, at least one block is modified at either the second or third track. Other embodiments are also described herein.

Abstract: A bus connection circuit connects a bus master and a plurality of bus slaves. The bus connection circuit includes a mirror area access detecting circuit and a processing circuit. The mirror area access detecting circuit detects that the bus master accesses a mirror area of a first bus slave of the plurality of bus slaves, and output a detection signal based on a detection result. The processing circuit executes processing preset in correspondence to the detection result, to an area or data as an access object, based on the detection result.

Abstract: A system, method, and computer-readable medium are disclosed for managing a system's entitlement to digital assets when the system's components are replaced. A unique system identifier, comprising the unique identifiers of predetermined system components, is associated with digital assets data to generate digital assets entitlement data, which in turn entitles the system to process the digital assets data. The digital assets entitlement is perpetuated when a first unique system component identifier is replaced with a second unique system component identifier.

Abstract: A microprocessor according to the present invention includes instruction execution unit that executes an instruction to output an access request to a memory according to a first protocol; memory control unit that converts the access request according to the first protocol to an access request according to a second protocol to perform an access control to an external memory to output the access request; selection unit that selects whether to access the external memory using the memory control unit; and interface unit that externally outputs one of the access request according to the first protocol and the access request according to the second protocol based on the selection result in the selection unit.

Abstract: Provided are a computer program product, system, and method for locking a cache line for a burst write operations on a bus. A cache line is allocated in a cache for a target address. A lock is set for the cache line, wherein setting the lock prevents the data in the cache line from being cast out. Data is written to the cache line. All the data in the cache line is flushed to the target address over a bus in response to completing writing to the cache line.

Abstract: Chunks of memory cells in a memory array are enabled to be accessed and then one or more of the chunks are disabled from being accessed. In one such apparatus, an array includes chunks of memory cells and a chunk selector circuit coupled to each chunk to enable the memory cells in the respective chunk to be accessed.

Abstract: Disclosed is a switching voltage regulator circuitry controlled to supply a voltage to at least a portion of an integrated circuit (IC). Information corresponding to a current load for a different power state of at least a portion of the IC is received. The switching voltage regulator circuitry is controlled to adjust the voltage to a different value based at least in part on the received information. Disclosed is a voltage received for a power state of at least a portion of an IC having first logic to perform one or more functions and second logic integrated with the first logic. Information corresponding to a current load for a different power state of at least a portion of the IC is sent from the second logic to voltage regulator control logic to adjust the voltage to a different value.

Abstract: A multi-core processor system includes a memory unit that for each input destination thread defined as a thread to which given data is input, stores identification information of an assignment destination core for the input destination thread; and a multi-core processor that is configured to update, in the memory unit and when assignment of the input destination thread to a multi-core processor is detected, the identification information of the assignment destination core for the input destination thread; detect a writing request for the given data; identify based on the given data for which the writing request is detected, the updated identification information among information stored in the memory unit; and store the given data to a memory of the assignment destination core that is indicated in the updated identification information and among cores making up the multi-core processor.

Abstract: Among other things, one or more techniques and/or systems are provided for storing data within a hybrid storage aggregate comprising a lower-latency storage tier and a higher-latency storage tier. In particular, frequently accessed data, randomly accessed data, and/or short lived data may be stored (e.g., read caching and/or write caching) within the lower-latency storage tier. Infrequently accessed data and/or sequentially accessed data may be stored within the higher-latency storage tier. Because the hybrid storage aggregate may comprise a single logical container derived from the higher-latency storage tier and the lower-latency storage tier, additional storage and/or file system functionality may be implemented across the storage tiers. For example, deduplication functionality, caching functionality, backup/restore functionality, and/or other functionality may be provided through a single file system (or other type of arrangement) and/or a cache map implemented within the hybrid storage aggregate.

Abstract: A method of transferring data in a flash storage device comprising a random access memory and a plurality of channels of a flash array is provided. The method comprises receiving a plurality of data segments from a host system, storing the plurality of data segments in the random access memory, allocating the plurality of data segments among the plurality of channels of the flash array, and writing the allocated data segments from the random access memory to the respective channels of the flash array.

Abstract: The present disclosure includes methods, devices, and systems for controlling a memory device. One method for controlling a memory device embodiment includes storing device class dependent information and a command in one or more of host system memory and host controller memory, setting a pointer to the command in a register in a host controller, directing access to the one or more of host system memory and host controller memory with the memory device via the host controller; and executing the command with the memory device.

Abstract: An apparatus and method for recognizing an external memory in a mobile terminal are provided. The apparatus includes an external memory manager for recognizing as if an external memory was attached without a separate external memory by defining a built-in memory as a virtual external memory after a booting process.

Abstract: A method for data storage, including configuring in a data storage system a volume storage pool as data storage resources available for allocation of volumes in the data storage system. The method also includes defining a threshold value for the volume storage pool. When the allocation of the volumes causes the threshold value to be crossed, the method includes performing an action for managing the volume storage pool.

Abstract: Embodiments provide access to a memory over a high speed serial link at slower speeds than the high speed serial links regular operation. An embodiment may comprise a memory apparatus with a differential receiver coupled to a protocol recognition circuit, a low speed receiving circuit that has a first receiver coupled with a first input of the differential receiver and a second receiver coupled with a second input of the differential receiver, wherein the low speed receiving circuit is coupled with the protocol recognition circuit, allowing the first and second receivers to access the protocol recognition block at a different frequency than the differential receiver.

Abstract: In one embodiment, a method includes receiving metadata corresponding to data on a removable storage device/medium, storing the metadata to a metadata repository that is not on the removable storage device/medium, associating an identifier with the stored metadata (the identifier corresponding to the removable storage medium/device), and storing the identifier to the metadata repository. According to another embodiment, a computer program product includes a computer readable storage medium having computer readable program code embodied therewith. The computer readable program code comprises computer readable program code configured to: receive metadata corresponding to data on a removable storage device/medium, store the metadata to a metadata repository, associate an identifier corresponding to the removable storage device/medium with the stored metadata, and store the identifier to the metadata repository. Other methods, systems, and devices are presented as well.

Abstract: A cloud system may create physical resource tags to store relationships between cloud computing offerings, such as computing service offerings, storage offerings, and network offerings, and the specific physical resources in the cloud computing environment. Cloud computing offerings may be presented to cloud customers, the offerings corresponding to various combinations of computing services, storage, networking, and other hardware or software resources. After a customer selects one or more cloud computing offerings, a cloud resource manager or other component within the cloud infrastructure may retrieve a set of tags and determine a set of physical hardware resources associated with the selected offerings. The physical hardware resources associated with the selected offerings may be subsequently used to provision and create the new virtual machine and its operating environment.

Abstract: Subject matter disclosed herein relates to validating memory content in persistent main memory of a processor.

Abstract: According to one embodiment, a semiconductor storage device includes a nonvolatile memory, memory controller storing control information, a switch between the nonvolatile memory/memory controller and a power supply terminal, a second memory, an interpreter interprets a command, a switch controller, and a third memory stores an address of the control information in the second memory. The memory controller instructs the switch controller to open the switch after writing the control information into the second memory and reads the control information from the second memory based on the address stored in the third memory when the memory controller is electrically connected to the first power supply terminal.

Abstract: Embodiments provide a solution for controlling file migration in archiving systems. A networked device can be configured to, during an archiving process, exclude or otherwise prevent files from migrating to tape or another archiving appliance connected to the networked device which, in one embodiment, implements an archive node appliance. The archive node appliance may be configured to start an archiving process to store a file. The archiving process may cause the file to be stored in a share or directory on the archive node appliance. The archive node appliance may check a file exclusion policy associated with the share or directory to determine whether the file is to be excluded from migration. The archive node appliance may stop the archiving process if it determines that the file exclusion policy contains a pattern that matches the file name. One example of such a pattern can be a user-defined glob.

Abstract: Memory management methods and systems for mobile devices are provided. A memory usage of a memory is monitored by a built-in memory management component of an OS of the device and a user-oriented memory management component. It is determined whether the memory usage of the memory is greater than a first threshold or a second threshold, wherein the second threshold is greater than the first threshold. When the memory usage of the memory is greater than the first threshold, a multi-level memory management is performed by the user-oriented memory management component. When the memory usage of the memory is greater than the second threshold, a primitive memory management is performed by the built-in memory management component.

Abstract: Methods and structure are provided for representing ports of a Serial Attached SCSI (SAS) expander circuit within routing memory. The SAS expander includes a plurality of PHYs and a routing memory. The routing memory includes entries that each indicate a set of PHYs available for initiating a connection with a SAS address, and also includes an entry that represents a SAS port with a start tag indicating a first PHY of the port and a length tag indicating a number of PHYs in the port. The SAS expander also includes a Content Addressable Memory (CAM) including entries that each associate a SAS address with an entry in the routing memory. Further, the SAS expander includes a controller that receives a request for a SAS address, uses the CAM to determine a corresponding routing memory entry for the requested SAS address, and selects the port indicated by the corresponding routing memory entry.

Abstract: Managing data returns to a host in response to read commands, an operation monitor of a solid-state drive (SSD) manages counters used to hold metrics that characterize the estimated time to complete a read operation on a corresponding flash die. A timer generates a periodic event which decrements the counters over time. The value stored in each counter is generated for flash operations submitted to the corresponding die and is, generally, based on the operational history and the physical location of the operation. Whenever a read command is scheduled for submission to a particular die, the time estimate for that particular read operation is retrieved and, based on this information, the optimum order in which to return data to the host is determined. This order is used to schedule and program data transfers to the host so that a minimum number of read commands get blocked by other read commands.

Abstract: Methods and structure are provided for representing ports of a Serial Attached SCSI (SAS) expander circuit within routing memory. The SAS expander includes a plurality of PHYs and a routing memory. The routing memory includes entries that each indicate a set of PHYs available for initiating a connection with a SAS address, and also includes an entry that represents a SAS port with a start tag indicating a first PHY of the port and a length tag indicating a number of PHYs in the port. The SAS expander also includes a Content Addressable Memory (CAM) including entries that each associate a SAS address with an entry in the routing memory. Further, the SAS expander includes a controller that receives a request for a SAS address, uses the CAM to determine a corresponding routing memory entry for the requested SAS address, and selects the port indicated by the corresponding routing memory entry.

Abstract: In accordance with at least one embodiment, memory power gating at word level is provided. In accordance with at least one embodiment, a word level power-gating technique, which is enabled by adding an extra control bit to each subarray (e.g., each word, each row, each wordline, each bitline, each portion of an array, etc.) of a memory array, provides fine-grained power reduction for a memory array. In accordance with at least one embodiment, a gating transistor is provided for each subarray (e.g., each word, each row, each wordline, each bitline, each portion of an array, etc.).

Abstract: Disclosed is an on-chip buffer program method for a data storage device which comprises a multi-bit memory device and a memory controller. The on-chip buffer program method includes measuring a performance of the data storage device, judging whether the measured performance satisfies a target performance of the data storage device, and selecting one of a plurality of scheduling manners as an on-chip buffer program scheduling manner of the data storage device according to the judgment result.

Abstract: Methods of operating a memory, and memories for performing such methods, include determining that a particular area of the memory is defective, locating a free area of the memory, programming data intended for the particular area of the memory to the free area of the memory, checking the particular area of the memory for data previously programmed to the particular area of the memory, and moving any previously-programmed data from the particular area of the memory to the free area of the memory.

Abstract: A method comprises creating a first node, determining whether an indicator associated with a head node is present, and designating the first node as a head node, defining and associating a head node identifier with the first node, define a link from the first node to the first node, and create and save an indicator associated with the head node responsive to determining that the indicator associated with a head node is not present.

Abstract: Embodiments of this disclosure relate to improving solid-state non-volatile memory management. Embodiments improve the management of solid-state non-volatile memory by providing a central manager responsible for receiving requests from media access requesters. In embodiments, the central manager updates requests with a physical address corresponding to a logical address for a request. In embodiments, the central manager is the only entity updating a mapping table and invalid page table for the system. In embodiments, the central manager may also throttle or prioritize requests originating from two or more requesters to change the ratio of requests executed from each requester.

Abstract: A method, a computer readable medium and a memory controller. The method for writing information to a K-level memory unit, includes: receiving a sequence of information bits; generating an information value that represents the sequence of information bits; applying a first function to the information value, to provide a first function result; selecting a first cell of the K-level memory unit as a current cell; wherein K is a positive integer that is greater than 1; writing the first function result to the first cell; and repeating the stages of: (a) reading a current cell to provide a current read result; (b) applying a second function to the current read result and to a function result that was written to the current cell, to provide a second function result; (c) selecting another cell as a current cell; and (d) writing the second function result to the current cell.

Abstract: In a three-dimensional NAND memory in which a block contains multiple separately-selectable sets of strings connected to the same set of bit lines, sets of strings are zoned, and different operating parameters applied to different zones. Operating parameters for a zone are obtained from characterizing a reference set of strings in the zone.

Abstract: A dual-mode computing system and machine-implemented method for providing an indication of an operating mode of the system. The system including a processor, a memory storing verified code, a secure memory coupled to a processor and a developer mode indicator coupled to the secure memory, wherein the processor is configured to execute verified code to perform operations comprising initiating boot up of the system. The operations further comprising accessing a developer mode state stored within the secure memory to determine whether the system is in developer mode, wherein the developer mode allows the system to execute unverified code, activating the developer mode indicator when it is determined that the system is in developer mode and locking the secure memory to ignore subsequent calls to modify the developer mode state when it is determined that the system is in developer mode.

Abstract: A method of controlling a storage device, the method including calculating, in a controller of the storage device, data throughput of the storage device in a current period, comparing, in the controller, the data throughput to a reference value and adjusting, with the controller, an operation performance of the storage device in a next period based on the comparison and a delay factor of a period prior the current period.

Abstract: A technique is provided for implementing online mirroring of a volume in a storage area network. A first instance of the volume is instantiated at a first port of the fiber channel fabric for enabling I/O operations to be performed at the volume. One or more mirroring procedures may be performed at the volume. In at least one implementation, the first port is able to perform first I/O operations at the volume concurrently while the mirroring procedures are being performed at the first volume. In one implementation, the mirroring procedures may be implemented at a fabric switch of the storage area network. Additionally, in at least one implementation, multiple hosts may be provided with concurrent access to the volume during the mirroring operations without serializing the access to the volume.