Abstract: A method for dynamically configuring multiple processors based on needs of applications includes receiving, from an application, an acceleration request message including a task to be accelerated. The method further includes determining a type of the task and searching a database of available accelerators to dynamically select a first accelerator based on the type of the task. The method further includes sending the acceleration request message to a first acceleration interface located at a configurable processing circuit. The first acceleration interface sends the acceleration request message to a first accelerator, and the first accelerator accelerates the task upon receipt of the acceleration request message.

Abstract: The present disclosure relates to a method and a system for generating a test suite comprising test cases. In one embodiment, the method generates the test cases based on functional requirements, service requirements and performance requirements received from a user such as a quality engineer associated with a software product or application. The method analyzes the interdependencies among the received requirements, generates sequences of the requirements based on the interdependencies and generates intermediate test cases based on the sequences. Further, the method deploys a test modeling tool on the intermediate test cases to generate final test cases which are then tested to evaluate the performance of the software product or the application. The test suite comprising the final test cases thus generated is rigid and provides a new dimension to the quality engineer to avoid the production failures and defect slippages and sustain the quality assurance (QA) of the business.

Abstract: A method for storage volumes in a cascade of storage volumes including starting a first data map relating a first storage volume to a second storage volume while a second data map relating the first storage volume and a third storage volume is active. Starting the first data map uses a zone map that relates the first storage volume to a zone within the cascade of storage volumes.

Abstract: A device includes a memory device and a controller. The controller is coupled to the memory device. The controller is configured to, in response to receiving a request to perform a memory access at the memory device, determine that the memory device has a characteristic indicative of a temperature crossing. The controller is also configured to, in response to determining that the memory device has the characteristic indicative of the temperature crossing, determine that the memory device satisfies an availability criterion. The controller is further configured to, in response to determining that the memory device satisfies the availability criterion, increase a temperature of the memory device by performing memory operations on the memory device until detecting a condition related to the temperature.

Abstract: Methods and systems are presented for allocating CPU cycles among processes in a storage system. One method includes operations for maintaining segments in a first memory, each segment including blocks, and for maintaining a block temperature for each block in a second memory. The first memory is a read-cache where one segment is written at a time, and each block is readable from the first memory without reading the corresponding complete segment. The block temperature is based on the frequency of access to the respective block, and a segment temperature is based on the block temperature of its blocks. Additionally, the segment with the lowest segment temperature is selected for eviction from the second memory, and blocks in the selected segment with a block temperature greater than a threshold temperature are identified. The selected segment is evicted, and a segment with the identified blocks is written to the first memory.

Abstract: A device includes a memory device and a controller. The controller is coupled to the memory device. The controller is configured to, in response to receiving a request to perform a memory access at the memory device, determine that the memory device has a characteristic indicative of a temperature crossing. The controller is also configured to, in response to the determination, increase a temperature of the memory device by performing memory operations on the memory device until detecting a condition related to the temperature.

Abstract: SSD wear-level data (320) is generated on managed nodes (202) having SSDs (206). The wear-level data is collected by a management node (204).

Abstract: A data storage device includes a non-volatile semiconductor storage device and a controller that is configured to perform interleaving of small reads with large reads and small writes with large writes. In the example of reads, the controller receives a sequence of read commands including a first read command having a read size larger than a read threshold size and a second read command having a read size smaller than the read threshold size, and issue first and second read requests in succession to read data of a predetermined size less than the read threshold size, from the non-volatile semiconductor storage device. The interleaving is achieved by issuing the first read request to execute the first read command and the second read request to execute the second read command. As a result of this interleaving, the second read command will have a chance to complete earlier than the first read command even though it was received by the controller later in time.

Abstract: A disassembler receives instructions and disassembles them into a plurality of separate opcodes. The disassembler creates a table identifying boundaries between each opcode. Each opcode is written to memory in an opcode-by-opcode manner by atomically writing standard blocks of memory. Debug break point opcodes are appended to opcode to create a full block of memory when needed. The block of memory may be thirty-two or sixty-four bits long, for example. Long opcodes may overlap two or more memory blocks. Debug break point opcodes may be appended to a second portion of the long opcode to create a full block of memory. A stream fault interceptor identifies when a requested data page is not available and retrieving the data page.

Abstract: A computer-implemented method for downloading and displaying pictures associated with instant messages is performed at a computing device. The computing device receives an instant message having an associated picture and including address information of the picture. The computing device determines whether it is in a first network environment. If so, the computing device displays a thumbnail of the picture on the screen and a visual cue indicating that the picture is being downloaded and starts downloading the picture associated with the instant message according to the address information without receiving a download instruction from a user of the computing device. The thumbnail is then replaced with the picture after the picture is downloaded. While the picture is being downloaded, the computing device may pause the download when it is no longer in the first network environment and replaces the visual cue with a different one indicating so.

Abstract: A storage system includes a first information processor, a second information processor, and a superordinate device. The first information processor includes a first memory device that stores therein the data, a difference generator that generates difference data representing a difference between updating data received from the superordinate device and the data stored in the first memory device before updating, a second memory device stores therein the generated difference data, and a data transmitter that transmits the stored difference data to the second information processor. The second information processor includes a third memory device that stores therein the parity, a data receiver that receives the difference data transmitted from the data transmitter, and a parity difference applier that generates a post-updating parity that is to be written into the third memory device by applying the received difference data to the stored parity before the updating.

Abstract: The present application is directed to a control circuit that provides a directory configured to maintain a plurality of entries, wherein each entry can indicate sharing of resources, such as cache lines, by a plurality of agents/hosts. Control circuit of the present invention can further provide consolidation of one or more entries having a first format to a single entry having a second format when resources corresponding to the one or more entries are shared by the agents. First format can include an address and a pointer representing one of the agents, and the second format can include a sharing vector indicative of more than one of the agents. In another aspect, the second format can utilize, incorporate, and/or represent multiple entries that may be indicative of one or more resources based on a position in the directory.

Abstract: Techniques for maintaining and updating authentication information for a plurality of accounts may be provided. In an example a first set of authentication information for the plurality of accounts may be maintained. A second set of authentication information that has been marked as potentially compromised may be received. A third set of authentication information may be generated based on the overlap between the first set of authentication information and the second set of authentication information. The first set of authentication information may be updated based at least in part on one or more security authentication protocols and the third set of authentication information.

Abstract: Transparent file processing is supported in Unix-like operating systems by emulating the desired file processing through a number of recipes that accommodate different contexts. Recipes are provided, for example, for local folders in user space, for whole devices (e.g., flash drives or network drives), and for folders synchronized to cloud data. By detecting the path type for a file operation and selecting and applying the appropriate recipe, file processing can be performed in a manner transparent to the user.

Abstract: A method of providing network management information about a multiple-layer network communications interface sub-stack to a network management client includes establishing a standardized network management representation by use of an interface manager and a real driver and a pseudo driver, receiving a request from the network management client for network management information about an expected sub-layer interface, and in response to the request obtaining, by the pseudo driver, data maintained by the real driver corresponding to the requested network management information, and returning the data obtained by the pseudo driver to the network management client in satisfaction of the request.

Abstract: Head start population of an image backup. In one example embodiment, a method for head start population of an image backup may include tracking blocks that are modified in a source storage between a first point in time and a second point in time, head start copying a first portion of the modified blocks into the image backup prior to the second point in time, activating a snapshot on the source storage at the second point in time where the snapshot represents a state of the source storage at the second point in time, and copying, subsequent to the second point in time, from the snapshot and into the image backup, a second portion of the modified blocks that were not yet copied into the image backup by the second point in time.

Abstract: Compression blocks are divided into partitions creating a two dimensional divide of the compression blocks by slicing the compression blocks forming a first dimension and sub-partitioning the compression blocks into the partitions forming a second dimension. Each one of the partitions are compressed in separate compression streams.

Abstract: Disclosed are a memory storage device and an operating method thereof. The operating method writes data to a plurality of memory devices of the memory storage device through a controller, and performs interleaving programming on the plurality of memory devices. The operating method includes a write request step, a read request step, a page temporary storage area write step, and a device switching step, which are repeated until the respective memory devices complete the above-described steps and a page temporary storage area programming step. Before the page temporary storage area programming step is performed, data transmitted to page temporary storage areas of the respective memory devices are temporarily stored in the page temporary storage areas. Thus, the number of SRAMs can be, reduced, and a programming operation can be performed on a plurality of memory devices at the same time.

Abstract: An interface receives a command corresponding to a non-volatile memory. The interface determines whether a bypass mode is enabled and whether the command is a medium-access command. A primary processing node processes the command in response to determining at least one of the following: that the bypass mode is disabled or that the command is not a medium-access command. A secondary processing node processes the command, in response to determining that the bypass mode is enabled and that the command is a medium-access command.

Abstract: A storage module and method for virtual abort are disclosed. In one embodiment, a virtual abort of a read command is provided. The read command triggers a read operation that comprises reading data from the storage module's memory, processing the data by at least one processing module as the data moves along a data path from the memory to the storage module's host interface module, and then providing the data to a host via the host interface module. When an abort command is received, the storage module allows the data that is read from the memory to be processed by the at least one processing module as the data moves along the data path to the host interface module but prevents the host interface module from providing the data to the host. In another embodiment, a virtual abort of a write command is provided.

Abstract: The present invention discloses a memory access method, a buffer scheduler, and a memory module, which can support multiple application scenarios without changing the memory module or a memory chip. The method includes: receiving an operation request message for memory access data, where the operation request message includes tag information of the memory access data, operation information of the memory access data, and a memory address of the memory access data; and performing, according to at least one of the tag information of the memory access data, a memory address of the memory access data, and the operation information of the memory access data, an operation on the tag of the memory access data and/or the memory access data stored in the memory module. The present invention is applicable to the computer field.

Abstract: A storage control device includes a processor. The processor is configured to classify second type storage devices into a first group and a second group. The second type storage devices temporarily store thereof data held in a first type storage device. The processor is configured to access the first type storage device using storage devices belonging to the second group while updating firmware of storage devices belonging to the first group.

Abstract: A data storage device including a flash memory and a controller. The flash memory has a plurality of single-level-cell units and a plurality of triple-level cell units. The controller performs a first predetermined number of read processes on a second predetermined number of specific single-level-cell units to program data stored in the second predetermined number of specific single-level-cell units into a specific triple-level cell unit of the triple-level cell units and determines whether any of the second predetermined number of specific single-level-cell units has not been read successfully by any of the read processes when the specific triple-level cell unit cannot be read successfully.

Abstract: One or more techniques and/or systems are provided for multicast transport configuration, for multicast transport, and/or for fault policy implementation. In an example, a multicast component may receive a data copy request from an application to copy data to multiple destinations. A scheduler component may create a transport schedule specifying an order with which to facilitate data copy operations across transports, such as heterogeneous transports, to the destinations. A dispatcher component may apply application specified transport modifiers to the data copy operations (e.g., a modification to a quality of service for a transport). The dispatcher component may facilitate the data copy operations and provide operation result information to a policy agent. The policy agent may provide notifications of data copy operation statuses from the operation result information and/or may implement a fault policy (e.g., a retry on a different transport) for a data copy operation that experienced a fault.

Abstract: A storage module includes a set of memories. Each of the memories in the set of memories may be divided into a set of portions. A controller is configured to transfer data between the set of memories and a host connected through an interface. A set of channels connects the set of memories to the controller. The controller is also configured to select: a memory from the set of memories, a portion from the set of portions for the selected memory, and/or a channel from the set of channels, e.g., connected to the selected memory, based upon an identification (ID) associated with the data. The ID may be separate from the data and a write address of the data, and the selected memory, the selected portion, and the selected channel may be used to store the data.

Abstract: A processor-based device for displaying simulated or modeled surface appearances based on surface color and surface texture data stored in a data storage. By selecting different combinations of color and texture, different surface appearances may be modeled and displayed. Also, the device may comprise an orientation sensor. Accordingly, the device may additionally consider the orientation of the device when generating surface appearances.

Abstract: Systems, apparatuses, and methods for moving the interconnect protocol configuration registers into the main memory space of a node. The region of memory used for storing the interconnect protocol configuration registers may also be made cacheable to reduce the latency of accesses to the interconnect protocol configuration registers. Interconnect protocol configuration registers which are used during a startup routine may be prefetched into the host's cache to make the startup routine more efficient. The interconnect protocol configuration registers for various interconnect protocols may include one or more of device capability tables, memory-side statistics (e.g., to support two-level memory data mapping decisions), advanced memory and interconnect features such as repair resources and routing tables, prefetching hints, error correcting code (ECC) bits, lists of device capabilities, set and store base address, capability, device ID, status, configuration, capabilities, and other settings.

Abstract: Disclosed are various embodiments to extract portions of video or audio data from a media summary corresponding to a media content item available in a media content catalog according to one or more predefined rules. The extracted portions of video and audio data are used to generate one or more network pages detailing or describing the media content item.

Abstract: Technologies for multithreaded synchronization including a computing device having a many-core processor. Each processor core includes multiple hardware threads. A hardware thread executed by a processor core enters a synchronization barrier and synchronizes with other hardware threads executed by the same processor core. After synchronization, the hardware thread synchronizes with a source hardware thread that may be executed by a different processor core. The source hardware thread may be assigned using an n-way shuffle of all hardware threads, where n is the number of hardware threads per processor core. The hardware thread resynchronizes with the other hardware threads executed by the same processor core. The hardware thread alternately synchronizes with the source hardware thread and the other hardware threads executed by the same processor core until all hardware threads have synchronized. The computing device may reduce a Boolean value over the synchronization barrier.

Abstract: An apparatus including a tuner configured for receiving television signals; a CPU configured to cause the apparatus to perform operations including: receiving configuration data from a first server; receiving a broadcast data stream for the television content via the tuner; obtaining a first plurality of data chunks from the broadcast data stream, wherein each data chunk encodes a portion of audio and/or video included in the broadcast data stream; determining, based on the configuration data, which of the first plurality of data chunks are included in a second plurality of data chunks for uploading, wherein at least one of the first plurality of data chunks is not included in the second plurality of data chunks; and uploading the second plurality of data chunks to a second server.

Abstract: A computer-implemented method according to one embodiment of the present disclosure includes identifying, by a computer system, an asset associated with a logical zone; detecting a change in an attribute of the asset; and in response to detecting the change in the attribute of the asset, modifying, by the computer system, a configuration setting for a firewall. Among other things, the embodiments of the present disclosure can perform dynamically configure and control security features in response to changes in the computing environment, including asset attribute changes, security events, operational events, user input and environmental changes. Embodiments of the present disclosure thereby help to quickly maintain or change the security posture of a system and maintain the level of compliance with set of predefined security benchmarks or codified best practices.

Abstract: Operating characteristics associated with non-volatile two-terminal memory can be modified post-fabrication, e.g., by a controller that controls the non-volatile two-terminal memory. As a result, two-terminal memory arrays included in memory devices (e.g., memory cards, solid-state drives, etc.) can be flexibly modified to provide numerous advantages over other types of non-volatile memory.

Abstract: A method and information processing system with improved cache organization is provided. Each register capable of accessing memory has associated metadata, which contains the tag, way, and line for a corresponding cache entry, along with a valid bit, allowing a memory access which hits a location in the cache to go directly to the cache's data array, avoiding the need to look up the address in the cache's tag array. When a cache line is evicted, any metadata referring to the line is marked as invalid. By reducing the number of tag lookups performed to access data in a cache's data array, the power that would otherwise be consumed by performing tag lookups is saved, thereby reducing power consumption of the information processing system, and the cache area needed to implement a cache having a desired level of performance may be reduced.

Abstract: The present invention relates to a method of transmitting a message comprising an integrity check and a header, between two processing units via a shared memory, comprising steps of: —generation (501), by a first processing unit, of a first pseudorandom binary string; —encryption (502) of the message to be transmitted by applying an involutive transformation dependent on the first pseudorandom binary string generated; —transmission and storage (503) of the encrypted message in the shared memory; —generation (504), by the second processing unit, of a second pseudorandom binary string; —decryption of the message stored by applying an involutive transformation dependent on the second pseudorandom binary string, and by decrypting the header (505) of said message, by verifying the decrypted header (505), and as a function of the result of the verification, by decrypting the complete message (506); —verification (507) of the integrity of the decrypted message on the basis of its integrity check.

Abstract: A communication device capable of performing wireless communication measures an actual time from a first timing (at which a communication request instructing to perform communication with a specific device is informed from an application program on the communication device to an OS (Operating System) on the communication device) to a second timing (at which reply information in response to the communication request is informed from the OS to the application program). When the actual time is greater than a predetermined threshold, the communication device determines that an associating process has been performed by the OS in a specific period from the first timing to the second timing, the associating process previously registering the communication device and the specific device in association with each other. When the actual time is smaller than the predetermined threshold, the communication device determines that the associating process has not been performed in the specific period.

Abstract: A storage system for constructing RAID on the basis of flash memory comprises: one or more RAID processors and a plurality of flash memories. The RAID processor comprises a plurality of read-and-write processing units, a data block pointer unit, a data block counter and a parity check code buffer. One read and write processing unit can control one or more flash memory units. A method for constructing RAID in a storage system on the basis of flash memory can realize the function of RAID in a very small logic area and approximately negligible time and realize the unification of the function and performance of a storage system such as an enterprise-level SSD.

Abstract: PCI devices write an MSI message in a memory and polling routines, which are executed by CPU cores respectively, poll the memory. The polling routines poll a cause of interrupt during an interval between tasks, during an interval between threads, and during idle and cause a CPU core with the lowest load to perform interrupt processing. An IO task performs inter-task communication with another IO task by using a command queue.

Abstract: Systems and method are disclosed for processing data storage commands for enclosure services. In one embodiment, a data storage device may include a virtual ATA packet interface (VATAPI). The VATAPI may identify itself as a SCSI enclosure services (SES) device. The VATAPI may allow the data storage device to use SES operations/commands to perform operations/commands for enclosure services.

Abstract: Embodiments include methods, systems and computer program products for performing a composite sort on a tunable hardware sort engine includes determining desired sort performance parameters, configuring a composite sort engine based on the desired sort performance parameters, and receiving a plurality of keys having a payload associated with each of the plurality of keys. The method also includes reserving DRAM storage for each of the payloads, generating a tag for each of the plurality of keys, the tag identifying the DRAM storage reserved for each of the payloads, and storing the payloads in the portions of the DRAM storage. The method further includes generating a composite key for each of the plurality of keys, sorting the composite keys by the composite sort engine, and retrieving the payloads associated with the sorted composite keys from the DRAM storage. The method also includes outputting the payloads associated the sorted composite keys.

Abstract: In accordance with an embodiment of the present disclosure, a semiconductor device may be provided. The semiconductor device may semiconductor device may be configured to store a bank address applied to an active signal from among command signals, and may perform a read or a write operation using the stored bank address based on activation of a command signal.

Abstract: The various embodiments described herein include systems, methods and/or devices used to enable firmware reversion triggering and control in a storage device. In one aspect, the method includes: (1) detecting a reversion trigger, the reversion trigger identifying a set of one or more controllers of a plurality of controllers on the storage device, and (2) in response to the reversion trigger, initiating recovery actions for each controller in the set of one or more controllers, including: for each controller in the set of one or more controllers: (a) asserting a revert signal to the controller to execute a firmware reversion for the controller, and (b) resetting the controller subsequent to asserting the revert signal to the controller.

Abstract: Frames in a variable length frame format which are addressed to a plurality of users are multiplexed and preferably transmitted. Data frames having different lengths are multiplexed on a same time through space division multiple access, but since the multiplexed frames are transmitted while eventually having a same length, when the multiplexed data frames from the access point STA0 are received in the respective communication stations STA1 to STA3 in FIG. 4 or when data simultaneously transmitted from the respective communication stations STA1 to STA3 are received in the access point STA0 in FIG. 5, it is possible to eliminate an operation instability of AGC.

Abstract: A method of operating a storage controller is provided. The method includes receiving first host data traffic from a host, for storage in a first partition within a storage system, the first host data traffic formatted for storage in a first type of data storage, and translating the first host data traffic into storage data, the storage data formatted for storage in a second type of data storage. The method further includes storing the storage data in the first partition, receiving a read request from the host through the host interface, and retrieving some or all of the storage data from the first partition. The method also includes formatting the some or all of the storage data into a format compatible with the first host data traffic, and transferring the formatted data to the host in a configuration corresponding to the first type of data storage.

Abstract: In general, one aspect of the subject matter described in this specification is embodied in operations of processing sequence data by selecting a distribution key according to a type of one or more tasks to be performed on the data. The key is one or more data fields of a sequence data file, e.g., a sequence alignment/map (SAM) format or binary sequence alignment/map (BAM) format file, or derived from one or more data fields of a sequence data file. The sequence data is then distributed to multiple nodes of a parallel processing relational database system. The system performs the tasks of processing the sequence data by executing database queries. The system executes the database queries on multiple nodes in parallel. The system can use query optimization functions built into the database to expedite performance of each task.

Abstract: This disclosure relates to systems and methods for adaptive configuration of software based on current and historical data. In one embodiment, a method is disclosed, which comprises receiving first data that reflects a first status of an execution of a software task. The method further comprises determining, based on the first data, a first set of configurations to be provided for the execution of the software task, wherein each configuration of the first set of configurations is associated with a weight that reflects a statistic measurement of a prior status of an execution of the software task when the configuration is provided, and wherein the first set of configurations are ranked based on the weights. The method also comprises providing, based on the ranking, at least one of the first set of configurations for the execution of the software task.

Abstract: The disclosure is directed to storing data in different tiers of a database based on the access pattern of the data. Immutable data, e.g., data that does not change or changes less often than a specified threshold, is stored in a first storage tier of the database, and mutable data, e.g., data that changes more often than immutable data, is stored in a second storage tier of the database. The second storage tier of the database is more performant than the first storage tier, e.g., the second storage tier has a higher write endurance and a lower write latency than the first storage tier. All writes to the database are performed at the second storage tier and reads on both storage tiers. The storage tiers are synchronized, e.g., the set of data is copied from the second to the first storage tier based on a trigger, e.g., a specified schedule.

Abstract: A tape drive adapted for providing a best access order for files or data sets on a tape loaded into the tape drive. The tape drive includes a processor and memory storing a file location table for the tape. The file location table includes identifiers for a plurality of files on the tape and location information for the plurality of files on the tape. The tape drive includes an order determination module, executed by the processor, processing an order request. The order request, from a host or user, includes a list of the files on the tape from which to generate, based on the location information in the file location table, a reordered list defining an order for accessing the files on the tape. The reordered list or best access order has (or produces via tape drive access) an access time for the files that is minimal or reduced.

Abstract: Embodiments include methods, systems and computer program products for performing a composite sort on a tunable hardware sort engine includes determining desired sort performance parameters, configuring a composite sort engine based on the desired sort performance parameters, and receiving a plurality of keys having a payload associated with each of the plurality of keys. The method also includes reserving DRAM storage for each of the payloads, generating a tag for each of the plurality of keys, the tag identifying the DRAM storage reserved for each of the payloads, and storing the payloads in the portions of the DRAM storage. The method further includes generating a composite key for each of the plurality of keys, sorting the composite keys by the composite sort engine, and retrieving the payloads associated with the sorted composite keys from the DRAM storage. The method also includes outputting the payloads associated the sorted composite keys.

Abstract: To effectively and efficiently provide control information, a broadcast pointer channel (BPCH) may be used to identify the type and perhaps relative location of control information that is being provided in a given frame structure, such as a sub-frame, frame, or superframe. A sub-frame (or like framing entity, such a frame or superframe) may have a BPCH and a corresponding system control information segment in which control information may reside. The system control information segment may have any number of control information blocks, wherein each control information block that is present may correspond to a particular type of control information. The BPCH is used to identify the type of control information that is present in a corresponding system control information segment, and if needed or desired, the relative locations of the various control information.

Abstract: In one embodiment, a method includes receiving a request to duplicate at least a portion of a volume stored on a first storage array managed by a storage controller, creating at least one dependent volume on the first storage array using the storage controller, duplicating the at least the portion of the volume to the at least one dependent volume on the first storage array to create a snapshot. The creation of the snapshot is performed entirely on the first storage array.