Storage Accessing And Control Patents (Class 711/100)
  • Patent number: 10339044
    Abstract: The various implementations described herein include systems, methods and/or devices used for garbage collection in memory system. The method includes: (1) determining occurrences of triggering events including data reclamation events, urgent data integrity recycling events, and scheduled data integrity recycling events, and (2) recycling, in response to each of a plurality of triggering events, data in a predefined quantity of memory units from a source memory portion to a target memory portion of the memory system. A respective data reclamation event corresponds to the occurrence of host data write operations in accordance with a target reclamation to host write ratio. A respective urgent data integrity recycling event occurs when a memory portion satisfies predefined urgent read disturb criteria. A respective scheduled data integrity recycling event occurs at a rate corresponding to a projected quantity of memory units to be recycled by the memory system over a period of time.
    Type: Grant
    Filed: February 1, 2017
    Date of Patent: July 2, 2019
    Assignee: SanDisk Technologies LLC
    Inventors: James M. Higgins, Ryan R. Jones
  • Patent number: 10324760
    Abstract: The described embodiments include a computing device that has two or more levels of memory, each level of memory having different performance characteristics. During operation, the computing device receives a request to lease an available block of memory in a specified level of memory for storing an object. When a block of memory is available for leasing in the specified level of memory, the computing device stores the object in the block of memory in the specified level of memory. The computing device also commences the lease for the block of memory by setting an indicator for the block of memory to indicate that the block of memory is leased. During the lease (i.e., until the lease is terminated), the object is kept in the block of memory.
    Type: Grant
    Filed: April 29, 2016
    Date of Patent: June 18, 2019
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventor: Mitesh Meswani
  • Patent number: 10324633
    Abstract: A technique for use in balancing flash drive wear in data storage systems is disclosed. multiple sets of flash drives are identified where data is stored as multiple slices striped across the set of flash drives. A write rate at which data will be written to the multiple slices stored on the set of flash drives during a next time interval is predicted. A number of bytes that can be written to each set of flash drives is determined. A wear metric representative of a wear rate is determined for each set of flash drives. A write quota and an interval period is determined for one or more sets of flash drives. If the wear metric exceeds the write quota for one or more sets of flash drives during the time interval, reduce the wear rate for the one or more sets of flash drives.
    Type: Grant
    Filed: October 26, 2016
    Date of Patent: June 18, 2019
    Assignee: EMC IP Holding Company LLC
    Inventor: Nickolay A. Dalmatov
  • Patent number: 10318163
    Abstract: A technique for use in balancing flash drive wear in data storage systems is disclosed. multiple sets of flash drives are identified where data is stored as multiple slices striped across the set of flash drives. A write rate at which data will be written to the multiple slices stored on the set of flash drives during a next time interval is predicted. A number of bytes that can be written to each set of flash drives is determined. A metric representative of a wear rate is determined for each set of flash drives. Flash drive wear rate is balanced such that the wear rate for each of the multiple is approximately equal.
    Type: Grant
    Filed: October 26, 2016
    Date of Patent: June 11, 2019
    Assignee: EMC IP Holding Company LLC
    Inventor: Nickolay A. Dalmatov
  • Patent number: 10310870
    Abstract: It is often desired to add or change the functionality of an existing executable, also known as binary. Simply splicing in new machine code into the binary will not work due to host system-specific and platform-specific limitations. The present invention will enable adding any new code to an existing program while overcoming the aforementioned consistency limitations and maintaining the original functionality.
    Type: Grant
    Filed: August 8, 2016
    Date of Patent: June 4, 2019
    Assignee: APPDOME LTD.
    Inventors: Avner Yehuda, Omer Schory, Meir Tsvi, Daniel Zatuchne
  • Patent number: 10296379
    Abstract: Scheduling threads in a system with many cores includes generating a thread map where a connection relationship between a plurality of threads is represented by a frequency of inter-process communication (IPC) between threads, generating a core map where a connection relationship between a plurality of cores is represented by a hop between cores, and respectively allocating the plurality of threads to the plurality of cores defined by the core map, based on a thread allocation policy defining a mapping rule between the thread map and the core map.
    Type: Grant
    Filed: March 17, 2017
    Date of Patent: May 21, 2019
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Kang Ho Kim, Kwang Won Koh, Jin Mee Kim, Jeong Hwan Lee, Seung Hyub Jeon, Sung In Jung, Yeon Jeong Jeong, Seung Jun Cha
  • Patent number: 10296246
    Abstract: Various embodiments are directed to providing integrity protection for a system management mode. During initialization, a hash value of a system management mode control routine may be determined. Subsequently, during operation, the hash value may be compared to a hash value of a system management mode control routine to be executed. The system management mode control routine to be executed may be determined to be authentic if the hash values are the same.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: May 21, 2019
    Assignee: INTEL CORPORATION
    Inventors: Jorge E. Gonzalez Diaz, Juan Manuel Cruz Alcaraz
  • Patent number: 10296240
    Abstract: A storage controller for cache management that includes a cache memory and a cache management module. The cache management module to, on receipt of region specification requests from hosts, extract from the region specification requests cache rules for management of regions of data storage of a storage array, and on receipt of data operation requests from hosts, process the data operation requests based on the extracted cache rules.
    Type: Grant
    Filed: April 28, 2014
    Date of Patent: May 21, 2019
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Nathaniel S DeNeui, Michael White, Jeffrey A Plank
  • Patent number: 10296418
    Abstract: A versioned records management computing system that uses a restart era in order to promote rapid recovery. A persistent store includes a multi-versioned record collection. The records are also associated with a restart era that corresponds to the era of operation of the computing system after a restart. Upon a recovery, the current restart era changes. An object collection media has an object collection that conforms to an object model such that the object model is used to operate upon the records. The object collection media is operable such that the object collection is durable so as to survive restarts of the system to thereby allow for accelerated recovery.
    Type: Grant
    Filed: January 19, 2016
    Date of Patent: May 21, 2019
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Per-Ake Larson, Robert Patrick Fitzgerald, Cristian Diaconu
  • Patent number: 10289710
    Abstract: Embodiments of the present invention provide a method for modifying a root node, and a modification apparatus. The method for modifying a root node of the present invention includes: receiving a root node modification request; modifying a root node in a data area of a database according to the modification information; replicating the modified root node to the general area of the database; finding, in the general area of the database, that an identifier of an active mapping page is the identifier of the first mapping page, and determining that the first mapping page is the active mapping page; and replacing the second mapping page with the modified root node according to the modified root node that is replicated to the general area, and modifying the identifier of the active mapping page to the identifier of the second mapping page. The present invention improves concurrent processing efficiency of indexing.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: May 14, 2019
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Yuansheng Liang, Li Yao, Jixuan Wang
  • Patent number: 10289502
    Abstract: Methods, computing systems and computer program products implement embodiments of the present invention that include defining a plurality of failure domains for sets of storage devices in a storage facility, and defining, using the failure domains, one or more limitations for distributing data on the storage devices. Upon identifying a data distribution configuration for a software defined storage system that is compliant with the one or more limitations, the identified data distribution configuration can be presented to a user. The failure domains may include physical failure domains, logical failure domains, or a combination of physical and logical failure domains, and the limitations may include mandatory limitations or a combination of mandatory and non-mandatory limitations.
    Type: Grant
    Filed: March 7, 2016
    Date of Patent: May 14, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Zah Barzik, Lior Chen, Michael Keller, Rivka M. Matosevich
  • Patent number: 10282323
    Abstract: A semiconductor chip comprising memory controller circuitry having interface circuitry to couple to a memory channel. The memory controller includes first logic circuitry to implement a first memory channel protocol on the memory channel. The first memory channel protocol is specific to a first volatile system memory technology. The interface also includes second logic circuitry to implement a second memory channel protocol on the memory channel. The second memory channel protocol is specific to a second non volatile system memory technology. The second memory channel protocol is a transactional protocol.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: May 7, 2019
    Assignee: Intel Corporation
    Inventors: Bill Nale, Raj K. Ramanujan, Muthukumar P. Swaminathan, Tessil Thomas, Taarinya Polepeddi
  • Patent number: 10282324
    Abstract: A multi-streaming memory system includes a memory, and a processor coupled to the memory, the processor executing a software component that is configured to identify multiple attributes that are each related to logical block addresses (LBAs), and that each correspond to each of a plurality of streams of data writes, evaluate an importance factor for each of the attributes for each of the streams, and clustering two or more of the LBAs by assigning a stream ID to each of the LBAs based on all of the importance factors for each of the LBAs and the assigned stream.
    Type: Grant
    Filed: November 4, 2016
    Date of Patent: May 7, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Janki S. Bhimani, Jingpei Yang, Changho Choi, Jianjian Huo
  • Patent number: 10275164
    Abstract: In one implementation, a computer-implemented method can include receiving, at a driver running on a mobile computing device with a local power source, a command from an application for an allocation of volatile memory; allocating, by the driver, memory from a pool of volatile memory for the application; storing data in the allocated memory; detecting, by the driver, that a particular situation currently exists on the mobile computing device that will cause the data to be lost; and performing, by the driver, an operation with regard to the memory and the data that will cause the data to be preserved following a conclusion of the particular situation.
    Type: Grant
    Filed: May 27, 2016
    Date of Patent: April 30, 2019
    Assignee: NUtech Ventures
    Inventors: Hao Luo, Hong Jiang, Lei Tian
  • Patent number: 10268557
    Abstract: According to an embodiment, a network monitoring device that monitors a network includes a software storage and a controller. The software storage is configured to store software applied to a first electronic device connected to the network. The controller is configured to determine, in response to reception of verification result data indicating software verification failure from the first electronic device, whether a recovery condition determined in advance as a condition of recovering software in the first electronic device is satisfied, and perform a control of transmitting the software stored in the software storage to the first electronic device when it is determined that the recovery condition is satisfied.
    Type: Grant
    Filed: February 23, 2017
    Date of Patent: April 23, 2019
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshiyuki Kito, Takeshi Kawabata
  • Patent number: 10261910
    Abstract: Methods, devices, and non-transitory process-readable storage media for compacting data within cache lines of a cache. An aspect method may include identifying, by a processor of the computing device, a base address (e.g., a physical or virtual cache address) for a first data segment, identifying a data size (e.g., based on a compression ratio) for the first data segment, obtaining a base offset based on the identified data size and the base address of the first data segment, and calculating an offset address by offsetting the base address with the obtained base offset, wherein the calculated offset address is associated with a second data segment. In some aspects, the method may include identifying a parity value for the first data segment based on the base address and obtaining the base offset by performing a lookup on a stored table using the identified data size and identified parity value.
    Type: Grant
    Filed: March 22, 2016
    Date of Patent: April 16, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Andrew Edmund Turner, George Patsilaras, Bohuslav Rychlik
  • Patent number: 10248330
    Abstract: A data storage device with one or more buffers can employ buffer tenure management with at least a data storage device having a first buffer, a second buffer, a buffer manager, and a non-volatile memory. The first buffer can be located on-chip while the second buffer is located off-chip. The first buffer may be filled with data having a tenure of less than a predetermined tenure threshold as directed by the buffer manager.
    Type: Grant
    Filed: May 30, 2017
    Date of Patent: April 2, 2019
    Assignee: Seagate Technology LLC
    Inventors: Jackson Ellis, Jeffrey Munsil, Timothy Canepa, Stephen Hanna
  • Patent number: 10250616
    Abstract: A server includes communication circuitry configured to communicate with a plurality of external terminals, a storage which stores reference data for hardware integrity verification of the plurality of external terminals, and a processor configured to verify the hardware integrity of a second external terminal using the reference data, when a request for the hardware integrity verification of the second external terminal is received through the communication circuitry from a first external terminal.
    Type: Grant
    Filed: August 10, 2016
    Date of Patent: April 2, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seung-hyun Ha, Dong-uk Kim, Jin-mok Kim
  • Patent number: 10249014
    Abstract: During a process of migrating a source system into a standardized virtual environment, virtual machine instances of the source system executing in a hypervisor are snapshotted as virtual machine images in an operational repository of the hypervisor. The virtual machine images in the operational repository are short-term snapshots. From time to time during the migration process, long-term snapshots of the source system are created by checking given ones of the virtual machine images from the hypervisor operational repository into an image library as image objects.
    Type: Grant
    Filed: April 23, 2017
    Date of Patent: April 2, 2019
    Assignee: International Business Machines Corporation
    Inventors: Vasanth Bala, Kamal Bhattacharya, Thomas Diethelm, Praveen Jayachandran, Lakshminarayanan Renganarayana, Marcel Schlatter, Akshat Verma, Xiaolan Zhang
  • Patent number: 10242111
    Abstract: A method for filtering out nodes associated with hierarchical data structures is provided. The method may include generating node controllers on the hierarchical data structures. The method may include determining whether user actions are received on a first node controller, a second node controller, and a third node controller associated with the generated plurality of node controllers. The method may include filtering node levels associated with hierarchical data structures, and presenting the hierarchical data structures without the filtered out node levels. The method may include filtering out sibling nodes associated with the hierarchical data structures, and presenting the hierarchical data structures without the filtered out sibling nodes. The may further include reverse-collapsing first node levels and filtering out second node levels based on the reverse-collapsed first node levels, and presenting the hierarchical data structures without the filtered out second node levels.
    Type: Grant
    Filed: March 22, 2016
    Date of Patent: March 26, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Yang Cao, He Jiang Jia, Xiao Zhen Zhu
  • Patent number: 10228883
    Abstract: A storage device includes a non-volatile storage, and a controller configured to carry out, in parallel, operations in response to a plurality of commands received from a host and queued in a command queue. When the controller receives, from the host, a read command and then a subsequent command before all data read from the non-volatile storage are transmitted to the host in response to the read command, the controller transmits a response to the subsequent command after part of the data read from the non-volatile storage are transmitted to the host and before the all data read from the non-volatile storage are transmitted to the host.
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: March 12, 2019
    Assignee: Toshiba Memory Corporation
    Inventor: Nobuyuki Myouga
  • Patent number: 10223103
    Abstract: Embodiments of the present disclosure relate to the communications field and disclose a read-only memory (ROM) flashing method and an intelligent terminal, so as to implement lossless ROM flashing on an original system of the intelligent terminal. A solution provided by the embodiments of the present disclosure includes: the intelligent terminal includes a virtual extended system and an original system, the original system runs a factory system file of the intelligent terminal, and the virtual extended system runs a ROM flashing system file; when a ROM flashing instruction entered by a user is received, the ROM flashing system file is written into a storage image file of the virtual extended system; and the virtual extended system is started to run the ROM flashing system file. The present disclosure is used to perform ROM flashing on an intelligent terminal.
    Type: Grant
    Filed: October 6, 2017
    Date of Patent: March 5, 2019
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Zhijun Lu, Laifa Zhang, Yakun Wang
  • Patent number: 10223257
    Abstract: Apparatus for a garbage collection is disclosed herein. The apparatus includes a processor that includes a load-monitored region register. A memory stores program code, which, when executed on the processor performs an operation for garbage collection, the operation includes specifying a load-monitored region within a memory managed by a runtime environment; enabling a load-monitored event-based branch configured to occur responsive to executing a first type of CPU instruction to load a pointer that points to a first location in the load-monitored region; performing a garbage collection process in background without pausing executing in the runtime environment; executing a CPU instruction of the first type to load a pointer that points to the first location in the load-monitored region; responsive to triggering a load-monitored event-based branch, moving an object pointed to by the pointer with a handler from the first location in memory to a second location in memory.
    Type: Grant
    Filed: July 27, 2015
    Date of Patent: March 5, 2019
    Assignee: International Business Machines Corporation
    Inventors: Giles R. Frazier, Michael Karl Gschwind, Younes Manton, Karl M. Taylor, Brian W. Thompto
  • Patent number: 10216757
    Abstract: A method is used in managing deletion of replicas of files. A request to delete a set of replicas of a file of a file system is received. A replica of the file represents a state of the file at a particular prior point in time. A destination replica is identified. A set of file system blocks shared between a replica of the set of replicas and the destination replica is de-allocated by updating metadata of the destination replica. File system blocks associated with the set of replicas are de-allocated. A subset of the file system blocks are de-allocated concurrently.
    Type: Grant
    Filed: December 23, 2014
    Date of Patent: February 26, 2019
    Assignee: EMC IP Holding Company LLC
    Inventors: Philippe Armangau, Junping Zhao, Yining Si, Fenghao Zhang, Gang Xie
  • Patent number: 10205732
    Abstract: A file protection method may include receiving a package that includes files for installing and executing an application, adding a protection file for an operation of a file protection module to the package, and providing the package to which the protection file is added over a network. In response to execution of a control command for a desired file that is controlled by the application through a service code of the application at an electronic device on which the application is installed and executed through the package, a protection command included in the file protection module is called and control of the desired file and integrity verification associated with data stored in the desired file are processed in response to the called protection command.
    Type: Grant
    Filed: February 7, 2017
    Date of Patent: February 12, 2019
    Assignee: Line Corporation
    Inventors: Sungbeom Ahn, SangHun Jeon, Myungju Chung, Dongpil Seo, Seong Yeol Lim, Wang Jin Oh, Kwang-Hee Han
  • Patent number: 10204699
    Abstract: A method for migrating data to avoid read disturbance is introduced to contain the following steps: obtaining first read counts corresponding to physical blocks from a first read-count table; obtaining second read counts corresponding to the physical blocks from a second read-count table; subtracting each first read count from one corresponding second read count to generate third read counts; finding a singular physical-block from physical blocks according to the third read counts; performing a test read on data of the ith physical page of the singular physical-block; determining whether the data of the ith physical page of the singular physical block has passed the test read; and if so, moving or copying data of the ith physical page and at least one neighboring physical-page of the singular physical block to an available physical-block.
    Type: Grant
    Filed: June 27, 2017
    Date of Patent: February 12, 2019
    Assignee: SHANNON SYSTEMS LTD.
    Inventor: Ting-Kuan Lin
  • Patent number: 10198371
    Abstract: Apparatuses and methods for transferring data from memory on a data path are described. An example apparatus includes: one or more data terminals; a plurality of memory banks, one of the plurality of memory banks being selected responsive, at least in part, to a bank address; and a data path including a plurality of data path routes and a plurality of switching buffers on the plurality of data path routes. The plurality of switching buffers are arranged such that one or more of the plurality of switching buffers are selected responsive, at least in part, to the bank address and activates one of the plurality of data path routes.
    Type: Grant
    Filed: August 28, 2015
    Date of Patent: February 5, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Hiromasa Noda
  • Patent number: 10198327
    Abstract: A method for recovering data from one or more storage systems for a group recovery. In response to receiving a request for the group recovery, the method implemented at a backup server identifies a group recovery resource based on the request, where the group recovery resource includes one or more recovery item lists. The backup server traverses the one or more recovery item lists of the group recovery resource to determine a source recovery storage system, target recovery storage systems, and one or more data items to be recovered to each of the target recovery storage systems. The backup server then initiates one or more recovery sessions to recover the one or more data items from the source recovery storage systems to the recovery target storage systems substantially concurrently.
    Type: Grant
    Filed: September 22, 2015
    Date of Patent: February 5, 2019
    Assignee: EMC IP Holding Company LLC
    Inventors: Ajith Gopinath, Kishore Kumar, Sathyamoorthy Viswanathan
  • Patent number: 10186290
    Abstract: A data storage device is disclosed wherein a first host block is written to a first data sector, and when writing a second host block to a second data sector the first host block is read from the first data sector. When the read of the first host block fails, a partial map is generated identifying a location of the second host block in the second data sector, the partial map is stored in a non-volatile memory, and the second host block is written to the second data sector. When a power failure occurs after writing the second host block to the second data sector, an exception entry is updated using the partial map, wherein the exception entry is associated with the first and second host blocks.
    Type: Grant
    Filed: May 25, 2017
    Date of Patent: January 22, 2019
    Assignee: Western Digital Technologies, Inc.
    Inventor: Ajay S. Nair
  • Patent number: 10180879
    Abstract: A system and method for offset protection data in a RAID array. A computer system comprises client computers and data storage arrays coupled to one another via a network. A data storage array utilizes solid-state drives and Flash memory cells for data storage. A storage controller within a data storage array is configured to store user data in a first page of a first storage device of the plurality of storage devices; generate intra-device protection data corresponding to the user data, and store the intra-device protection data at a first offset within the first page. The controller is further configured to generate inter-device protection data corresponding to the first page, and store the inter-device protection data at a second offset within a second page in a second storage device of the plurality of storage devices, wherein the first offset is different from the second offset.
    Type: Grant
    Filed: December 14, 2015
    Date of Patent: January 15, 2019
    Assignee: Pure Storage, Inc.
    Inventors: John Colgrove, John Hayes, Bo Hong, Ethan Miller
  • Patent number: 10177913
    Abstract: A semiconductor device may include: a bus; first and second function modules configured to communicate via the bus; a first encryption module configured to encrypt first data output from the first function module using a first encryption key to generate first encrypted data; and/or a second encryption module configured to decrypt the first encrypted data using the first encryption key, to output the decrypted first data to the second function module, and to encrypt second data output from the second function module using a second encryption key to generate second encrypted data. A semiconductor device may include: a bus; first and second modules configured to communicate via the bus; and/or an encryption module configured to use different encryption policies for first data, which is output from the first module and stored in a memory, and second data, which is output from the second module and stored in the memory.
    Type: Grant
    Filed: May 15, 2015
    Date of Patent: January 8, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Heon Soo Lee, Yong Ki Lee, Sang Hyun Park, Mi Jung Noh, Hong Mook Choi, Dong Jin Park, Woo Hyung Chun
  • Patent number: 10170176
    Abstract: Various embodiments of the invention relate generally to an electronic device, and more particularly, to a semiconductor memory device and an operating method thereof. A semiconductor memory device including a plurality of memory cells using an optimal input buffer reference voltage may include at least one input buffer receiving data to be stored in the plurality of memory cells, and an input buffer reference voltage control unit setting one of a plurality of internal voltages generated beforehand and having different voltage levels as a reference voltage of the at least one input buffer in response to a control signal received from a controller controlling the semiconductor memory device.
    Type: Grant
    Filed: June 6, 2017
    Date of Patent: January 1, 2019
    Assignee: SK Hynix Inc.
    Inventor: Sung Hwa Ok
  • Patent number: 10169358
    Abstract: Embodiments of the present invention provide methods, systems, and computer program products for data deduplication. In one embodiment, for a data chunk, it is determined whether a hash value of the data chunk generated by a first hash function is present in a hash table. Once a threshold size of the hash table is reached, it is determined whether there is free space in a write data area, identified by a second hash function. When there is no free space in the write data area, a post-deduplication process is performed for each data chunk in the write data area. Once free space is cleared in the write data area, the data chunk is written to the write data area identified by the second hash function.
    Type: Grant
    Filed: October 8, 2015
    Date of Patent: January 1, 2019
    Assignee: International Business Machines Corporation
    Inventors: Hiroshi Araki, Tohru Hasegawa
  • Patent number: 10168908
    Abstract: A method for storage volumes in a cascade of storage volumes including starting a first data map relating a first storage volume to a second storage volume while a second data map relating the first storage volume and a third storage volume is active. Starting the first data map uses a zone map that relates the first storage volume to a zone within the cascade of storage volumes.
    Type: Grant
    Filed: November 3, 2017
    Date of Patent: January 1, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: John P. Agombar, Christopher B. E. Beeken, Stephanie Machleidt
  • Patent number: 10169121
    Abstract: Disclosed herein are systems and methods for managing information management operations. The system may be configured to employ a work flow queue to reduce network traffic and manage server processing resources. The system may also be configured to forecast or estimate information management operations based on estimations of throughput between computing devices scheduled to execute one or more jobs. The system may also be configured to escalate or automatically reassign notification of system alerts based on the availability of system alert recipients. Various other embodiments are also disclosed herein.
    Type: Grant
    Filed: May 9, 2014
    Date of Patent: January 1, 2019
    Assignee: Commvault Systems, Inc.
    Inventors: Anand Vibhor, Bhavyan Bharatkumar Mehta, Amey Vijaykumar Karandikar
  • Patent number: 10169407
    Abstract: A computer-implemented method is provided for storing process data. The method comprises allocating a storage area for the process data in the storage means, loading the process data, from the at least one source system, and storing the process steps according to a predetermined data structure in the allocated storage area of the storage means. The predetermined data structure comprises a first attribute, in which a unique identification of the process instance of the respective process step is stored, a second attribute, in which an identification of the respective process step is stored, and a third attribute, in which the sequence of the process steps within a process instance is stored. The method then sorts the process steps in the allocated storage area, wherein the process steps are first sorted according to the first attribute, and subsequently, according to the third attribute.
    Type: Grant
    Filed: September 4, 2015
    Date of Patent: January 1, 2019
    Assignee: CELONIS SE
    Inventors: Alexander Rinke, Martin Klenk, Bastian Nominacher
  • Patent number: 10169224
    Abstract: A data protecting method, a memory storage apparatus and a memory control circuit unit are provided. The method includes: determining whether a first procedure being executed or about to be executed by the memory storage device is a first type procedure; and if the first procedure being executed or about to be executed by the memory storage device is the first type procedure, temporarily stopping receiving a first data corresponding to a first write command before the first procedure is finished.
    Type: Grant
    Filed: April 3, 2014
    Date of Patent: January 1, 2019
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Chih-Kang Yeh
  • Patent number: 10162975
    Abstract: A computer system with multiple security levels, the system comprising a high-power processing device (130), a low-power processing device (110), and an interface unit (120) comprising functions for moving classified information between the high-power device (130) and the low-power device (110) according to formal rules for confidentiality and/or integrity. Additional security aspects, e.g. availability, may readily be accommodated. A method for implementing multiple levels of security along a number of independent security axes on the system is also disclosed.
    Type: Grant
    Filed: September 18, 2017
    Date of Patent: December 25, 2018
    Assignee: CUPP Computing AS
    Inventor: Omar Nathaniel Ely
  • Patent number: 10162835
    Abstract: Proactive management of a plurality of storage arrays in a multi-array system, including: comparing one or more conditions of a particular storage array to conditions of other storage arrays in the multi-array system; and generating an action recommendation based on the comparison, the action recommendation specifying one or more actions for improving the conditions of the particular storage array relative to the conditions of the other storage arrays.
    Type: Grant
    Filed: December 15, 2015
    Date of Patent: December 25, 2018
    Assignee: Pure Storage, Inc.
    Inventors: Benjamin Borowiec, Terence Noonan
  • Patent number: 10156890
    Abstract: In one embodiment of the invention, a memory apparatus is disclosed. The memory apparatus includes a memory array, a block read/write controller, and a random access read memory controller. The memory array is block read/write accessible and random read accessible. The block read/write controller is coupled between the memory array and an external interconnect. The block read/write controller performs block read/write operations upon the memory array to access blocks of consecutive memory locations therein. The random access read memory controller is coupled between the memory array and the external interconnect in parallel with the block read/write access controller. The random access read memory controller performs random read memory operations upon the memory array to access random memory locations therein.
    Type: Grant
    Filed: April 6, 2016
    Date of Patent: December 18, 2018
    Assignee: VIRIDENT SYSTEMS, LLC
    Inventors: Vijay Karamcheti, Kenneth Alan Okin, Kumar Ganapathy
  • Patent number: 10157016
    Abstract: A memory system and method of operating the same is described, where the memory system is used to store data in a RAIDed manner. The stored data may be retrieved, including the parity data so that the stored data is recovered when the first of either the stored data without the parity data, or the stored data from all but one memory module and the parity data, has been received. The writing of data, for low write data loads, is managed such that only one of the memory modules of a RAID stripe is being written to, or erased, during a time interval.
    Type: Grant
    Filed: March 1, 2016
    Date of Patent: December 18, 2018
    Assignee: VIOLIN SYSTEMS LLC
    Inventor: Jon C. R. Bennett
  • Patent number: 10146623
    Abstract: Example implementations relate to obtaining information about and indicating a state of a storage device. In example implementations, an indication that a storage device is rebuilding address mappings may be received, and how much progress has been made in the rebuilding may be determined. A representation of the progress made in the rebuilding may be displayed.
    Type: Grant
    Filed: November 18, 2013
    Date of Patent: December 4, 2018
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Byron A. Alcorn, Bruce Trevino, Scotty M. Wiginton
  • Patent number: 10146842
    Abstract: Methods, systems, and apparatus, for selecting one or more native application deep links from search results and instantiating, for each native application deep link that is selected, a background instance of the native application to which the native application deep link corresponds; determining, in response to an occurrence of a background unload event, background instances of the native applications instantiated from the native application deep links and that were not brought to the foreground prior to the occurrence of the background unload event; and terminating each of the background instances of the native applications instantiated that were not brought to the foreground prior to the occurrence of the background unload event.
    Type: Grant
    Filed: November 19, 2015
    Date of Patent: December 4, 2018
    Assignee: Google LLC
    Inventors: Jaehyun Yeom, Dong Ha Lee, Jongho Choy
  • Patent number: 10133881
    Abstract: A circuit arrangement and method for securing an integrated electronic circuit against scans of an address space, wherein the circuit arrangement has at least one master unit and at least one slave unit interconnected via a bus system for access of the master unit to the slave unit, and addresses are used from an address space that is allocated and used in accordance with functionalities of the integrated electronic circuit, where a defense slave unit is connected to the bus system, access to unused address regions of the address space are forwarded to the defense slave unit, the access is analyzed and evaluated by the defense slave unit and depending on an analysis result and the respective access type, defensive measures are triggered, such that address space scans are interrupted or a potential scan result is rendered useless in a simple manner.
    Type: Grant
    Filed: July 17, 2014
    Date of Patent: November 20, 2018
    Assignee: Siemens AG Österreich
    Inventors: Friedrich Eppensteiner, Majid Ghameshlu, Herbert Taucher
  • Patent number: 10133483
    Abstract: A memory system and method for differential thermal throttling are disclosed. In one embodiment, a memory system is provided comprising a memory and a controller. The controller is configured to receive a command to perform an operation in the memory and analyze the command to determine whether thermal throttling the memory system would result in an unacceptable impact on user experience. In response to determining that thermal throttling the memory system would result in an unacceptable impact on user experience, the controller executes the command. In response to determining that thermal throttling the memory system would not result in an unacceptable impact on user experience, the controller thermal throttles the memory system. Other embodiments are provided.
    Type: Grant
    Filed: April 28, 2015
    Date of Patent: November 20, 2018
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Evgeny Postavilsky, Gadi Vishne, Judah Gamliel Hahn
  • Patent number: 10129101
    Abstract: An apparatus comprising a processor configured to obtain estimated processing requirements, estimated memory requirements, estimated storage requirements, and estimated network communication requirements for a plurality of data center (DC) tenants; determine a Minimum Resource Schedulable Unit (MRSU) for the tenants, the determined MRSU comprising a dynamically allocatable group of processor resources, processing memory resources, storage resources, and network resources comprised in at least one of a plurality of DC servers, wherein the MRSU is determined such that each DC tenant's estimated processing requirements, estimated memory requirements, estimated storage requirements, and estimated network communications requirements are met by allocation of a corresponding integer value of MRSUs; and allocate the corresponding integer value of MRSUs to each DC tenant as an MRSU allocation; and a transmitter coupled to the processor and configured to transmit the MRSU allocation to the DC servers for allocation to
    Type: Grant
    Filed: April 19, 2016
    Date of Patent: November 13, 2018
    Assignee: Futurewei Technologies, Inc.
    Inventors: Min Luo, David Estevez, Jiafeng Zhu
  • Patent number: 10126957
    Abstract: A semiconductor storage device includes memory cells, select transistors, memory strings, first and second blocks, word lines, and select gate lines. In the memory string, the current paths of plural memory cells are connected in series. When data are written in a first block, after a select gate line connected to the gate of a select transistor of one of the memory strings in the first block is selected, the data are sequentially written in the memory cells in the memory string connected to the selected select gate line. When data are written in the second block, after a word line connected to the control gates of memory cells of different memory strings in the second block is selected, the data are sequentially written in the memory cells of the different memory strings in the second block which have their control gates connected to the selected word line.
    Type: Grant
    Filed: October 3, 2017
    Date of Patent: November 13, 2018
    Assignee: Toshiba Memory Corporation
    Inventor: Hiroshi Maejima
  • Patent number: 10108685
    Abstract: Database storage systems provide replication capability that allows data of a source database storage system to be replicated to a target database storage system. Virtual databases can be provisioned from the target database system, thereby supporting remote provisioning of virtual databases. The virtual databases on the remote site can be used to perform various operations including read/write of data, refresh, rollback, and so on. Database objects may be deleted on the source database storage system while the corresponding data is used by other entities for example, virtual databases at the target database storage system. The database storage system verifies if an entity being deleted is in use by any other database infrastructure object of the database storage system. A placeholder object maintains the data corresponding to the deleted object. This provides the ability to create geographical distribution networks and support remote provisioning of virtual databases.
    Type: Grant
    Filed: July 9, 2014
    Date of Patent: October 23, 2018
    Assignee: Delphix Corp.
    Inventors: Matthew Benjamin Amdur, Eric Noah Schrock
  • Patent number: 10095584
    Abstract: The amount of data to be backed up and recovered is reduced when supply of power to a semiconductor device is stopped and restarted. A backup need determination circuit provided in the semiconductor device reads the kind of instruction decoded by a decoder and determines whether data needs to be backed up from a volatile register to a nonvolatile register. With a structure according to one embodiment of the present invention, it is possible to select necessary data from data used for operation in a logic circuit before the power supply is stopped and after the power supply is restarted. Data that is necessary after the power supply is restarted can be backed up from the volatile register to the nonvolatile register before the power supply is stopped. Data that is unnecessary is not backed up from the volatile register to the nonvolatile register before the power supply is stopped.
    Type: Grant
    Filed: April 23, 2014
    Date of Patent: October 9, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Seiichi Yoneda
  • Patent number: 10083418
    Abstract: Described in detail herein are systems and methods for detecting absent like physical objects at a first facility and replenishing the like physical objects from the second facility to the first facility. The system includes an autonomous robot device configured to detect absent like physical objects at a first facility and transmit an identifier associated with the like physical objects to a first computing system. The first computing system determines the need for the addition of the like physical objects in the first facility and transmits the data associated with the like physical objects to the second computing system. The second computing system corrects a perpetual inventory error associated with the like physical objects based on the received data and transmits instructions to an autonomous robot picker disposed at a second facility to replenish the like physical objects at the first facility.
    Type: Grant
    Filed: May 4, 2017
    Date of Patent: September 25, 2018
    Assignee: Walmart Apollo, LLC
    Inventors: Benjamin D. Enssle, David Blair Brightwell, Greg A. Bryan, Cristy Crane Brooks, Howard Gabbert