Abstract: A computer system with multiple security levels, the system comprising a high-power processing device (130), a low-power processing device (110), and an interface unit (120) comprising functions for moving classified information between the high-power device (130) and the low-power device (110) according to formal rules for confidentiality and/or integrity. Additional security aspects, e.g. availability, may readily be accommodated. A method for implementing multiple levels of security along a number of independent security axes on the system is also disclosed.

Abstract: Proactive management of a plurality of storage arrays in a multi-array system, including: comparing one or more conditions of a particular storage array to conditions of other storage arrays in the multi-array system; and generating an action recommendation based on the comparison, the action recommendation specifying one or more actions for improving the conditions of the particular storage array relative to the conditions of the other storage arrays.

Abstract: A memory system and method of operating the same is described, where the memory system is used to store data in a RAIDed manner. The stored data may be retrieved, including the parity data so that the stored data is recovered when the first of either the stored data without the parity data, or the stored data from all but one memory module and the parity data, has been received. The writing of data, for low write data loads, is managed such that only one of the memory modules of a RAID stripe is being written to, or erased, during a time interval.

Abstract: In one embodiment of the invention, a memory apparatus is disclosed. The memory apparatus includes a memory array, a block read/write controller, and a random access read memory controller. The memory array is block read/write accessible and random read accessible. The block read/write controller is coupled between the memory array and an external interconnect. The block read/write controller performs block read/write operations upon the memory array to access blocks of consecutive memory locations therein. The random access read memory controller is coupled between the memory array and the external interconnect in parallel with the block read/write access controller. The random access read memory controller performs random read memory operations upon the memory array to access random memory locations therein.

Abstract: Methods, systems, and apparatus, for selecting one or more native application deep links from search results and instantiating, for each native application deep link that is selected, a background instance of the native application to which the native application deep link corresponds; determining, in response to an occurrence of a background unload event, background instances of the native applications instantiated from the native application deep links and that were not brought to the foreground prior to the occurrence of the background unload event; and terminating each of the background instances of the native applications instantiated that were not brought to the foreground prior to the occurrence of the background unload event.

Abstract: Example implementations relate to obtaining information about and indicating a state of a storage device. In example implementations, an indication that a storage device is rebuilding address mappings may be received, and how much progress has been made in the rebuilding may be determined. A representation of the progress made in the rebuilding may be displayed.

Abstract: A memory system and method for differential thermal throttling are disclosed. In one embodiment, a memory system is provided comprising a memory and a controller. The controller is configured to receive a command to perform an operation in the memory and analyze the command to determine whether thermal throttling the memory system would result in an unacceptable impact on user experience. In response to determining that thermal throttling the memory system would result in an unacceptable impact on user experience, the controller executes the command. In response to determining that thermal throttling the memory system would not result in an unacceptable impact on user experience, the controller thermal throttles the memory system. Other embodiments are provided.

Abstract: A circuit arrangement and method for securing an integrated electronic circuit against scans of an address space, wherein the circuit arrangement has at least one master unit and at least one slave unit interconnected via a bus system for access of the master unit to the slave unit, and addresses are used from an address space that is allocated and used in accordance with functionalities of the integrated electronic circuit, where a defense slave unit is connected to the bus system, access to unused address regions of the address space are forwarded to the defense slave unit, the access is analyzed and evaluated by the defense slave unit and depending on an analysis result and the respective access type, defensive measures are triggered, such that address space scans are interrupted or a potential scan result is rendered useless in a simple manner.

Abstract: An apparatus comprising a processor configured to obtain estimated processing requirements, estimated memory requirements, estimated storage requirements, and estimated network communication requirements for a plurality of data center (DC) tenants; determine a Minimum Resource Schedulable Unit (MRSU) for the tenants, the determined MRSU comprising a dynamically allocatable group of processor resources, processing memory resources, storage resources, and network resources comprised in at least one of a plurality of DC servers, wherein the MRSU is determined such that each DC tenant's estimated processing requirements, estimated memory requirements, estimated storage requirements, and estimated network communications requirements are met by allocation of a corresponding integer value of MRSUs; and allocate the corresponding integer value of MRSUs to each DC tenant as an MRSU allocation; and a transmitter coupled to the processor and configured to transmit the MRSU allocation to the DC servers for allocation to

Abstract: A semiconductor storage device includes memory cells, select transistors, memory strings, first and second blocks, word lines, and select gate lines. In the memory string, the current paths of plural memory cells are connected in series. When data are written in a first block, after a select gate line connected to the gate of a select transistor of one of the memory strings in the first block is selected, the data are sequentially written in the memory cells in the memory string connected to the selected select gate line. When data are written in the second block, after a word line connected to the control gates of memory cells of different memory strings in the second block is selected, the data are sequentially written in the memory cells of the different memory strings in the second block which have their control gates connected to the selected word line.

Abstract: Database storage systems provide replication capability that allows data of a source database storage system to be replicated to a target database storage system. Virtual databases can be provisioned from the target database system, thereby supporting remote provisioning of virtual databases. The virtual databases on the remote site can be used to perform various operations including read/write of data, refresh, rollback, and so on. Database objects may be deleted on the source database storage system while the corresponding data is used by other entities for example, virtual databases at the target database storage system. The database storage system verifies if an entity being deleted is in use by any other database infrastructure object of the database storage system. A placeholder object maintains the data corresponding to the deleted object. This provides the ability to create geographical distribution networks and support remote provisioning of virtual databases.

Abstract: The amount of data to be backed up and recovered is reduced when supply of power to a semiconductor device is stopped and restarted. A backup need determination circuit provided in the semiconductor device reads the kind of instruction decoded by a decoder and determines whether data needs to be backed up from a volatile register to a nonvolatile register. With a structure according to one embodiment of the present invention, it is possible to select necessary data from data used for operation in a logic circuit before the power supply is stopped and after the power supply is restarted. Data that is necessary after the power supply is restarted can be backed up from the volatile register to the nonvolatile register before the power supply is stopped. Data that is unnecessary is not backed up from the volatile register to the nonvolatile register before the power supply is stopped.

Abstract: Described in detail herein are systems and methods for detecting absent like physical objects at a first facility and replenishing the like physical objects from the second facility to the first facility. The system includes an autonomous robot device configured to detect absent like physical objects at a first facility and transmit an identifier associated with the like physical objects to a first computing system. The first computing system determines the need for the addition of the like physical objects in the first facility and transmits the data associated with the like physical objects to the second computing system. The second computing system corrects a perpetual inventory error associated with the like physical objects based on the received data and transmits instructions to an autonomous robot picker disposed at a second facility to replenish the like physical objects at the first facility.

Abstract: Mechanisms are provided, in a processor, for executing instructions that are younger than a previously dispatched synchronization (sync) instruction is provided. An instruction sequencer unit of the processor dispatches a sync instruction. The sync instruction is sent to a nest of one or more devices outside of the processor. The instruction sequencer unit dispatches a subsequent instruction after dispatching the sync instruction. The dispatching of the subsequent instruction after dispatching the sync instruction is performed prior to receiving a sync acknowledgement response from the nest. The instruction sequencer unit performs a completion of the subsequent instruction based on whether completion of the subsequent instruction is dependent upon receiving the sync acknowledgement from the nest and completion of the sync instruction.

Abstract: This invention provides a cache system and method based on instruction read buffer (IRB). When applied to the field of processor, it is capable of filling instructions to the instruction read buffer which can be directly accessed by processor core and the processor core outputs instruction to the processor core for execution autonomously and achieve a high cache hit rate.

Abstract: A method obtains a first data item signature for a first data item, the first data item signature comprising an association between a plurality of synch points in the first data item and a corresponding plurality of block signatures. The process attempts to find one of the synch points in a second data item; and, if such a synch point is found, then a block signature of a corresponding block of bits in the second data item is determined. The process ascertains whether the synch point and corresponding block signature from the second data item correspond to a synch point and block signature in the first data item. If a predetermined number of synch points and corresponding block signatures match, the first and second data items are considered to match. In response to said determining, one or more actions associated with the first data item are performed.

Abstract: Systems and methods are disclosed for error correction control (ECC) for a memory device comprising a data portion and an ECC portion, the memory device coupled to a system on a chip (SoC). The SoC includes an ECC cache. On receipt of a request to write a line of data to the memory, a determination is made if the data is compressible. If so, the data line is compressed. ECC bits are generated for the compressed or uncompressed data line. A determination is made if an ECC cache line is associated with the received data line. If the data line is compressible, the ECC bits are appended to the compressed data line and the appended data line is stored in the data portion of the memory. Otherwise, the ECC bits are stored in the ECC cache and the data line is stored in the data portion of the memory.

Abstract: Systems and methods for providing dynamic topology information to virtual machines hosted by a multi-processor computer system supporting non-uniform memory access (NUMA). An example method may comprise assigning, by a hypervisor executing on a computer system, unique identifiers to a plurality of memory blocks residing on a plurality of physical nodes; determining that a memory block has been moved from a first physical node to a second physical node; determining memory access latency values to the second physical node by a plurality of virtual processors of the computer system; and updating, using a unique identifier of the memory block, a data structure storing memory access latency information, with the memory access latency values for the memory block.

Abstract: A method, system and computer program product for sharing class data among virtual machine applications running on one or more guests in a virtualized environment. A control program in a virtual operating system is used to manage the user portions of the virtual operating system, each commonly referred to as a guest. A guest operating system runs on each guest and applications can run on each guest operating system. A memory management facility manages shared memory which includes a class cache configured to store class data. The shared memory may be mounted onto each guest using a cluster file system or accessed via an API interface thereby allowing the class cache to be shared across the guests. By sharing the class cache among the guests, multiple copies of the same class data are no longer necessary thereby optimally using the physical memory on the host.

Abstract: According to one embodiment, an information processing apparatus includes a host and a memory system. The host includes a main memory. The memory system includes a memory access unit and an interface unit. The memory access unit converts a first request into transmission information. The first request is a request for data transfer toward a memory region as a part of the main memory. The interface unit transmits transmission information according to an instruction from the memory access unit.

Abstract: A memory system includes a plurality of memory devices and a memory controller configured to control the memory devices. The memory controller receives a read request having a variable size, generates at least one memory request having a fixed size in response to the read request, and transmits the at least one memory request to at least one of the memory devices.

Abstract: Each of a plurality of Worker processes are allowed to perform any and all of the following tasks involving logged work items: (1) reading a subset of the work items from a log; (2) sequentially ordering work items for corresponding data objects; (3) applying a sequentially ordered set of work items to a corresponding data object; and (4) transmitting a subset of work items to a Worker process running on another database server in a cluster, if necessary. These tasks can be performed concurrently, at will, and as available, by the Worker processes. An improved checkpointing technique eliminates the need for the Worker processes to get to a synchronization point and stop. Instead, a Coordinator process examines the current state of progress of the Worker processes and computes a past point in the sequence of work items at which all work items before that point have been completely processed, and records this point as the checkpoint.

Abstract: An apparatus for implementing an enhanced-write-bandwidth caching stream includes a memory that stores machine instructions and a processor that executes the machine instructions. The apparatus receives a first host write stream and a second host write stream that comprises latency-sensitive host write requests. The apparatus also subjects the first host write stream to host-write throttling, and exempts the second host write stream from host-write throttling. The apparatus further requires that the second host write stream invalidate logical blocks in an order corresponding to a previous order in which the respective logical blocks were previously programmed.

Abstract: Various methods and systems are provided to capture a unique product code, such as QR code, on a mobile device, process the information contained in the code, provide the user with options of making a purchase, including purchasing a plurality of selected products from different captured codes, and processing the payment via the user's mobile device.

Abstract: A database system may maintain a plurality of log records at a distributed storage system. Each of the plurality of log records may be associated with a respective change to a data page. The plurality of log records may be transformed (e.g., cropped, prune, reduce, fused, deleted, merged, added, etc.).

Abstract: Methods, systems and apparatus for a distributed data environment in which data can be seamlessly accessed from remote computing devices are disclosed. For a given user having multiple computing devices, a personal distributed data bank can be formed from data storage capacities resident at the multiple computing device. The given user can access data on any of the multiple computing devices without knowing on which of the multiple computing devices the data resides. In one embodiment, an index for the user's data within the personal distributed data bank can be provided to facilitate searching, browsing and accessing of user data by the given user.

Abstract: Mechanisms are provided, in a storage system controller of a storage system, for writing data to a storage medium. The storage system controller receives a write request to write a block of data to the storage medium. The write request does not specify a location on the storage medium to which to write the block of data. The storage system controller determines a current position of a write mechanism of the storage system relative to the storage medium and determines a location on the storage medium to write the block of data based on the current position of the write mechanism. The storage system controller sends a notification to a host system identifying the location of the block of data on the storage medium as determined by the storage system controller. The writing mechanism writes the block of data to the determined location on the storage medium.

Abstract: Local checkpointing using a multi-level call is described herein. An example method includes storing a first datum in a first level of a multi-level cell. A second datum is stored in a second level of the multi-level cell, the second datum representing a checkpoint of the first datum. The first datum is copied from the first level to the second level of the multi-level cell to create the checkpoint.

Abstract: Methods and systems are presented for allocating CPU cycles among processes in a storage system. One method includes operations for maintaining segments in a first memory, each segment including blocks, and for maintaining a block temperature for each block in a second memory. The first memory is a read-cache where one segment is written at a time, and each block is readable from the first memory without reading the corresponding complete segment. The block temperature is based on the frequency of access to the respective block, and a segment temperature is based on the block temperature of its blocks. Additionally, the segment with the lowest segment temperature is selected for eviction from the second memory, and blocks in the selected segment with a block temperature greater than a threshold temperature are identified. The selected segment is evicted, and a segment with the identified blocks is written to the first memory.

Abstract: The disclosed embodiments included a system, apparatus, method, and computer program product for optimizing the storage of data based at least in part on cost and service levels utilizing a cloud-based virtual storage fabric. Those embodiments are configured to compile operational information for service offerings that provide data storage at different storage locations, determine the costs of migrating that data to and storing that data at each of those storage locations utilizing the operational information, designate at which storage location each datum is to be stored based in part on those costs, and designate at least one datum for migration from one of the storage locations to another if the cost of storing that datum at that storage location is determined to be greater than the costs of migrating and storing that datum at the other storage location.

Abstract: Embodiments for managing data in a virtual tape storage environment, by a processor device, are provided. A management system on a host is used to define volume expiration attributes for virtual tape volumes and the volume expiration attributes are forwarded to a virtual tape server. Return-to-scratch processing is performed on the virtual tape volumes directly on the virtual tape server by using the volume expiration attributes to compile candidate volumes without querying the host, where the candidate volumes are expired and converted to scratch by the virtual tape server.

Abstract: Embodiments for managing data in a virtual tape storage environment, by a processor device, are provided. A management system on a host is used to define volume expiration attributes for virtual tape volumes and the volume expiration attributes are forwarded to a virtual tape server. Return-to-scratch processing is performed on the virtual tape volumes directly on the virtual tape server by using the volume expiration attributes to compile candidate volumes without querying the host, where the candidate volumes are expired and converted to scratch by the virtual tape server.

Abstract: A reconfigurable cache architecture is provided. In processor design, as the density of on-chip components increases, a quantity and complexity of processing cores will increase as well. In order to take advantage of increased processing capabilities, many applications will take advantage of instruction level parallelism. The reconfigurable cache architecture provides a cache memory that in capable of being configured in a private mode and a fused mode for an associated multi-core processor. In the fused mode, individual cores of the multi-core processor can write and read data from certain cache banks of the cache memory with greater control over address routing. The cache architecture further includes control and configurability of the memory size and associativity of the cache memory itself.

Abstract: In one embodiment, a system includes a cache storage device and a processor and logic integrated with and/or executable by the processor. The logic is configured to receive a plurality of access requests for data in the cache storage device, each request being directed to data in a common cache block descriptor (CBD). The CBD stores metadata corresponding to a storage location of the data in the cache storage device. The logic is also configured to update a request queue to reflect each access request from the plurality of access requests in an order in which individual access requests were received. Moreover, the logic is configured to delay at least some overlapping access requests.

Abstract: Techniques for parallel data collection and recovery for a failing virtual processing system are disclosed. According to aspects of the present disclosure, an example method includes: detecting that the virtual processing system experiences an irreparable error; saving, by each of a plurality of processors of the physical processing system, a corresponding context and data stored in an allocated portion of a memory of the physical processing system to a data store; selecting one of the plurality of processors as a recovery processor; initializing, by the recovery processor, a pre-determined reserved portion of the memory; initiating, by the recovery processor, a new instance of the virtual processing system on the reserved portion of the memory while each remaining processor of the plurality of processors continues the saving; and dynamically adding each remaining processor of the plurality of processors to the new instance of the virtual processing system.

Abstract: A hybrid module includes one or more memory modules, each of which includes one or more memory devices and a memory controller, one or more storage modules, each of which includes one or more storage devices and a storage controller. A host interface of the hybrid module includes a main controller and provides an interface with the memory controller and the storage controller. A transaction-based memory interface provides an interface between the main controller and a host memory controller.

Abstract: A memory system has a non-volatile memory of which access speed is electrically controlled, a control circuitry that selects a first region which is a portion of a memory region of the non-volatile memory, and a boost circuit that adjusts an access speed of the first region to be higher than an access speed of a second region different from the first region in the memory region.

Abstract: A versioned records management computing system that uses a restart era in order to promote rapid recovery. A persistent store includes a multi-versioned record collection. The records are also associated with a restart era that corresponds to the era of operation of the computing system after a restart. Upon a recovery, the current restart era changes. An object collection media has an object collection that conforms to an object model such that the object model is used to operate upon the records. The object collection media is operable such that the object collection is durable so as to survive restarts of the system to thereby allow for accelerated recovery.

Abstract: A memory manager reduces the impact of memory clean-up operations on server performance. The memory manager monitors local memory usage and other resource usage by the server, such as processor, storage, and network usage. When moderately high memory usage is detected, the memory manager performs memory clean-up operations during relatively low processor, storage, and network usage to reduce the impact of the clean-up operations on server performance. When excessively high memory usage is detected, the memory manager more aggressively cleans-up local memory independently of processor, storage, and network usage.

Abstract: A dispersed storage system includes a plurality of storage units that each include a partial rebuild grid module. The partial rebuild grid module includes partial rebuilding functionality to reconstruct one of a plurality of encoded data slices wherein the plurality of encoded data slices are generated from a data segment based on an error encoding dispersal function. In the partial rebuilding process, a data slice is rebuilt by combining in any order slice partials generated from at least a threshold number T of the plurality of data slices.

Abstract: A method and system of compiling and linking source stream programs for efficient use of multi-node devices. The system includes a compiler, a linker, a loader and a runtime component. The process converts a source code stream program to a compiled object code that is used with a programmable node based computing device having a plurality of processing nodes coupled to each other. The programming modules include stream statements for input values and output values in the form of sources and destinations for at least one of the plurality of processing nodes and stream statements that determine the streaming flow of values for the at least one of the plurality of processing nodes. The compiler converts the source code stream based program to object modules, object module instances and executables. The linker matches the object module instances to at least one of the multiple cores.

Abstract: A parallel execution runtime prevents stack overflow by maintaining an inline counter for each thread executing tasks of a process. Each time that the runtime determines that inline execution of a task is desired on a thread, the runtime determines whether the inline counter for the corresponding thread indicates that stack overflow may occur. If not, the runtime increments the inline counter for the thread and allows the task to be executed inline. If the inline counter indicates a risk of stack overflow, then the runtime performs additional one or more checks using a previous stack pointer of the stack (i.e., a lowest known safe watermark), the current stack pointer, and memory boundaries of the stack. If the risk of stack overflow remains after all checks have been performed, the runtime prevents inline execution of the task.

Abstract: There is provided with an information processing apparatus and a method of controlling the same. The apparatus sets a naming rule for an image file and determines whether or not the set naming rule satisfies a predetermined condition. If it is determined that the naming rule does not satisfy the predetermined condition, the information processing apparatus warns a user. On the other hand, if it is determined that the naming rule satisfies the predetermined condition, the information processing apparatus generates a file name of the image file in accordance with the set naming rule, and stores the image file with the file name.

Abstract: A test selection method includes: generating, by a computer, relationship information that includes information indicating whether there is a relationship between each pair of one of a plurality of first tests and one of a plurality of second tests, and information on the number of relationships that indicates the number of pairs having the relationship from among a plurality of the pairs, by use of a result of performing the plurality of first tests and a result of performing the plurality of second tests; and when a specific test included in the plurality of first tests is designated, extracting by the computer, from among the plurality of second tests, a related test that relates to the specific test, on the basis of the relationship information and the information on the number of relationships.

Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for file transmission. In one aspect, a system includes at least one machine control system, having access to a first data storage; at least one service computer, having access to a second data storage; and a central computer having at least one virtual machine. The machine control system is connectable to the virtual machine via a first communication connection in a manner that files between the first data storage and a data storage, to which the virtual machine has access, are transmissible. The service computer is connectable to the virtual machine via a second communication connection, in a manner that the virtual machine can access the second data storage and can store there files of a transmission via the first communication connection or can read files for a transmission via the first communication connection.

Abstract: A hypervisor identifies a set of pages to be polled for updates made by a guest operating system, each page having a write protection attribute that causes an exit to a hypervisor upon a guest operating system attempt to update a corresponding page. The hypervisor modifies the write protection attribute for each page of the set of pages to avoid the exit to the hypervisor upon the guest attempt to update the corresponding page. The hypervisor then initiates polling of the set of pages to detect updated pages, wherein detecting updated pages comprises detecting a status indicator set to a first value. The hypervisor then logs a modification of each updated page, and resets the status indicator to a second value to indicate that the modification to each updated page has been logged.

Abstract: A system and method are provided including one or more processors and one or more computer-readable media coupled to the one or more processors. The one or more computer-readable media storing instructions that, when executed by the one or more processors, cause the one or more processors to perform operation including performing, at an image processing device, a login process wherein access to one or more resources on the image processing device is granted based on a credential associated with a user and receiving a request to perform a scan and send process is received at the image processing device, the request comprising instructions for scanning a physical document and sending an electronic document representing the scanned physical document to a destination system. The scan process is initiated and a data object including data representing job data and the credential associated with the use is generated.

Abstract: A processor determines that processing of a thread is suspended due to limited availability of a processing resource. The processor supports execution of the plurality of threads in parallel. The processor obtains a lock on a second processing resource that is substitutable as a resource during processing of the first thread. The second processing resource is included as part of a component that is external to the processor. The component supports a number of threads that is less than the plurality of threads. The processing of the thread is suspended until the lock is available. The processor processes the first thread using the second processing resource. The processor includes a shared register to support mapping a portion of the plurality of threads to the component. The portion of the plurality of threads is equal to, at most, the number of threads supported by component.

Abstract: A storage device is provided. The storage device includes storage clusters, and a controller. The controller receives a command and an address from an external host device, selects a storage cluster according to the received address, and transmits the received command and the received address to the selected storage cluster. The controller controls the storage clusters as normal storage clusters and slow storage clusters according to a temperature of a zone to which the storage clusters belong.

Abstract: Systems, methods, and computer program products are provided for providing context through a scripting-type programming language to data included in a SIP message. The method includes defining one or more contexts through a scripting-type computer programming language. The one or more contexts reference a particular pre-defined portion of a SIP message and are provided by the scripting-type computer programming language. A series of SIP messages may then be received, where each SIP message in the series belongs to the same SIP message flow. After a particular SIP message in the series is received, the message is parsed to identify whether it includes any portion of data that can be referenced via one or more contexts. Any particular portion of data that can be referenced via a context is associated with a respective context such that the respective portion of data can be referenced by the context.