Abstract: A method for operating a brushless electric motor, the windings being energized by an inverter with the aid of six switches. A detection unit for detecting defective switches, a unit for measuring voltage at the outputs of the inverter, and a microcontroller for controlling the switch and for generating a pulse width modulated voltage supply for the windings are provided. A short-circuited switch causes a torque in the electric motor opposite the actuating direction of the electric motor. The method proposes that after detecting a short-circuited switch, the windings (U. V. W) are energized to generate a motor torque that is, on the whole, positive. An actuating period of the electric motor is divided into a plurality of sectors, wherein, in accordance with the defective switch, individual sectors are deactivated for the actuation of the windings (U, V, W), while other sectors are used to actuate the windings (V, W).

Abstract: A semiconductor device includes an internal circuit, a power supply control circuit which controls supply of a power supply to the internal circuit upon receipt of a first control signal, and a control signal generation circuit which outputs the first control signal upon receipt of a second control signal. The control signal generation circuit does not deactivate the first control signal when an inactive period of the second control signal is equal to or less than a first period and deactivates the first control signal when the inactive period of the second control signal is more than the first period.

Abstract: An active matrix panel includes a gate line connected to control electrodes of a plurality of transistors; and a drive circuit supplying the gate line with a conducting voltage and a non-conducting voltage. The drive circuit includes a shift register including a plurality of shift register unit circuits connected to each other, and a demultiplexer including a plurality of demultiplexer unit circuits into which output signals of the shift register unit circuits are input. The demultiplexer unit circuit includes a first transistor for supplying the gate line with the conducting voltage, and a second transistor for supplying the gate line with the non-conducting voltage. The first transistor is changed from a non-conducting state into a conducting state when the second transistor is in the conducting state.

Abstract: A digital power gating system for performing power gating to reduce a voltage of a gated supply bus to a state retention voltage level that reduces leakage current while retaining a digital state of a functional circuit. The power gating system includes gating devices and a power gating control system. Each gating device has current terminals coupled between a global supply bus and the gated supply bus, and a control terminal controlled by a bit of a digital control value. The power gating control system successively adjusts the digital control value to reduce a voltage of the gated supply bus to the state retention voltage level. Adjustment gain and/or adjustment periods may be changed, such as when the digital control value reaches certain values or when the gated supply reaches certain voltage levels. Various parameters are programmable to adjust for particular configurations or to achieve desired operation.

Abstract: A design method is executed by a computer. The design method includes grouping logical modules in each of power domains arranged on a chip; provisionally arranging regular cells in each of logical module groups formed by the grouping; and arranging power switches around each of the logical module groups.

Abstract: A semiconductor device outputs a signal to control a gate potential a switching device. The semiconductor device includes a first signal output terminal, and is capable of receiving or internally creating a reference signal, which varies between a first potential and a second potential. The semiconductor device can switch between first and second operations. The first operation outputs to the first signal output terminal a signal that is at a third potential when the reference signal is at the first potential, and that is at a fourth potential higher than the third potential when the reference signal is at the second potential. The second operation outputs to the first signal output terminal a signal that is at the fourth potential when the reference signal is at the first potential, and that is at the third potential when the reference signal is at the second potential.

Abstract: An RF pulse signal generation switching circuit for controlling an output of a power FET for amplifying a high frequency signal to generate an RF pulse signal that is the high frequency signal pulse formed into a pulse-wave shape is provided. The circuit includes first and third n-type FETs of which gates are inputted with a control pulse that supplies a rise timing and a fall timing of a pulse, and a second n-type FET of which a gate is connected with a drain of the first FET. A source of the first FET and a source of the third FET are grounded, respectively. The drain of the first FET is applied with a first drive voltage via a resistor. A drain of the second FET is applied with a second drive voltage. A source of the second FET is connected with a drain of the third FET and the connection point therebetween is connected with the power FET. A capacitor is connected between the connection point and an end of the resistor from which the first drive voltage is applied.

Abstract: An apparatus includes a first die having a first bus, a second die having a second bus stacked on the first die, a plurality of through silicon vias connecting the first bus to the second bus, and first control logic for sending data to identified ones of the plurality of through silicon vias. Also, optionally, second control logic for determining a first set of the plurality of through silicon vias that are nonfunctional, wherein the second control logic is configured to send information to the first control logic identifying the first set of the plurality of through silicon vias or identifying a second set of through silicon vias that are functional. Also a method of sending signals through a plurality of through silicon vias.

Abstract: Embodiments of the invention provide IGBT circuit modules with increased efficiencies. These efficiencies can be realized in a number of ways. In some embodiments, the gate resistance and/or voltage can be minimized. In some embodiments, the IGBT circuit module can be switched using an isolated receiver such as a fiber optic receiver. In some embodiments, a single driver can drive a single IGBT. And in some embodiments, a current bypass circuit can be included. Various other embodiments of the invention are disclosed.

Abstract: An integrated circuit including a global supply bus, a gated supply bus, and a digital power gating system with controlled resume. The digital power gating system includes gating devices and a power gating control system. Each gating device has a pair of current terminals coupled between the global supply bus and the gated supply bus and each has a control terminal. The power gating control system controls a digital control value which controls activation of the gating devices. The power gating control system is configured to successively adjust the digital control value to increase a voltage of the gated supply bus from a reduced voltage level to a normal operating voltage level in response to a resume indication. The reduced voltage level may be a state retention level or full power gating. Successive adjustment may be with constant or adjusted gain using a constant clock or a dynamically adjusted clock.

Abstract: Provided is a switching apparatus that switches a connection state between two terminals, comprising a switch that switches the connection state between the two terminals according to a control voltage supplied thereto; a driving section that provides the switch with the control voltage corresponding to a control signal supplied thereto; and a changing section that changes the control voltage output from the driving section, according to a designated switching time. The changing section may change power supplied as a power supply to the driving section, according to the designated switching time. The changing section may change the control voltage output from the driving section prior to switching of the switch.

Abstract: A multi-chip package having a plurality of slice chips coupled through a through-via, at least one slice chip may include an input unit suitable for receiving a slice activation signal, and outputting the slice activation signal to the through-via in response to a slice identification corresponding to the slice chip, a first output unit suitable for outputting the activation signal transferred through the through-via to an internal circuit of the slice chip in response to the corresponding slice identification, and a second output unit suitable for selectively outputting the activation signal transferred through the through-via to the internal circuit of the slice chip in a predetermined activation mode for the multi-chip package.

Abstract: An apparatus includes an integrated circuit with a clock network in an array of circuit blocks. The clock network includes routing tracks, distribution spines, and clock leaves. The routing tracks and the distribution spines are bidirectional.

Abstract: The invention relates to a receiving circuit for transmission through interconnections used for sending a plurality of electrical signals. Each of the output signals of the receiving circuit produced by the receiving circuit of the invention is delivered by an output of a combining circuit having 4 inputs and 4 outputs. Each signal terminal of the receiving circuit is connected to a first input terminal of a differential circuit, the differential circuit also having a second input terminal and a single output terminal. The common terminal of the receiving circuit is connected to the second input terminal of each of the differential circuits. Each input of the combining circuit is coupled to the output terminal of one of the differential circuits. Each of the output signals of the receiving circuit is a linear combination of the voltages between one of the signal terminals and the common terminal.

Abstract: A gate driving device includes a gate driving unit, a first control unit, a second control unit and a switch unit. The first control unit includes an input terminal receiving a first output signal and a first clock input terminal receiving a first clock signal. The second control unit includes an input terminal receiving a second output signal and a first clock input terminal receiving a second clock signal. The switch unit, the first control unit and the second control unit are coupled to a carryout signal output node for generating a carryout signal at the carryout signal output node which indicates whether the gate driving unit is functioning correctly. The first output signal and the second output signal of the gate driving unit are respectively one signal generated by any two different stages of shift register in the gate driving unit.

Abstract: A readout device is adapted for dual-band sensing, and includes an amplifier, two direct injection (DI) readout circuits to be respectively connected to two sensors, and a switching module. Through operation of the switching module, one of the DI readout circuits can be electrically connected to the amplifier, and cooperate with the other DI readout circuit to achieve a dual-band sensing feature.

Abstract: A method and apparatus for controlling a device in electronic equipment having a plurality of devices are provided. The apparatus includes a power supply for supplying power, a slave device including a driving circuit operated according to the supplied power for transmitting and receiving data to and from another device, a switching circuit for connecting the driving circuit to a ground terminal when the switching circuit is turned-on and for opening the driving circuit from the ground terminal when the switching circuit is turned-off, and a host device for transmitting a control signal for turning-on the switching circuit when driving the slave device and for turning-off the switching circuit when not driving the slave device. When the device is not driven, the switching circuit may open a driving circuit from a ground terminal, thereby cutting-off leakage of an electric current through the device.

Abstract: A multi-chip package having a plurality of slice chips coupled through a through-via, at least one slice chip may include an input unit suitable for receiving a slice activation signal, and outputting the slice activation signal to the through-via in response to a slice identification corresponding to the slice chip, a first output unit suitable for outputting the activation signal transferred through the through-via to an internal circuit of the slice chip in response to the corresponding slice identification, and a second output unit suitable for selectively outputting the activation signal transferred through the through-via to the internal circuit of the slice chip in a predetermined activation mode for the multi-chip package.

Abstract: A High Voltage switch configuration having an input terminal which receives an input signal and an output terminal which issues an output signal to a load. The High Voltage switch configuration comprises at least a first and a second diode, being placed in antiseries between said input and output terminals and having a pair of corresponding terminals in common, in correspondence of a first internal circuit node.

Abstract: Electrolyte gating with ionic liquids is a powerful tool for inducing conducting phases in correlated insulators. An archetypal correlated material is VO2 which is insulating only at temperatures below a characteristic phase transition temperature. We show that electrolyte gating of epitaxial thin films of VO2 suppresses the metal-to-insulator transition and stabilizes the metallic phase to temperatures below 5 K even after the ionic liquid is completely removed. We provide compelling evidence that, rather than electrostatically induced carriers, electrolyte gating of VO2 leads to the electric field induced creation of oxygen vacancies, and the consequent migration of oxygen from the oxide film into the ionic liquid.

Abstract: A low voltage isolation circuit is coupled between an input terminal for receiving a high voltage signal and an output terminal for transmitting the high voltage signal to a load. The isolation circuit includes a driving block; having a first driving transistor coupled between a first voltage reference and an intermediate node and a second driving transistor coupled between the intermediate node and a second voltage reference; an isolation block connected between the input and output terminals and, through a protection block to the intermediate node. The protection block includes first and second protection transistors (MD1, coupled in anti-series to each other and having control terminals receiving complementary protection driving signals. The isolation block includes a voltage limiter block, a diode block and a control transistor connected across the diode block between the input and output terminals and having a control terminal connected to the intermediate node through the protection block.

Abstract: A control system for semiconductor switches, the control system (CTRL) being configured to calculate an estimate of the instantaneous dissipation power of at least one semiconductor component unit (SU1) during an analysis period, whereby the at least one semiconductor component unit (SU1) includes at least one semiconductor switch (S1), and the instantaneous dissipation power includes the conduction losses and switching losses of the at least one semiconductor component unit (SU1).

Abstract: An integrated circuit device may include a plurality of external connections, any one of the connections providing both a power voltage path for the integrated circuit (IC) as well as an information signal path for the IC. At least one switch may be coupled to provide a power supply voltage to one of the external connections.

Abstract: An electronic USB or similar device 101 with a CMOS audio output stage 105 for driving, in a first mode, e.g., a headset via a port commonly used also in a second mode by a digital data transmission stage 103 for digital data and supply, the audio output stage P-channel transistor MP being switchably back-gate biased by a bias circuit 107 according to the operating mode to achieve high-voltage tolerance.

Abstract: An electronic device connectable with an electronic accessory according to the present disclosure is provided. The electronic device includes a jack, a data signal transceiving unit, a measuring unit, a switching unit and a processing unit. The jack is adapted to receive an insertion of a plug of the electronic accessory and has a first contact terminal adapted to be in contact with a first contact of the plug. The data signal transceiving unit is adapted to transmit to or receive from the electronic accessory a data signal through the first contact terminal of the jack. The measuring unit is adapted to measure a parameter resulted from the contact of the first contact terminal of the jack with the first contact of the plug through the first contact terminal when the plug is inserted into the jack. The switching unit is adapted to selectively connect the first contact terminal of the jack electrically to the data signal transceiving unit or the measuring unit.

Abstract: There is provided a high frequency switch capable of suppressing deterioration in distortion characteristics. The high frequency switch includes: a common port outputting a transmission signal to an antenna; a plurality of transmission ports each having the transmission signal input thereto; and a plurality of switching units each connected between the plurality of transmission ports and the common port to conduct or block the transmission signal from each of the transmission ports to the common port, wherein each of the switching units has one or more metal oxide semiconductor field effect transistors (MOSFETs) formed on a silicon substrate, and a capacitor connected between a body terminal of a MOSFET connected to the common port among the MOSFETs and a terminal of the MOSFET connected to the common port.

Abstract: A data control circuit includes an output stage circuit, a switch circuit, and an impedance module. The output stage circuit outputs a data signal. An input terminal of the switch circuit is coupled to an output terminal of the output stage circuit, and an output terminal of the switch circuit is coupled to a post-stage circuit. According to a control of a control signal, the switch circuit determines whether to transmit the data signal of the output stage circuit to the post-stage circuit. The impedance module is configured in the output stage circuit, configured between the output stage circuit and the switch circuit, or configured in the switch circuit. Here, the impedance module reduces noise flowing from the switch circuit to the output stage circuit.

Abstract: An integrated circuit, in accordance with embodiments of the present technology, includes a plurality of engines, a plurality of engine level power gating (ELPG) controllers, and a power gating arbiter for implementing engine level power gating arbitration techniques. The power gating arbiter may receive requests from one or more ELPG controllers to turn on their respective engines or portions therein. The power gating arbiter prioritizes the request and sends an acknowledgment to a given ELPG controller to turn on or off its corresponding engine according to the prioritized predetermined order. After receiving the acknowledgement, the given ELPG controller turns on or off its corresponding engine and returns an indication to the power gating arbiter that the corresponding engine is turned on or off. The process may be iteratively repeated for each received request after receiving the indication from the previously serviced ELPG controller that its corresponding engine is turned on or off.

Abstract: A method for controlling a multi-phase switching converter with a plurality of switching circuits, including: sensing the output current of the switching circuit and generating a current sensing signal; generating a digital phase current signal based on the current sensing signal; subtracting the digital phase current signal from a current reference signal and generating a current error signal; proportionally integrating the current error signal and generating a first bias signal; conducting a sigma-delta modulation of the first bias signal and generating a second bias signal, wherein the first bias signal is a P-bit digital signal, the second bias signal is a Q-bit digital signal, and P is larger than Q; and adjusting a control signal controlling the switching circuit based on the second bias signal.

Abstract: A gate drive circuit includes a first gate terminal, a second gate terminal, and a driver circuit including an input and including an output coupled to the first gate terminal. The driver circuit is configured to provide a drive signal to the first gate terminal to control a first switch to selectively couple a first current path to a first wire pair of a network port. The gate drive circuit further includes a switch including a first terminal coupled to the output of the driver circuit, a second terminal coupled to the second gate terminal, and a control terminal responsive to a switch control signal to selectively couple the output of the driver circuit to the second gate terminal to control a second switch to selectively couple a second current path to a second wire pair of the network port.

Abstract: A circuit includes first to third nodes, resistors with different resistance, capacitors with different capacitance, first switches corresponding to the same number of resistors, second switches corresponding to the same number of capacitors, and a third switch. A first terminal of each resistor is connected to the first node. A second terminal of each resistor is connected to a first terminal of a corresponding one first switch, a second terminal of each first switch is connected to the second node. A first terminal of the third switch is connected to the second terminal of each first switch. A second terminal of the third switch is connected to a first terminal of each capacitor. A second terminal of each capacitor is connected to a first terminal of a corresponding one second switch. A second terminal of each second switch is connected to the third node.

Abstract: A rush-in current controller includes a clock module connected to provide a delayed sleep control signal based on counting a preset number of clock cycles corresponding to an input sleep control signal. Additionally, the rush-in current controller includes a ring oscillator module connected to maintain the delayed sleep control signal based on counting a preset number of ring oscillator cycles corresponding to a virtual power supply line voltage. A method of controlling a rush-in current includes providing a delayed sleep control signal based on counting a preset number of clock cycles corresponding to an input sleep control signal and maintaining the delayed sleep control signal based on counting a preset number of ring oscillator cycles corresponding to a virtual power supply line voltage.

Abstract: A system for controlling gatings of a multi-core processor, the system includes a pulse width modulation generator for generating a control square wave; and a phase shifter for shifting a phase of the control square wave to generate control square waves with different phases, and respectively inputting the control square waves with the different phases to a gating of each of multiple processing engines in the multi-core processor. A multi-core processor is provided that includes multiple processing engines. Each processing engine includes a gating, and a system for controlling the gating. Accordingly, in the multi-core processor, the load to be processed in a certain period of a working cycle can be averaged to be processed in a longer period of the working cycle. Consequently, current noise and voltage noise and temperature growth due to the load change can be reduced.

Abstract: A semiconductor device includes an internal circuit, a power supply control circuit which controls supply of a power supply to the internal circuit upon receipt of a first control signal, and a control signal generation circuit which outputs the first control signal upon receipt of a second control signal. The control signal generation circuit does not deactivate the first control signal when an inactive period of the second control signal is equal to or less than a first period and deactivates the first control signal when the inactive period of the second control signal is more than the first period.

Abstract: A communication system according to one aspect of the present invention, comprises one or more integrated circuits. The one or more integrated circuits comprise at least one of a local integrated circuit and a remote integrated circuit. At least one sending application hardware module located on the local integrated circuit has a sending logic that controls the sending of messages from the sending application hardware module. At least one receiving application hardware module is located on at least one of the local integrated circuit or remote integrated circuit. A sending application hardware module sends messages to a receiving application hardware module without its sending logic having been constructed with a priori knowledge of the address of or the path to said receiving application hardware module. A dispatch logic located on the local integrated circuit that routes at least one or more.

Abstract: In a programmable logic device having high-speed serial interface channels, a clock distribution network for providing one or more high-speed clocks to dynamic phase alignment circuitry of those high-speed serial interfaces includes at least one bus that is segmentable (e.g. using tristatable buffers). This allows the bus to be divided into different portions that can be connected to different clock sources when the high-speed serial interfaces are running at different speeds. In one embodiment, the segmenting elements (e.g., the aforementioned buffers) are located between selected channels (e.g., every fourth channel), limiting the size of the different segments. In another embodiment, segmenting elements are located between each channel, allowing complete user freedom in selecting the sizes of the segments. Thus, instead of providing a bus for every clock source, multiple clocks can be made available to different channels by segmenting a single bus.

Abstract: A system and device for providing power to and monitoring the energy usage of a device connected thereto includes a unit having one or more circuit boards having components for detecting the energy usage of the connected device and an interface for electrically connecting to the device. The unit communicates with a coordinator regarding the connected device or the state of the unit itself. Depending on the communication received from the unit, the coordinator relays the received data to a server and awaits instruction, or immediately commands the unit to take a certain action. If the server receives data from the coordinator, it sends such data to a remote server, saves it, generate reports based thereon, and/or alerts a user regarding same. The user can choose to send a command to the unit or device through the system, for example, to shut down, turn on, or to adjust the power being supplied to the device.

Abstract: A low voltage isolation switch is coupled between an input terminal suitable for receiving a high voltage signal and an output terminal suitable for transmitting this high voltage signal to a load. The isolation switch includes a first driving transistor coupled between a first reference terminal and an intermediate node, a second driving transistor coupled between the intermediate node and the second reference terminal, a control transistor connected across a diode block coupled between the input and output terminals. The control transistor has a control terminal connected to the intermediate node through a low voltage decoupling block that includes first and second substrate terminals, first and second parasitic capacitive element connected to these first and second substrate terminals, and first and second decoupling transistors coupled in parallel to each other and having control terminals connected to the first and second parasitic capacitive elements, respectively.

Abstract: An integrated exciter-igniter architecture is disclosed that integrates compact, direct-mounted exciter electronics with an aerospace designed igniter to reduce overall ignition system complexity. The integrated exciter-igniter unit hermetically seals exciter electronics within a stainless steel enclosure or housing. The stainless enclosure enables the exciter electronics to remain near atmospheric pressure while the unit is exposed to vacuum conditions. The exciter electronics include a DC-DC converter, timing circuitry, custom-designed PCBs, a custom-designed main power transformer, and a high voltage ignition coil. All of which are packaged together in the stainless steel enclosure. The integrated exciter-igniter unit allows for efficient energy delivery to the spark gap and eliminates the need for a high voltage cable to distribute the high voltage, high energy pulses.

Abstract: A constant on-time switching converter includes a switching circuit, an on-time control circuit, a comparing circuit and a logic circuit. The switching circuit has a first switch and is configured to provide an output voltage to a load. The on-time control circuit generates an on-time control signal to control the on-time of the first switch. The comparing circuit compares the output voltage of the switching circuit with a reference signal and generates a comparison signal. The logic circuit generates a control signal to control the first switch based on the on-time control signal and the comparison signal. When the switching frequency of the switching circuit approaches an audible range, the switching converter enters into a sleep mode, the on-time control signal is reduced to increase the switching frequency of the switching circuit.

Abstract: A delay measuring circuit includes a first trigger-signal generating unit that, when a value of a signal input to a circuit under test, changes, generates a first trigger signal. The delay measuring circuit includes a second trigger-signal generating unit that, when a value of a signal output from the circuit under test changes, generates a second trigger signal. The delay measuring circuit includes a delay unit that includes a plurality of delay elements connected in series. The delay measuring circuit includes a delay information retaining unit that individually captures and retains the first trigger signal output from each of the delay elements included in the delay unit between when the first trigger signal is generated by the first trigger-signal generating unit and when the second trigger signal is generated by the second trigger-signal generating unit.

Abstract: A circuit and method are provided for switching in a semiconductor based high power switch. Complementary p-type based transistors are utilized along insertion loss insensitive paths allowing biasing voltages to alternate between supply and ground, allowing for negative voltage supplies and blocking capacitors to be dispensed with, while improving performance.

Abstract: It is described a switching device comprising a semiconductor switching unit; a contactor electrically coupled in series with the semiconductor switching unit; and a controller being configured for activating an electrically isolating state of the switching device and/or activating an electrically conducting state of the switching device based on a command signal or based on a comparison of a measured value and predetermined activation condition.

Abstract: According to one aspect of this disclosure, a circuit arrangement is provided, the circuit arrangement including an electronic component coupled to at least one common power supply node and configured to provide a first signal having a variation in time that is based on power supply via the at least one common power supply node; a detecting circuit coupled to the electronic component, the detecting circuit being configured to detect the first signal and to provide a digital switch array control signal based on the variation in time of the first signal; and a switch array coupled between the at least one common power supply node and at least one power supply source, the switch array being configured to control the power supply via the at least one common power supply node based on the digital switch array control signal.

Abstract: A system for automatically transforming a given synchronous circuit description into an equivalent and provably correct desynchronized circuit description. Included in the automated transformation are techniques for synthesizing a variability-aware controller using a two-phase protocol, techniques for synthesizing a variability-aware controller using gated clocks and testability circuits, techniques for synthesizing a variability-aware controller optimized for performance, techniques for initializing the synthesized controller, techniques for dynamically minimizing power requirements, and techniques for interfacing the desynchronized circuit with external synchronous circuits. Also disclosed are techniques for implementing a system for automatically transforming a synchronous circuit description into an equivalent and provably correct desynchronized circuit description within the context of an electronic design automation design flow.

Abstract: A power converter system includes a controller that provides first and second bistate control signals having mutually exclusive true logic states. Also included is a tri-state interface circuit having a switching stage that generates a tri-state output, wherein true and false logic states correspond to the mutually exclusive true logic states and a high impedance state corresponds to concurrent false logic states of the first and second bistate control signals. The tri-state interface circuit also has a level setting stage that controls a voltage level of the tri-state output during the high impedance state. The power converter system further includes a driver that converts the voltage level of the tri-state output to power stage control signals and a power stage that converts an input voltage to an output voltage based on the power stage control signals. A method of operating a tri-state interface circuit is also provided.

Abstract: Under-voltage, over-voltage, and temperature detectors disposed in a switching circuit are turned on periodically and in response to an oscillating signal having a low duty cycle. Accordingly, because the voltage and temperature detectors remain off for long durations, their operating currents, and thus the operating current of the switching circuit is substantially reduced. The switching circuit has a current limiting function which is disabled when the switch current is below a threshold value, thereby further decreasing the current consumption of the switching circuit at low switch current levels.

Abstract: The present disclosure is directed to a unit phase mixer in combination with an input buffer. The unit phase mixer has a pull-up path for pulling an output terminal up to a first voltage. The pull-up path has a first transistor responsive to a first enable signal and a series connected second transistor responsive to a first clock signal. The unit phase mixer has a pull-down path for pulling the output terminal down to a second voltage. The pull-down path has a third transistor responsive to a second clock signal and a series connected fourth transistor responsive to a second enable signal. The input buffer skews the first and second clock signals by different amounts to enable a break-before-make method of operation so that the first voltage is not connected to the second voltage. The unit phase mixer can be used as a building block in more complex mixers which may include the ability to weight the input clocks as well as providing feed-forward paths for certain of the signals.

Abstract: A microcontroller has an input capture peripheral, wherein the input capture peripheral is configured to store timer values of an associated timer in a memory and wherein the input capture peripheral has a gating input which controls whether an input capture function is activated.

Abstract: A circuit includes first to third nodes, resistors with different resistance, capacitors with different capacitance, first switches corresponding to the same number of resistors, second switches corresponding to the same number of capacitors, and a third switch. A first terminal of each resistor is connected to the first node. A second terminal of each resistor is connected to a first terminal of a corresponding one first switch, a second terminal of each first switch is connected to the second node. A first terminal of the third switch is connected to the second terminal of each first switch. A second terminal of the third switch is connected to a first terminal of each capacitor. A second terminal of each capacitor is connected to a first terminal of a corresponding one second switch. A second terminal of each second switch is connected to the third node.