Abstract: A control chip includes a configurable pin and a control logic. The configurable pin is arranged for coupling a first pin and a second pin of a high-definition multimedia interface (HDMI) connector. The control logic is arranged for controlling the configurable pin to switch between a first operation mode and a second operation mode. The configurable pin serves as an input pin when operating in the first operation mode, and the configurable pin serves as an output pin when operating in the second operation mode. For example, the input pin is arranged for receiving a power supply signal derived from a +5V power signal received by the first pin, and the output pin is arranged for outputting a control signal for controlling hot plug detection (HPD).

Abstract: System and method for controlling one or more switches. The system includes a first converting circuit, a second converting circuit, and a signal processing component. The first converting circuit is configured to convert a first current and generate a first converted voltage signal based on at least information associated with the first current. The second converting circuit is configured to convert a second current and generate a second converted voltage signal based on at least information associated with the second current. The signal processing component is configured to receive the first converted voltage signal and the second converted voltage signal and generate an output signal based on at least information associated with the first converted voltage signal and the second converted voltage signal.

Abstract: A double pole double throw switch device is provided. The device includes a first path circuit, a second path circuit, a third path circuit and a fourth path circuit. The first terminals of the first and second path circuits are coupled to a first port, and the second terminals of the first and second path circuits are respectively coupled to a third port and a fourth port. The first terminals of the third and fourth path circuits are coupled to a fourth port, and the second terminals of the third and fourth path circuits are respectively coupled to the second port and the third port. Each path circuit includes a switch module and a functional switch circuit. When a switch module is turned on, its corresponding functional switch circuit is turned off, and when the switch module is turned off, its corresponding functional switch circuit is turned on.

Abstract: The present invention provides an energy reuse circuit. The energy reuse circuit is connected among a plurality of converters at a releasing side or an absorbing side, and includes an energy absorbing portion, an energy releasing portion and an energy exchange portion, wherein the energy exchange portion is connected to the energy absorbing portion and the energy releasing portion, so as to make the energy absorbing portion and the energy releasing portion exchange potential energy in sequence and thus complete energy reuse.

Abstract: Embodiments of radio frequency switching systems, modules, and methods with improved high frequency performance are described generally herein where the switching module may include a first switch module coupled in series to a second switch module, and a third switch module coupled between the first and the second module and ground. A controllable element of the second module may have a lower off capacitance than a controllable element of the first module. Other embodiments may be described and claimed.

Abstract: In an integrated circuit (IC) adapted for use in a stack of interconnected ICs, interrupted through-silicon-vias (TSVs) are provided in addition to uninterrupted TSVs. The interrupted TSVs provide signal paths other than common parallel paths between the ICs of the stack. This permits IC identification schemes and other functionalities to be implemented using TSVs, without requiring angular rotation of alternate ICs of the stack.

Abstract: An RF switch circuit includes an RF switch including a first NMOS switch formed on a chip substrate, a switch controller including a second NMOS switch and a PMOS switch formed on the substrate, for controlling the RF switch, and a limiter including a deep N-type well diode formed on the substrate, for limiting an RF signal level transferred from the RF switch to the switch controller through the substrate. The first NMOS switch includes a first N-type terminal formed on a deep N-type well substrate formed on the substrate, for receiving a driving power through a first floating resistor, a P-type terminal for receiving a body power through a second floating resistor, and two second N-type terminals for receiving a gate power through a third floating resistor. The P-type and two second N-type terminals are formed on a P-type substrate formed on the deep N-type well substrate.

Abstract: Circuits, integrated circuits, and methods are disclosed for bimodal disable circuits. In one such example method, a counter is maintained, with the counter indicating a logic level at which an output signal will be disabled during at least a portion of one of a plurality of disable cycles. The logic level indicated by the counter is transitioned. An input signal is provided as the output signal responsive to the enable signal indicating that the output signal is to be enabled, and the output signal is disabled at the logic level indicated by the counter responsive to the enable signal indicating that the output signal is to be disabled.

Abstract: A circuit includes an amplifier having an input and an output; and at least one transistor comprising at least one terminal and at least one isolated well. The input of the amplifier is electrically connected to the at least one terminal of the transistor; and the output of the amplifier is electrically connected to the at least one isolated well of the at least one transistor.

Abstract: A high-frequency switch module includes a switch IC. An impedance matching circuit is connected to the antenna port of the switch IC. The impedance matching circuit includes a high-pass filter and a low-pass filter. The high-pass filter is disposed on the side of the antenna port, and is a substantially L-shaped circuit including a capacitor and an inductor. The antenna port is connected to the ground by the inductor.

Abstract: An embodiment of the invention provides an electronic device. The electronic device includes a digital-to-analog converter (DAC), a transmitter front-end (TX FE), an amplifier, an analog-to-digital converter (ADC), and a swap circuitry. The TX FE has a first and a second input end coupled to a first and a second output end of the DAC, respectively. The ADC has a first and a second input end coupled to a first and a second output end of the amplifier, respectively. The swap circuitry is configured to couple the first and second output ends of the DAC to a first and a second input end of the amplifier in a normal state, respectively, and couple the first and second output ends of the DAC to the second and first input ends of the amplifier in a swapped state, respectively.

Abstract: A circuit includes a switching circuit, a node, and a tracking circuit. The switching circuit has a first terminal, a second terminal, and a third terminal. The node has a node voltage. The tracking circuit is electrically coupled to the third terminal and the node, and configured to receive the node voltage and generate a control voltage at the third terminal based on the node voltage.

Abstract: A signal input circuit and method and chip are disclosed. The signal input circuit includes a control signal input terminal configured for receiving a control signal; at least one common signal input terminal each configured for receiving a corresponding common signal; at least one first signal output terminal each configured for outputting a corresponding first signal; at least one first signal unit each configured for receiving said corresponding common signal and outputting said corresponding common signal as said corresponding first signal under control of said control signal; at least one second signal output terminal each configured for outputting a corresponding second signal; and at least one second signal unit each configured for receiving said corresponding common signal and outputting said corresponding common signal as said corresponding second signal under control of said control signal.

Abstract: An element substrate includes a plurality of terminals, a first receiving circuit and a second receiving circuit each receiving a differential signal via one of the terminals included in the plurality of terminals, a driving circuit including a first input unit for inputting a first signal and a second input unit for inputting a second signal and driving a driving element based on the first signal and the second signal, and a setting circuit for setting a first connection state of connecting an output from the first receiving circuit to the first input unit and connecting an output from the second receiving circuit to the second input unit, and a second connection state of connecting an output from the first receiving circuit to the second input unit and connecting an output from the second receiving circuit to the first input unit based on an externally input signal.

Abstract: A signal transfer circuit includes a signal transfer unit configured to transfer an input signal applied to an input node to an output node in response to a control signal and a driving unit configured to drive an output signal of the output node to a level of the input signal in response to the control signal.

Abstract: An electronic circuit includes a receiver circuit (BSP) operable to perform coherent summations having a coherent summations time interval, and a power control circuit (2130) coupled to said receiver circuit (BSP) and operable to impress a power controlling duty cycle (TON, TOFF) on the receiver circuit (BSP) inside the coherent summations time interval. Other circuits, devices, systems, methods of operation and processes of manufacture are also disclosed.

Abstract: In some embodiments, an input/output (I/O) circuit sends and receives a high-level signal and a low-level signal via a coupling capacitance provided on a communication line. The I/O circuit includes a receiving portion including a first detection circuit arranged to detect one of the signals and a second detection circuit arranged to detect the other signal, a transmitting portion including a three-value output circuit configured to output one of signals consisting of a high-level signal, a low-level signal, and a high impedance signal, and a control circuit configured to control the receiving portion and the transmitting portion. The control circuit judges a level of an inputted signal depending on detection results of the first detection circuit and the second detection circuit in a receiving state and controls an output value of the three-value output circuit in a transmitting state.

Abstract: In an exemplary embodiment, an apparatus includes a first set of circuit elements and a second set of circuit elements. The first set of circuit elements is used in a first configuration of the apparatus, and the second set of circuit elements is used in a second configuration of the apparatus. The first configuration of the apparatus is switched to the second configuration of the apparatus in order to improve reliability of the apparatus.

Abstract: A circuit and method are provided for switching in a semiconductor based high power switch. Complementary p-type based transistors are utilized along insertion loss insensitive paths allowing biasing voltages to alternate between supply and ground, allowing for negative voltage supplies and blocking capacitors to be dispensed with, while improving performance.

Abstract: An information generating apparatus and an operation method thereof are provided. The information generating apparatus includes a first logic contact, a second logic contact, an information output contact and a plurality of switches SW(i,j), wherein SW(i,j) represents a jth switch in an ith layer, 1?i?L, and 1?j?2(i?1). The switch SW(i,j) has a first input terminal, a second input terminal and an output terminal, wherein the output terminal is selectively connected to the first or the second input terminal. The first and the second input terminals of the switches SW(Lj) in the Lth layer are respectively connected to the first logic contact and the second logic contact. The first and the second input terminals of the switch SW(i,j) in other layers are respectively connected to the output terminals of the switches SW(i+1,2j-1) and SW(i+1,2j). The output terminal of the switch SW(1,1) is connected to the information output contact.

Abstract: A driving circuit outputs an output voltage as a driving signal to the gate of a semiconductor element based on a control signal given from an input circuit. The output voltage is at “H” (ON level) if it is determined by a power supply voltage VCC, and is at “L” (OFF level) if it is determined by a ground voltage GND. A reference power supply section includes a series connection of resistors. The reference power supply section obtains a voltage determined by dividing a potential difference between the power supply voltage VCC and the ground voltage GND by a predetermined dividing ratio (resistance ratio between the resistors) as a reference voltage. A buffer circuit applies an output voltage as a reference signal determined by the reference voltage to the source of the semiconductor element.

Abstract: A nonvolatile nano-electromechanical system device is provided and includes a cantilever structure, including a beam having an initial shape, which is supported at one end thereof by a supporting base and a beam deflector, including a phase change material (PCM), disposed on a portion of the beam in a non-slip condition with a material of the beam, the PCM taking one of an amorphous phase or a crystalline phase and deflecting the beam from the initial shape when taking the crystalline phase.

Abstract: A method and apparatus for controlling a device in electronic equipment having a plurality of devices are provided. The apparatus includes a power supply for supplying power, a slave device including a driving circuit operated according to the supplied power for transmitting and receiving data to and from another device, a switching circuit for connecting the driving circuit to a ground terminal when the switching circuit is turned-on and for opening the driving circuit from the ground terminal when the switching circuit is turned-off, and a host device for transmitting a control signal for turning-on the switching circuit when driving the slave device and for turning-off the switching circuit when not driving the slave device. When the device is not driven, the switching circuit may open a driving circuit from a ground terminal, thereby cutting-off leakage of an electric current through the device.

Abstract: A semiconductor memory device includes a first plane and a second plane each configured to include a plurality of memory cells, and a data transfer circuit configured to transfer first data, stored in the memory cells of the first plane, to the second plane and transfer second data, stored in the memory cells of the second plane, to the first plane when a copyback operation is performed and to transfer the first data or the second data to an I/O circuit when a read operation is performed.

Abstract: An integrated circuit device for switching data has a plurality of input channels and a plurality of output channels. The device includes a switch for selectively connecting a subset of the output channels, mutually orthogonal, to the input channels by providing signal paths between the selected mutually orthogonal output channels and the input channels. The selected output channels are not orthogonal to the output channels that are not selected.

Abstract: The invention describes an image reading device having a housing, a transparent panel, an image sensor, a carriage, and an electric cable. The housing has a first, second, and third surface. The transparent panel defines a portion of the first surface. The image sensor extends in a first direction, and is mounted to the carriage and optically reads a document through the transparent panel while the carriage reciprocates in a second direction. The electric cable is electrically connected to the image sensor, and includes a band surface portion having a band surface and extending in a third direction intersecting the first and second direction. The electric cable also has a first end portion attached to the carriage; and a second end portion attached to the second surface. At least a portion of the electric cable is twisted such that the band surface and the third surface are not parallel.

Abstract: An apparatus for selecting a plurality of input signals from a plurality of y signals in a device has a switching matrix with a plurality of n to 1 mulitplexers, wherein each n to 1 multiplexer is assigned to a different input set of n of the y signals wherein a subset of less than n input signals of each set of input signals of each of the n to 1 multiplexers is also a subset of input signals of another n to 1 multiplexer.

Abstract: A driving system for an electrical power conversion equipment includes a driving circuit for driving a switching device provided in the electrical power conversion equipment, and a driving capacity control circuit for controlling a driving capacity of the driving circuit. The driving capacity during a resonant operation of the electrical power conversion equipment becomes higher than that at a start of the resonant operation when the switching device is turned-on.

Abstract: A pass transistor circuit according to an embodiment includes: a first input/output terminal connected to a first signal line; a second input/output terminal connected to a second signal line; a first device having a first terminal connected to a first power supply and a second terminal; a second device having a third terminal connected to the second terminal and a fourth terminal connected to a second power supply; a first transistor having one of source/drain connected to the second terminal, a gate receiving a first control signal; and a second transistor having a gate connected to the other one of source/drain of the first transistor, one of source/drain connected to the first input/output terminal, and the other one of source/drain connected to the second input/output terminal. One of the first and second devices is a nonvolatile memory device, the other one of the first and second devices is a MOSFET.

Abstract: There is provided a method for testing a switching circuit including a first FET connected between input/output terminals, a capacitor connected between one of the input/output terminals and the first FET, and a second FET that is connected in parallel with the capacitor and has a gate electrode connected to a ground terminal. The method includes, applying a potential that sets the second FET to a conducting state to the ground terminal, and testing a DC test for the first FET via the second FET.

Abstract: A power supply switch apparatus includes a main outlet, first and second load outlets, a manual switch, and first and second electronic switches. The positive terminal of the main outlet is connected to the positive terminal of the first load outlet and connected to the second terminal of the first electronic switch. The third terminal of the first electronic switch is connected to the positive terminal of the second load outlet. The first terminal of the first electronic switch is connected to the second terminal of the second electronic switch and connected to a voltage terminal through a first resistor. The third terminal of the second electronic switch is grounded. The first terminal of the second electronic switch is connected to the voltage terminal through the manual switch and a second resistor in that order, and grounded through a third resistor.

Abstract: A semiconductor switch includes: a first terminal; a second terminal; a switch section including a through FET connected between the first terminal and the second terminal and a shunt FET connected between the second terminal and a first ground terminal; a first control terminal configured to drive the through FET; a second control terminal configured to drive the shunt FET; and a driver provided on a substrate together with the switch section and configured to provide a differential output to the first control terminal and the second control terminal.

Abstract: An electronic circuit for switching purposes comprises a set of at least four electronic switches. A first subset and a second subset comprise at least two electronic switches of said set, respectively. Said at least two electronic switches of said first subset are arranged in a serial connection. Said at least two electronic switches of said second subset are arranged in a serial connection. The electronic circuit comprises a first buffer connected to a first electronic switch of said first subset and a second buffer connected to a second electronic switch of said second subset. Said first buffer minimises a potential drop across said first electronic switch when in open state, and said second buffer minimises a potential drop across said second electronic switch when in open state. The electronic circuit further comprises a switched connection towards ground arranged in between the two subsets.

Abstract: A circuit includes an amplifier having an input and an output; and at least one transistor comprising at least one terminal and at least one isolated well. The input of the amplifier is electrically connected to the at least one terminal of the transistor; and the output of the amplifier is electrically connected to the at least one isolated well of the at least one transistor.

Abstract: A solid state relay has independent charge pumps isolating each gate of a full bridge to achieve faster and proper gate turn on. The low side MOSFETs of the bridge are the current sensing device reducing loss and allowing a device controlled by the relay to achieve peak performance. Dynamic braking is achieved by the two low side MOSFETs being fully conducted and applying a load across the DC motor. Addition of a microprocessor to the device provides undervoltage sensing, current vs time readings, motor stall sensing, and motor temperature sensing. Motor temperature is detected by checking impedance of the motor at microsecond pulses to see if the motor is getting hot.

Abstract: A circuit for converting a measured variable capacitance to an output voltage signal includes a charge amplifier circuit selectively coupled to an integrator circuit. The charge amplifier circuit, in one implementation, is configured as a high pass filter. In another implementation, the charge amplifier circuit is configured as a combination high pass and low pass filter. The charge amplifier circuit is selectively coupled to the integrator circuit when the circuit forces a switch in voltage across a measurement capacitor.

Abstract: An integrated circuit, in accordance with embodiments of the present technology, includes a plurality of engines, a plurality of engine level power gating (ELPG) controllers, and a power gating arbiter for implementing engine level power gating arbitration techniques. The power gating arbiter may receive requests from one or more ELPG controllers to turn on their respective engines or portions therein. The power gating arbiter prioritizes the request and sends an acknowledgment to a given ELPG controller to turn on or off its corresponding engine according to the prioritized predetermined order. After receiving the acknowledgement, the given ELPG controller turns on or off its corresponding engine and returns an indication to the power gating arbiter that the corresponding engine is turned on or off. The process may be iteratively repeated for each received request after receiving the indication from the previously serviced ELPG controller that its corresponding engine is turned on or off.

Abstract: In accordance with embodiments, a method for configuring an electronic device during a power-on sequence includes sampling a boot pin state multiple times. The method also includes storing a value corresponding to each sampled boot pin state, wherein the stored values comprise one of four different states for a single boot pin.

Abstract: In accordance with an embodiment, a driver circuit includes a low-side driver having a first output configured to be coupled to a control node of a first semiconductor switch, and a reference input configured to be coupled to a reference node of the first semiconductor switch. The low-side driver also includes a first capacitor coupled between an output node of the first semiconductor switch and a first node, a first diode coupled between the first node and a first power input of the driver, and a second capacitor coupled between the first power input of the low-side driver and the reference node of the first semiconductor switch.

Abstract: Methods, circuits and systems for converting of a non-predicated asynchronous netlist to a predicated asynchronous netlist are described. These may operate to identify one or more portions of an asynchronous netlist corresponding to a partially utilized portion of an asynchronous circuit. The asynchronous netlist may be modified to control the partially utilized portion. Additional methods, circuits, and systems are disclosed.

Abstract: A multi-channel semiconductor device comprises a plurality of buffer groups each comprising at least one output buffer, a plurality of pad groups each comprising at least one output pad, and a channel switching portion that controls connection between the plurality of buffer groups and the plurality of pad groups. One of the pad groups outputs an output signal of one of the buffer groups in a first operation mode and sequentially outputs output signals of all of the buffer groups in a second operation mode.

Abstract: Provided is a detection circuit for monitoring a power supply voltage with a circuit configuration in which power consumption is reduced, and a sensor device including the detection circuit. A detection circuit (100) detects an input signal input thereto to output an output signal. An interrupt condition generating circuit (10a) directly detects a power supply voltage (VDD) supplied thereto from a power supply, and outputs an interrupt signal until the power supply voltage makes a transition to a predetermined voltage range. An interrupt condition reception circuit outputs, as an output signal, a given voltage without allowing an input signal (Vtemp) to be output until an interrupt caused by the interrupt signal is released, and outputs, as an output signal, the input signal by allowing the input signal to be output when the interrupt caused by the interrupt signal is released.

Abstract: A power control module including a socket, a switch circuit and an interface control circuit is provided. A plug is adapted to be inserted into the socket, and the socket has a positive terminal, a first negative terminal and a second negative terminal. When the plug is inserted into the socket, a negative terminal of the plug sequentially contacts the first negative terminal and the second negative terminal. The switch circuit receives a power voltage through the positive terminal. The interface control circuit determines whether to generate a switching signal to the switch circuit according to a voltage level of the second negative terminal. When receiving the switching signal, the switch circuit outputs the power voltage.

Abstract: Techniques are disclosed for reducing off-state leakage current in a differential switching device. The techniques can be embodied, for example, in a method that includes receiving a differential input signal at a differential input of each of a primary switch and a dummy switch. In an enabled-state of the device, the method further includes passing the differential input signal to a differential output of the primary switch. In a disabled-state of the device, the method further includes canceling off-state leakage current at the differential output of the primary switch, by virtue of the dummy switch having its differential output reverse-coupled to the differential output of the primary switch. The method may further include preventing the dummy switch from passing signals other than off-state leakage signals. The techniques can be embodied, for instance, in a switching device.

Abstract: A method and apparatus for implementing integrated circuit security features are provided to selectively disable testability features on an integrated circuit chip. A test disable logic circuit receives a test enable signal and responsive to the test enable signal set for a test mode, establishes a test mode and disables ASIC signals. Responsive to the test enable signal not being set, the ASIC signals are enabled for a functional mode and the testability features on the integrated circuit chip are disabled. When the functional mode is enabled, the test disable logic circuit prevents the test mode from being established while the integrated circuit chip is powered up.

Abstract: A high-frequency switch module that significantly reduces deterioration of high-frequency characteristics and improves harmonic wave distortion characteristics includes a high-frequency switch and SAW filters mounted on a multilayer substrate. Low pass filters are provided within the multilayer substrate. The terminals of the high-frequency switch are located on the bottom surface of the semiconductor substrate. The high-frequency switch includes a high-frequency circuit ground terminal and a control circuit ground terminal, the multilayer substrate includes therein a ground electrode which is electrically connected to a top surface connection electrode to which the high-frequency circuit ground terminal is connected, and a wiring electrode electrically connected to a top surface connection electrode to which the control circuit ground terminal is connected is arranged so as to be insulated from the ground electrode.

Abstract: Embodiments of a computer system, a method, an integrated circuit and a computer-program product (i.e., software) for use with the computer system are described. These devices and techniques may be used to analyze an electrical characteristic of a logic gate electrically coupled to an output network in a stage. In particular, during the analysis, the effective capacitance of an output network coupled to a logic gate is approximated as a function of a total resistance of the output network, a total capacitance of the output network, and a geometric parameter of the output network. Using the effective capacitance and other parameters, such as a slew rate of an electrical signal applied to an input of the logic gate, an electrical characteristic of the logic gate, such as an input capacitance, is determined.

Abstract: Embodiments of the invention generally provide a radio frequency switch, for example for use in a satellite receiver. The switch includes a plurality of input ports and a plurality of output ports, where output ports independently select signal paths from any of the input ports. The entire switch is embodied in a compact single-board layout. In another embodiment, a satellite receiver includes at least one antenna for receiving a signal from a satellite transponder and a radio frequency switch for selecting the satellite transponder from among a plurality of satellite transponders.

Abstract: A system comprising an antenna, an antenna matching network, an amplifier of a radio frequency (RF) module, a matching circuit, and a switch. The switch is configured to selectively connect said amplifier to test apparatus via said matching circuit when in a first position, and to said antenna via said antenna matching network when it is in a second position.

Abstract: A logic circuit simulation apparatus used in designing a logic IC (integrated circuit) is provided. The logic circuit simulation apparatus includes a power control signal specifying unit which creates power control signal information for specifying statuses of a plurality of power control signals, a logic circuit simulation control information generation unit which reads the power control signal information and related circuit connection information and generates a logic circuit simulation control information based on the power control signal information and the circuit connection information, and a logic circuit simulation unit which fixes with high impedance each input of a circuit block to which power is not supplied in accordance with the logic circuit simulation control information, simulating the logic circuit.