Abstract: Apparatus for controlling an integrated circuit comprises a power control device for controlling the power to at least part of the integrated circuit, the power control device is connected to a first input, for receiving a power-down signal, and a second input, for receiving a power-up signal, the power control device is adapted to power-up the at least part of the integrated circuit if a power-up signal is received at the second input when the at least part of the integrated circuit is in a powered-down state, and the power control device is further adapted to maintain the at least part of the integrated circuit in the powered-up state regardless of any signal received at the second input when the at least part of the integrated circuit is in a powered-up state, the apparatus is arranged so that the second input is also connected to a component of the integrated circuit and the apparatus comprising means for sending a signal to the component of the integrated circuit via the second input when the at least pa

Abstract: Subject matter disclosed herein relates to circuit design, and more particularly relates to low power circuit techniques for receiver circuits.

Abstract: According to one embodiment, a switching control circuit includes an output circuit, a first circuit, and a second circuit. The output circuit includes an input terminal, an output terminal, and a switching element. The first circuit is connected to a control terminal of the switching element. The first circuit controls an input signal during a period when an output signal of the output circuit changes. The second circuit is connected to a control terminal of the first circuit. The second circuit generates a control signal for controlling a current flowing in the first circuit during the period when the output signal of the output circuit changes.

Abstract: A pulsewidth modulation circuit uses a plurality of programmable paths to connect its output line to ground connections. The paths have different numbers of serially-connected NFETs to provide different pulldown rates. A desired programmable paths is selected based on encoded control signals, with decode logic integrated into the programmable paths. The decode logic includes, for each path, at least two transistors controlled by one of the encoded signals or their complements. A default path to ground may also be provided for use when none of the programmable paths is selected. For example, two encoded signals may be used to select 1-in-4 among the default path and three programmable paths. Integration of the decode logic into the programmable paths results in smaller overall circuit area, leading to reduced power usage, while still retaining the orthogonal benefit of encoded control signals.

Abstract: An apparatus includes a first die having a first bus, a second die having a second bus stacked on the first die, a plurality of through silicon vias connecting the first bus to the second bus, and first control logic for sending data to identified ones of the plurality of through silicon vias. Also, optionally, second control logic for determining a first set of the plurality of through silicon vias that are nonfunctional, wherein the second control logic is configured to send information to the first control logic identifying the first set of the plurality of through silicon vias or identifying a second set of through silicon vias that are functional. Also a method of sending signals through a plurality of through silicon vias.

Abstract: A method for configuring a combinational switching matrix comprises the steps of setting a first switching module and a second switching module, coupling at least one of the output ports of the first switching module with at least one of the input ports of the second switching module to form the combinational switching matrix, building a connection mapping table based on the coupling relationship between the output port of the first switching module and the input port of the second switching module, and displaying a channel switching interface showing the input terminals, the output terminals, and the on/off states of the virtual switching devices of the combinational switching matrix.

Abstract: Power management methods and systems. First, a running cycle of a processing unit processing a data unit is recorded. A gating signal is generated according to the running cycle and a performance requirement, and a working clock is adjusted according to the gating signal. Thereafter, the adjusted working signal is provided to the processing unit.

Abstract: Apparatus for controlling an integrated circuit comprises a power control device for controlling the power to at least part of the integrated circuit, the power control device is connected to a first input, for receiving a power-down signal, and a second input, for receiving a power-up signal, the power control device is adapted to power-up the at least part of the integrated circuit if a power-up signal is received at the second input when the at least part of the integrated circuit is in a powered-down state, and the power control device is further adapted to maintain the at least part of the integrated circuit in the powered-up state regardless of any signal received at the second input when the at least part of the integrated circuit is in a powered-up state, the apparatus is arranged so that the second input is also connected to a component of the integrated circuit and the apparatus comprising means for sending a signal to the component of the integrated circuit via the second input when the at least pa

Abstract: To improve the speed of accessing a low-speed circuit block from a high-speed circuit block without significantly increasing power consumption.

Abstract: A semiconductor device includes: a plurality of external signal input means; an external input unit having a switch each connected between the external signal input means and a read line and electrically connected for output from the external signal input means on the read line; a shift register receiving an external control signal and an external clock signal and synchronized with the external clock signal to shift successively the external control signal to provide shifted data and output the external control signal to electrically connect the switches in accordance with the shifted data; an output circuit receiving the external control signal from the shift register and externally outputting the external control signal; and a frequency divider circuit dividing the external clock signal in frequency to generate and output an internal clock signal, wherein the output circuit is synchronized with the internal clock signal to externally output the external control signal.

Abstract: A circuit arrangement and a method for the DC-isolated driving of a semiconductor switch, wherein the circuit arrangement has a control circuit, a driver, a transformer for the DC-isolated transfer of a drive signal from the controller as switching signal into the driver and means for rectifying the switching signal, wherein the driver contains the semiconductor switch having a gate, a source and a drain, wherein the semiconductor switch can be switched by a predetermined first voltage between the gate and the source with the result that a predetermined current flows between the drain and the source, wherein the switching signal can be applied to the gate in order to switch the semiconductor switch, wherein the driver contains a control transistor having a base, an emitter and a collector, wherein the control transistor can be switched by a predetermined second voltage between the base and the emitter, with the result that the gate of the semiconductor switch can be connected to the source of the semiconducto

Abstract: Provided is an apparatus for protecting a receiver circuit in a Time Division Duplexing (TDD) wireless communication system. In the protecting apparatus, an antenna switch transmits an output signal of a power amplifier to an antenna feed line and transmits an output signal of the antenna feed line to a low noise amplifier. A status monitor monitors a status of the antenna switch. A mode determiner disables an amplification operation of the power amplifier when a status monitoring signal output from the status monitor indicates an RX mode.

Abstract: An electronic device includes a central processing unit, a USB connector, a USB switch, and an audio path selector. The USB switch has a data transmission path and an audio signal transmission path for signal transmission between the central processing unit and the USB connector. The USB switch selects the data transmission path for data transmission according to a first selection signal from the central processing unit, and selects the audio signal transmission path for audio signal transmission according to a second selection signal from the central processing unit. The audio path selector interconnects the central processing unit and the USB switch, and has a first audio path for output of audio signals from the central processing unit to the audio signal transmission path, and a second audio path for output of audio signals from the audio signal transmission path to the central processing unit.

Abstract: There is provided a semiconductor device including: a temperature sensor detecting temperature; an inner circuit operating when supplied with a power supply voltage from a power supply line; a switch connected between the power supply line and the inner circuit; and a control circuit performing control in which, in a case where the temperature detected by the temperature sensor is higher than a threshold value, the switch is turned on when the inner circuit is in operation and the switch is turned off when the inner circuit is in non-operation, and in a case where the temperature detected by the temperature sensor is lower than the threshold value, the switch is turned on when the inner circuit is in operation and in non-operation.

Abstract: A peripheral device has a bus-controlled switching arrangement for operating a power supply. A device comprises a bus interface adapted for communicating with a remote device via a bus. A switch circuit is connected between the bus interface and a power supply. The switch circuit is operative, when the power supply is in an inactive state, for sensing bus activity and for generating a signal for activating the power supply in response to the sensed bus activity, wherein the switch circuit has no power dissipation when no activity is sensed on the bus.

Abstract: A switch circuit includes: a first charge/discharge circuit having a fixed first time constant; a second charge/discharge circuit having a second time constant associated with the operation statuses of a plurality of switches; first and second input/output ports to which the first and second charge/discharge circuits are connected, respectively; and a control section adapted to measure the first and second time constants by charging or discharging the first and second charge/discharge circuits and determine the operation statuses of a plurality of switches based on the ratio of the measured first and second time constants.

Abstract: One embodiment of an apparatus for switching a transistor includes a first current mirror providing iB=K1i1, as a transistor base current, wherein the first current mirror is selectively driven by a current source i B ? ? MAX K 1 . A second current mirror providing a feedback signal i2=K2iD to the first current mirror such that i 1 + i 2 = i B ? ? MAX K 1 , wherein iD contributes to the transistor collector current, wherein iB=iBMAX?K1K2iD.

Abstract: An integrated gate driver circuit receives a plurality of clocks and includes a plurality of driving units cascaded in series. Each driving unit is for driving a load and includes an input terminal, an output terminal, a first switch and a second switch. The first switch has a first terminal coupled to the input terminal, a second terminal coupled to a first node, and a control terminal receiving a first clock, and the first switch is turned on when the first clock is at high level. The second switch has a first terminal receiving a second clock, a second terminal coupled to the output terminal, and a control terminal coupled to the first node, wherein the second clock charges and discharges the load through the second switch when the first node is at high level; wherein the output terminal of each driving unit is coupled to the input terminal of the immediately succeeding driving unit.

Abstract: A self-powered current loop transmitter transmits a process variable over a wireless link, deriving operating power from the current which drives the loop. A storage capacitor is connected across the system input terminals through a switch to provide the operating power for the system components.

Abstract: A signal processing circuit is configured by connecting a plurality of basic circuits connected in series, each of the basic circuits comprising an arithmetic circuit subjecting a first input signal and a second input signal to a signal processing; a first selection circuit outputting the first input signal or an output signal of the arithmetic circuit; and a second selection circuit outputting the second input signal or an output signal of the arithmetic circuit, so as to make it possible to change operations of the circuit as a whole by properly making a selection on which signal should be output with the aid of the first and second selection circuits, and to execute different signal processing on a single circuit depending on the selection.

Abstract: A switch circuit is provided for conditional communication within a magnetic-induction interface, including first and second control nodes, a data input and output nodes, a parallel circuit, and first and second control nodes. The parallel circuit includes a pair of legs, each leg connecting to the data input and data output nodes. Each leg has a connector to a condition. Each control node is connected to the corresponding connector. The condition is one of the interface is connected and the interface is disconnected. The parallel circuit enables communication between the data input and output nodes only in response to the condition being that the interface is disconnected. The pair of leg includes first and second legs. The first leg includes a first MOSFET and a first diode. The first MOSFET has a first source, a first gate and a first drain. The second leg includes a second MOSFET and a second diode. The second MOSFET has a second source, a second gate and a second drain.

Abstract: The invention relates to current switches using a differential pair of transistors and being able to operate under a low supply voltage Vcc. According to the invention, provision is made for the current switch to include two differential pairs of two transistors each (T1, T1b; T2, T2b), cascaded together, the second pair (T2, T2b) having complementary current outputs (H, Hb) that flip according to the states of the inputs (E, Eb). The first pair (T1, T1b) is connected to a ground (GND) through a current source, supplying a current of value Io and comprising a transistor (Ts1) biased by a voltage Vbias, and it is supplied by a voltage equal to N·Vbe+Vbias, where N is a whole number (preferably equal to 1) and Vbe is the base-emitter voltage of the transistor (Ts1). The second pair (T2, T2b) is connected to ground directly through a resistance (R2). The invention can be applied to the on-off control of sample-and-hold circuits, multiplexers, fast low-voltage logic circuits, etc.

Abstract: A device for measuring the position of a first body relative to a second body comprising: a first body which further comprises an electrical intermediate device; a second body which further comprises at least two inductors energised with an alternating current and at least one of which is formed by a planar spiral winding on a printed circuit board normal to the measurement axis and attached to the second body; arranged such that displacement of the electrical intermediate device causes a change in inductance of the planar spiral winding and whereby measurement of the ratio of the inductances indicates the position of the first body relative to the second.

Abstract: A power-off circuit includes a power unit (10), a power management unit (20), an integrated circuit chip (IC chip, 40), a switching apparatus (30), and a clamp circuit (70). The switching apparatus produces and transmits a power-off instruction to the power management unit. The power management unit produces and transmits a power-off notice to the IC chip in accordance with the power-off instruction. And the IC chip feeds back a power-off affirmation in accordance with the power-off notice to the clamp circuit. The clamp circuit receives the power-off affirmation and produces and transmits interrupted power-off signals to the power management unit, till the power management unit completely cuts off power supplied from the power unit to the IC chip.

Abstract: This control device includes: a rectifier to rectify a received signal; an amplifier having an amplifying element to amplify the signal rectified by the rectifier and an assisting element being connected to the amplifying element to assist the amplifying element; a determination unit to determine presence or absence of the signal amplified by the amplifier; and a controller to control the connection of the assisting element with the amplifying element at a predetermined timing.

Abstract: Provided is a clock gating circuit which receives a first clock signal and controls an output of a second clock signal corresponding to the first clock signal in response to a control signal. The clock gating circuit includes: a first latch that latches a signal value of the control signal in synchronization with the first clock signal; an AND that receives the first clock signal and controls an output of the second clock signal in response to an output signal of the first latch; and a second latch that latches a signal value of the output signal of the first latch in synchronization with the first clock signal, and outputs a latched value. This enables execution of a scan test with a simple circuit configuration.

Abstract: In one embodiment of the invention, a capacitor is provided between a node and a negative-side input terminal of a differential amplifier. A switch SW11 is provided between the negative-side input terminal and an output terminal of the differential amplifier. A switch SW12 is provided between the node and the output terminal of the differential amplifier. Switches SW13 to SW16 are provided for switching between a voltage of the node and a positive-side input voltage of the differential amplifier. The switches SW11 and SW12 are on during different periods. In a positive polarity mode, the switches SW13 and SW16 are when the switch SW11 is on while the switch SW16 is on when the switch SW12 is on. In a negative polarity mode, the switches SW14 and SW15 are on when the switch SW11 is on while the switch SW16 is on when the switch SW12 is on. Thus, two types of gradation voltages each required for AC drive of a liquid crystal can be generated with a small circuit scale.

Abstract: A signal generating and switching apparatus and a method thereof are provided. According to a simple layout technique, the signal switching apparatus is formed in each layer of a plurality of metal layers in an integrated circuit. When there is a need to correct any one of the plurality of conductive layers in the integrated circuit, the changing of the signal switching apparatus in that conductive layer can be achieved by changing mask patterns of the conductive layer. As a result, the transmission path of signals in the conductive layer is changed, and the purpose to change output logic signals is achieved. Therefore, there is no need to change additional conductive layers, thereby significantly reducing the correcting cost of the integrated circuit.

Abstract: An exemplary circuit for turning on a motherboard comprises a first switch module comprising a first terminal arranged to receive a standby power and connected to a sixth terminal of a computer front panel header, a second terminal arranged to receive the standby power, and a control terminal; a timing circuit charged by a system power; and a second switch module comprising a first terminal connected to the control terminal of the first switch module via the timing circuit, a second terminal arranged to receive the standby power, and a control terminal arranged to receive the system power, wherein, when the system power is lost, the second switch module discharges the timing circuit for turning on the first switch module after a discharge time, and the motherboard is turned on when the first switch module is turned on to ground the sixth terminal of the computer front panel header.

Abstract: Provided are a pass gate circuit and a method of controlling the same for improving meta-stability when transferring signals. The gate circuit includes a signal transfer unit transferring an input signal in response to a transfer control signal, and a control signal generating unit generating a safety window having a predetermined width in response to detection of a transition of the input signal, generating an internal control signal for maintaining the signal transfer state of the signal transfer unit, and outputting the internal control signal to the signal transfer unit as the transfer control signal.

Abstract: A high-voltage tolerant pass-gate assembly (18) for controlling an electrical signal between a first pad (12) and a second pad (14) includes a pass-gate (24) and a first native device (26). In certain embodiments, the first native device (26) is positioned between the first pad (12) and the pass-gate (24). The first native device (26) is permanently enabled. In another embodiment, the pass-gate assembly (18) includes a second native device (28) positioned between the pass-gate (24) and the second pad (14). The second native device (28) can also be permanently enabled. Neither the first native device (26) nor the second native device (28) controls an on-off state of the pass-gate (24). The first native device (26) can have a first voltage and the pass-gate (24) can have a supply voltage that is substantially similar to the first voltage.

Abstract: Off-leak current of a TFT, required for a drive circuit configured with a TFT of a single conductivity type, is realized with simple manufacturing steps. The impurity concentration of a source region and a drain region of a TFT is set between 2*1018 cm?3 and 2*1019 cm?3, whereby off-leak current of the TFT can be sufficiently reduced even in a single gate structure.

Abstract: A signal output circuit adapted to a selector circuit is constituted of an inverter circuit which activates propagation of an input signal therethrough in an active level of a control signal and which inactivates it in an inactive level of the control signal, and a control circuit which maintains the input terminal of the inverter circuit at a predetermined potential irrespective of the level of the input signal in the inactive level of the control signal. This achieves high-speed and high-precision propagation of the input signal. The selector circuit is formed using a plurality of signal output circuits so as to selectively output one of first and second input signals in response to the control signal.

Abstract: A method for switching an operating state in a portable electronic device includes sending a switching signal when a plurality of specific pads of the portable electronic device are triggered simultaneously, and switching the operating state of the portable electronic device according to the switching signal.

Abstract: A circuit arrangement (100) and a method for the DC-isolated driving of a semiconductor switch (400) are presented, wherein the circuit arrangement has a control circuit (101), a driver circuit (102), a transformer (200) for the DC-isolated transfer of a drive signal from the control circuit (101) as switching signal into the driver circuit (102) and means for rectifying (301, 302) the switching signal, wherein the driver circuit (102) contains the semiconductor switch (400) having a gate electrode (401), a source electrode (402) and a drain electrode (403), wherein the semiconductor switch (400) can be switched by a predetermined first voltage between the gate electrode (401) and the source electrode (402), with the result that a predetermined current flows between the drain electrode (403) and the source electrode (402), wherein the switching signal can be applied to the gate electrode (401) in order to switch the semiconductor switch (400), wherein the driver circuit (102) contains a control transistor (32

Abstract: A semiconductor network is interposed between first and second multiple-port interfaces each having high-voltage, intermediate-voltage and ground ports to form a switch assembly. The assembly includes a primary switch circuit, a support network, internal and external-port circuits and internal and external-port control circuits. The primary switch circuit is coupled to high-voltage ports of the multiple-port interfaces and to the support network. The internal and external-port circuits are coupled to intermediate-voltage ports of the multiple-port interfaces, the internal and external-port control circuits and the support network. The internal-port control circuit is coupled to the internal-port circuit, the support network and a ground port of a first multiple-port interface. The external-port control circuit is coupled to the external-port circuit, the support network and a ground port of the second multiple-port interface.

Abstract: A thin film transistor circuit has a main thin film transistor (10), a control input (12) for controlling the operation of the main thin film transistor and a threshold adjustment capacitor (14) connected between the control input and the gate of the main thin film transistor. A charging circuit (16, 18) is used for charging the threshold adjustment capacitor to a desired threshold adjustment voltage. The circuit is used to affect a voltage shift to the voltage applied to the control input. This effectively implements a threshold voltage change by altering the relative voltages on the main transistor gate and the control input.

Abstract: A non-reflective ring topology MPNT switching device comprises at least two poles, at least four throws, plural main switches, and plural bridge switches. The bridge switches enable all throws to be non-reflective throughout a wide frequency range. Each main switch is connected between one of the poles and one of the throws. Each bridge switch is connected between two of the throws, and each throw is connected to at least M+1 of the bridge switches, M being the pole count. In operation, each of M of the main switches has a first (ON) state and is connected to one of M active throws. For each active throw, each bridge switch connected to the active throw has a second (OFF) state. For each non-active throw, one bridge switch connected to the non-active throw has the first (ON) state and each other connected bridge switch has the second (OFF) state.

Abstract: A semiconductor integrated circuit includes power supply pads of two or more kinds, switches each of which is connected between adjacent two of the power supply pads to allow short-circuiting them, and at least one control line connected to control terminals of the switches according to the kinds of the power supply pads connected to the switches.

Abstract: The application provides a switching circuit for switchably connecting an input node and an output node. The switching circuit comprises a switch operable to switchably connect the input node to the output node in response to a switching signal. A sensor is provided for sensing the voltage between the input and output nodes and providing a sense signal in response thereto. A driver coupled to the sensor adjusts the switching signal in response to the sense signal.

Abstract: The present invention is a solid state relay having improved high speed turn on and lower heat dissipation of the power transistor. It uses a voltage level converter and AC-DC converter to provide a control input to an isolation transformer primary. The secondary of the isolation transformer is rectified and charges capacitors having capacitance much higher than that of control input of the power transistor. Transistors are coupled to a controller and the capacitors. The transistors are controlled by the controller to provide for the charging of the capacitors and later transferring of voltage from the capacitors into the capacitance of the control input of the power transistor so that it is charged quickly and turns on quickly. Similar operation occurs for quickly turning off the power transistor.

Abstract: A system for automatically transforming a given synchronous circuit description into an equivalent and provably correct desynchronized circuit description. Included in the automated transformation are techniques for synthesizing a variability-aware controller using a two-phase protocol, techniques for synthesizing a variability-aware controller using gated clocks and testability circuits, techniques for synthesizing a variability-aware controller optimized for performance, techniques for initializing the synthesized controller, techniques for dynamically minimizing power requirements, and techniques for interfacing the desynchronized circuit with external synchronous circuits. Also disclosed are techniques for implementing a system for automatically transforming a synchronous circuit description into an equivalent and provably correct desynchronized circuit description within the context of an electronic design automation design flow.

Abstract: A level converter for providing an output signal at a circuit output based on an input signal includes an output coupling circuit formed to provide an output signal based on a first partial output signal and a second partial output signal, a driver circuit formed to provide the second partial output signal such that the second partial output signal is switchable between two different signal levels depending on the state of the input signal, wherein an input of the driver circuit is capacitively coupled to the input of the level converter in order to allow for switching between the signal levels of the second partial output signal by the capacitive coupling in response to a change in the state of the input signal, and a holding circuit formed to keep the state of the second partial output signal constant in case of a constant state of the input signal.

Abstract: The semiconductor intergrated circuit comprises: a circuit that executes a predetermined process and a switching circuit that selects a power impedance, The switching circuit selects the power impedance, in accordance with a variation in voltage supplied to the circuit, so that a resonant frequency of the semiconductor integrated circuit is different from a operation frequency of the circuit.

Abstract: A system for equalizing transition density in an integrated circuit includes a first circuit configured to transition according to a data stream; and a second circuit configured to transition at a time when the first circuit is not transitioning.

Abstract: A CMOS circuit in low-voltage implementation, low power-consumption implementation, high-speed implementation, or small-size implementation. In a circuit which uses a FD-SOI MOST where a back gate is controlled by a well, voltage amplitude at the well is made larger than input-voltage amplitude at the gate. Alternatively, the circuit is modified into a circuit which uses a MOST that changes dynamically into an enhancement mode and a depletion mode.

Abstract: Provided is an electronic device capable of completely interrupting a power source and an electronic circuit when the electronic circuit is not being operated, and reducing power consumed wastefully. In the electronic device including the power source, a switch, and the electronic circuit, the power source and the electronic circuit are electrically interrupted by the switch when the electronic circuit is not being operated. The electronic device further includes a power generation source for converting environmental energy into electric energy, and a switch control circuit driven by the power generation source.

Abstract: An interface circuit provided with a first input/output unit and a second input/output unit which respectively access external apparatuses to which electric power is supplied from power sources via different electric power supply lines includes an acquisition unit configured to acquire information whether electric power is supplied to the respective external apparatuses based on a command from the outside; a selection circuit configured to select an input/output unit corresponding to an external apparatus to which electric power is supplied, from the first input/output unit and the second input/output unit based on the information acquired by the acquisition unit; and a control circuit configured to output an instruction corresponding to the command, to the external apparatus to which electric power is supplied, via the input/output unit selected by the selection circuit.

Abstract: A circuit is disclosed, including a transistor switch having a first terminal to receive an input voltage, a second terminal to output an output voltage and a gate terminal; a determination circuit, coupled to the first terminal and the second terminal of the transistor switch, to determine a lower or higher voltage between the input voltage and the output voltage; a voltage generator, coupled to the determination circuit, to generate a sum voltage or difference voltage using the lower or higher voltage; and a control circuit, coupled to the voltage generator and the gate terminal of the transistor switch, to apply the sum voltage or difference voltage to the gate terminal of the transistor switch during a first time interval.

Abstract: A computer readable storage medium includes executable instructions to analyze an asynchronous, multi-rail digital circuit to identify a gating sub-circuit and a gated sub-circuit. The asynchronous, multi-rail digital circuit is transformed to segregate the gating sub-circuit and the gated sub-circuit.