Abstract: A device monitors at least one power switch which is series-mounted with a logic core between a first and a second potential. A connection point between the switch and logic core is carried to a third potential. The switch is biased by a biasing potential. The device includes a feedback control module mounted between first and second potentials which is capable of generating a set potential representative of the third potential variation. A biasing module of the power switch is mounted between the first and second potentials, and generates a biasing potential based on the set potential. The biasing potential linearly varies with the decrease of the third potential.

Abstract: An output signal switching device includes a switching unit connected to a base board and a detection resistor. The voltage of the detection resistor is set to be constant by a resistor. The expansion board includes the detection resistor. When being connected to the expansion board, the switching unit interrupts a signal inputted to the switching unit from the base board.

Abstract: There is provided a switching circuit including, a semiconductor switching circuit comprising, a transistor, a first electrode of the transistor being connected to an electrical source via a load, a second electrode of the transistor being connected to a standard potential, a driving circuit outputting a signal to a control electrode of the transistor on a basis of a potential in the first electrode of the transistor so as to turn on and off the transistor, the driving circuit turning on when an input voltage applied from an input terminal being a first voltage higher than a threshold voltage of the transistor, the driving circuit turning off when the input voltage being a second voltage lower than the threshold voltage of the transistor.

Abstract: A circuit for breaking a signal path has not only a switching means but also a low-pass or bandpass filter whose frequency characteristic is switchable or bypassable. The insulation between the input and the output when the switching means is open, which decreases with frequency in the case of ordinary switching means, is compensated for by the filter which is then connected. In one embodiment of the circuit, an out-of-band signal is applied to the circuit in addition to the useful signal. The out-of-band signal is intended to be supplied permanently to an evaluation circuit, regardless of the switching position of the switching means. To this end, the out-of-band signal is tapped off downstream of the filter, and the filter is designed such that the out-of-band signal can pass through the filter In the case of a circuit for selecting one of two inputs, at least one of the inputs is provided with switchable or bypassable filter, and the switching means is a selection means.

Abstract: An apparatus for driving a load that may include, for instance, a semiconductor chip, comprising a first switch, and a fracture sensor. The apparatus may further include, for instance, a circuit disposed outside the semiconductor chip and comprising a second switch coupled in series with the first switch, and configured such that an on/off state of the second switch is set in accordance with a state of the fracture sensor.

Abstract: A transmission gate switch includes a switching unit to conduct a switching operation between first and second nodes in response to a switching signal, and an isolation unit to prevent the switching unit from being turned on by a negative swing of the first or second node while the switching unit is being turned off.

Abstract: System and method for changing a current input terminal of a user device. In one embodiment of the invention, a method includes receiving an input terminal change request, requesting that a current input terminal be changed from a first input terminal to a second input terminal. The method may further include determining if an external device is connected to the second input terminal. In one embodiment of the invention, the second input terminal includes a connection detection switch. The method may also include switching to the second input terminal when the connection detection switch indicates an external device connection and skipping the second input terminal when the connection detection switch indicates no external device connected according to one embodiment of the invention.

Abstract: The invention relates to an electronic switching circuit in which a plurality of test circuit blocks is provided, whereby every test circuit block comprises a first sub-circuit block and at least one second sub-circuit block. A field effect transistor in the first sub-circuit block has a gate insulation layer that is thicker than the gate insulation layer of a field effect transistor in the second sub-circuit block.

Abstract: In an embodiment of the invention, power consumption savings are realized in an array design. Such an array design, for example and not limitation, can be used in integrated circuits, including microprocessors as memory arrays, and or instruction cache arrays. Power consumption savings are realized in the array design by utilizing multiple gating modes to allow an early gating signal, late resolving gating signals, and/or specific encodings of way select signals to gate all of the array or a portion of the array saving power when it is determined the array output is not needed.

Abstract: A semiconductor circuit which outputs an active potential in a first period and which holds an inactive potential in a second period which is longer than the first period and then outputs the inactive potential, the semiconductor circuit includes a switch element which is connected between a potential supply section which supplies the inactive potential and a circuit output terminal, and which is brought into a conduction state in the second period so as to output the inactive potential to the circuit output terminal.

Abstract: A buffer circuit operative at multiple power supply voltage levels includes first and second buffers, the first buffer being configured for operation with a first voltage source and the second buffer being operative with a second voltage source. The buffer circuit further includes a controllable isolation circuit. An output of the first buffer connects to an external pad of the buffer circuit, and an output of the second buffer connects to the pad via the isolation circuit. The buffer circuit is selectively operative in at least a first mode or a second mode in response to at least a first control signal. The isolation circuit is operative in the first mode to substantially isolate the second buffer from the external pad and is operative in the second mode to connect the output of the second buffer to the external pad.

Abstract: A buffer circuit permitting an input signal to pass and prohibiting the input signal from passing corresponding to an output control signal, including an output switching device, a control portion having a first switching circuit controlling the output switching device into conductive state and a second switching circuit controlling the output switching device into non-conductive state, and controlling the output switching device into the conductive state or non-conductive state corresponding to the input signal and the output control signal, wherein a connecting point between the first switching circuit and the second switching circuit is coupled to the output switching device, and a changing portion connected to the second switching circuit in series and limiting the drive capacity of the output switching device when the output control signal is in an output prohibition state of prohibiting the input signal from passing.

Abstract: A semiconductor integrated circuit includes an oscillation circuit outputting an oscillation signal, and a switch circuit switching whether the oscillation signal received from the oscillation circuit is to be output to the outside or not.

Abstract: A switch circuit comprising a plural of switch elements and a control circuit operative to simultaneously shut off all of the switch elements. When forming a switch device by the combination of plural switch circuits, no other additional switches connected in series in the subsequent stage is required for shutting off unintentional signals from other input terminals.

Abstract: A reference voltage generator uses a conventional forward junction voltage generating device and a conventional thermal generator to generate a thermal voltage. The forward junction voltage and the thermal voltages have respective thermal sensitivities that act oppositely to each other so that, when the forward junction voltage is combined with the thermal voltage to produce a reference voltage, the reference voltage is substantially insensitive to temperature. The forward junction voltage and the thermal voltage are combined to produce the reference voltage in a manner that avoids generating any voltage having a magnitude that is greater than the magnitude of the sum of the forward voltage and the thermal voltage.

Abstract: A signal switching circuit includes an input terminal to which a signal is input, an output terminal from which a signal is output, a first electronic circuit and a second electronic circuit which are alternately connected between the input terminal and the output terminal, and switching elements for alternately connecting the first electronic circuit and the second electronic circuit between the input terminal and the output terminal through a selection. A signal alternative path for connecting between the input terminal and the output terminal at all times is provided. Even when the switching elements are in an open state, the signal that is input to the input terminal is output to the output terminal via the signal alternative path.

Abstract: The first terminals of a plurality of resistor elements are connected to the intermediate connection points of a plurality of FETs connected in series, and a voltage, having a phase opposite to that of the voltage applied to the gate terminals of the plurality of FETs, is applied to the second terminals of the plurality of resistor elements. With this configuration, the potentials at the intermediate connection points of the plurality of FETs connected in series can be prevented from lowering. As a result, the power that can be handled can be increased. Furthermore, since the potentials at the intermediate connection points of the plurality of FETs connected in series can be prevented from lowering, the deterioration of the distortion characteristic and the isolation characteristic owing to the lowering of the potentials at the intermediate connection points of the plurality of field-effect transistors connected in series is prevented, and excellent high-frequency characteristics are obtained.

Abstract: An electronic signal processing apparatus has a signal switch with a first and a second transistor of normally-on type, having main current channels coupled between an internal node and a switch input and output, respectively. A diode provides a switchable signal coupling between the internal node and ground. A switch control circuit has a control output that is DC coupled to the main current channel of the first and the second transistor via the internal node to control conduction of the main current channels. The diode is also DC-coupled to the internal node so that a DC potential of a terminal of the diode that controls whether the diode is on or off is determined by a potential of the internal node. The diode is preferably incorporated in the DC current path from the control output to the internal node, so that the diode is forward-biased when a control voltage that makes the main current channels non-conductive is applied.

Abstract: A switch includes at least two signal ports in series with a series FET connected therebetween, and a shunt path having an FET, whereby an input bias is applied to a gate on the series FET and to a drain on the shunt FET. In one embodiment, the switch includes a control signal input, an FET connected in series across the first port and the second port, the series FET having a gate coupled to the control signal input, and a shunt path provided by an FET, the shunt FET having a drain coupled to the control signal input and to the gate of the series FET, whereby a single control signal is applied to both the series FET and the shunt FET, via the control signal input, in order to turn the series FET on and simultaneously turn the shunt FET off and, conversely, in order to turn the series FET off and simultaneously turn the shunt FET on.

Abstract: A time limit function utilization apparatus includes a first function block, a second function block, a signal line which connects the first and second function blocks and allows using a desired function that is generated by accessing the first and second function blocks with each other, and a semiconductor time switch interposed in or connected to the signal line, and disables or enables mutual access between the first and second function blocks upon the lapse of a predetermined time.

Abstract: A high-speed CMOS transmit/receive antenna switch includes a first transistor, a second transistor and a parasitic compensation network. The first transistor is operably coupled to an antenna, to a transmit path, and to receive a transmit/receive (T/R) control signal. The second transistor is operably coupled to the antenna, the receive path, and to receive the T/R control signal. When the T/R control signal is in a first state, the first transistor is active and the second transistor is inactive such that the transmit path is coupled to the antenna. When the T/R control signal is in a second state, the second transistor is active and the first transistor is inactive such that the receive path is coupled to the antenna. The parasitic compensation network is coupled to compensate for adverse effects of parasitic components of the first and second transistors at operating frequencies of the transmit/receive antenna switch.

Abstract: A semiconductor apparatus is provided which makes it possible to reduce the number of control terminals required for switching through paths of a high frequency signal, simplify the circuit configuration for controlling the terminals, improve an isolation characteristic between on path and off path of a through FET, and obtain a sufficiently high isolation. In this semiconductor apparatus, one specific through FET and each of shunt FETs connected to each of through FETs other than the one specific through FET are simultaneously turned on in response to the same control signal inputted to the same control terminal. Thus, when a high frequency signal leaks from an output terminal to the signal path of the through FET having been turned on, through the signal paths of the through FETs having been turned off, the high frequency signal can be released to GND through the shunt FET having been turned on.

Abstract: A semiconductor switch comprises two NMOS transistors coupled in an anti-series arrangement, and a gate control circuit coupled to both gates of the NMOS transistors. Both drains of the NMOS transistors are interconnected, and the gate control circuit is coupled to the drains interconnection. The required chip area is halved compared to prior art switches. Pumping the gates to higher voltages may cause a further reduction of the sizes of the NMOS transistors. In addition, advantageously, a large range of input and output voltages can be allowed between the sources of the NMOS transistors, whereby the sources act as input and output respectively of the switch, thus allowing application of the switch in a broad technical field.

Abstract: The first terminals of a plurality of resistor elements are connected to the intermediate connection points of a plurality of FETs connected in series, and a voltage, having a phase opposite to that of the voltage applied to the gate terminals of the plurality of FETs, is applied to the second terminals of the plurality of resistor elements. With this configuration, the potentials at the intermediate connection points of the plurality of FETs connected in series can be prevented from lowering. As a result, the power that can be handled can be increased. Furthermore, since the potentials at the intermediate connection points of the plurality of FETs connected in series can be prevented from lowering, the deterioration of the distortion characteristic and the isolation characteristic owing to the lowering of the potentials at the intermediate connection points of the plurality of field-effect transistors connected in series is prevented, and excellent high-frequency characteristics are obtained.

Abstract: A one way conductor includes a MOSFET and a driving device. The MOSFET has a source and a drain respectively serving a positive end P and a negative end N of the one way conductor. The driving device including a BJT differential amplifier detects a voltage difference between the source and the drain of the MOSFET. When the voltage of the positive end P is higher than the voltage of the negative end N, the driving device outputs a driving voltage to a gate of the MOSFET to turn on the MOSFET. If the voltage of the positive end P is lower than the voltage of the negative end N, the driving device cannot output the driving voltage for turning on the MOSFET, and the one way conductor is turned off at this time. Consequently, the one way conductor of the invention has the one way conductive property.

Abstract: A high-speed CMOS transmit/receive antenna switch includes a first transistor, a second transistor and a parasitic compensation network. The first transistor is operably coupled to an antenna, to a transmit path, and to receive a transmit/receive (T/R) control signal. The second transistor is operably coupled to the antenna, the receive path, and to receive the T/R control signal. When the T/R control signal is in a first state, the first transistor is active and the second transistor is inactive such that the transmit path is coupled to the antenna. When the T/R control signal is in a second state, the second transistor is active and the first transistor is inactive such that the receive path is coupled to the antenna. The parasitic compensation network is coupled to compensate for adverse effects of parasitic components of the first and second transistors at operating frequencies of the transmit/receive antenna switch.

Abstract: One embodiment is a clock gater circuit comprising an inverter block for driving an output clock signal responsive at least in part to an input clock signal that is selectively driven via a clock generator circuit to an input node of the inverter block responsive to a qualifier signal. Also included is circuitry for restoring a logic level at the input node of the inverter block to a particular value, the circuitry operating responsive to the qualifier signal.

Abstract: An I/O circuit between a low voltage circuit and a high voltage circuit includes a switching device, a native device and a gate control logic circuit. The switching device provides an output signal to the high voltage circuit in response to a data input signal received from the low voltage circuit. The native device passes the data input signal to control an on or off state of the switching device. The gate control logic circuit operates in an output disabled mode and an output enabled mode. In the output disabled mode, the gate control logic circuit disables the native device for preventing a leakage current passing therethrough. In the output enabled mode, the gate control logic circuit enables the native device to pass the data input signal through without a substantial voltage drop, thereby enhancing a switching speed of the switching device.

Abstract: Transition signal control for creating asynchronous timing is provided using a transition signal control circuit, which includes Muller C elements each with an inverter. The control device is constituted by a machine ring including n-stages of transition signal control circuits, a state ring including k-stages of transition signal control circuits, and a synchronous circuit for synchronizing with the machine ring by receiving a vector which is output from the state ring. When the output vector of the state ring is received, the synchronous circuit outputs a vector to the machine ring. The output vector of the machine ring and the output vector of the state ring create timings for controlling the processor, for example, asynchronously, and these timings are input to the instruction decoder, for example.

Abstract: A synchronous induction motor has a stator having a main winding and an auxiliary winding; a rotor having a yoke, a permanent magnet embedded in the yoke and a secondary conductor provided in the vicinity of periphery of the yoke; and a starter. The starter has a starting capacitor connected in series with the auxiliary winding of the synchronous induction motor, and a switching unit to open/close a circuit from the starting capacitor to the auxiliary winding. The switching unit closes the circuit from the starting capacitor to the auxiliary winding when the synchronous induction motor is at rest, and opens the circuit after the synchronous induction motor is started. The synchronous induction motor is highly efficient and easy to re-start with low power consumption. The electric hermetic compressor equipped with the synchronous induction motor can perform with the similar effects.

Abstract: A one-way switch comprises a metal-oxide semiconductor field-effect transistor (MOSFET) and a driver. Source and drain of the transistor function as P-terminal and N-terminal of the one-way switch. The driver, such as comparator or amplifier, is used to detect the voltage difference between the source and drain of the MOSFET. When the voltage of the P-terminal is higher than that of the N-terminal, the driver 150 outputs a driving voltage to gate of the MOSFET to turn on the MOSFET. If the voltage of P-terminal is lower than that of the N-terminal, the driver 150 cannot output voltage to turn on the MOSFET, and the one-way switch is off. Therefore, the one-way switch has the characteristic of workings in one direction.

Abstract: A high frequency switch circuit including high frequency terminals which input/output a high frequency signal, high frequency semiconductor switch sections which are arranged on lines coupling the high frequency terminals, a DC potential isolating circuit which isolates the plurality of high frequency semiconductors switch sections from each other in a DC state, and DC potential transmission sections. Each DC potential transmission section couples a control side of an associated high frequency semiconductor switching section to at least one of an input side and an output side of another one of the plurality of high frequency semiconductor switch sections.

Abstract: A voltage switching circuit is disclosed which is constructed from a minimum number of transistors and prevents the threshold voltage margin from being lowered by causing high-voltage cutoff and supply voltage transfer functions heretofore performed by a single depletion transistor to be shared between two series-connected depletion transistors different in gate insulating film thickness or threshold voltage. Thus, without using enhancement transistors which involve an increase in pattern area a voltage switching circuit can be provided which is small in chip area, low in cost and high in yield and reliability and provides a stable operation with a low supply voltage which is impossible with one depletion transistor.

Abstract: Phase modulating systems and methods for modulating the phase of a signal are based on a digital control signal used to select one of a plurality of carriers having different phase angles. In order to reduce the number of short delays that have to be applied to the original signal for obtaining the plurality of carriers, it is proposed that delay elements are arranged in a matrix form. Alternatively, phase shifts are realized by digital frequency dividers instead of by delay elements. Further alternatively or in addition, part of the required delay is approximated or realized by an analog phase shifter. In case the phase modulating system is to be employed for modulating signals of different frequencies, the digital control signal is scaled with a factor associated to the respective frequency in order to change the addressing range for selecting a carrier from among the plurality of carriers.

Abstract: Electronic switch (1) with two switching states (ON, OFF) possesses at least one field effect switching transistor (Q1), input port (In) connected with source terminal (S), on which input signal (Vin) is present, output port (Out) connected with drain terminal, on which switched signal (Vout) is present, control port (Con) connected to gate terminal (G), on which is present signal (Vc) for controlling electronic switch (1) and switch apparatus (Sw), which creates the two switching states (ON, OFF) by means of a changing of control signal (Vc). Controlling signal (Vc), during at least one of the two switching states (ON, OFF) is, at least partially, formed by correction signal (Sc), which in turn is produced from input signal (Vin), so that the frequency dependent drop in voltage between the drain-source channel and the gate electrode of the field effect switching transistor (Q1) is at least partially compensated.

Abstract: Methods and apparatus for power managing IDE devices. A driver is coupled to a switch, the driver receiving a control signal from a computer system, the control signal indicating whether the computer system is in a power-save mode. The driver drives the switch which generates an output control signal to an IDE device. When the operating system detects that the computer system has been idle for a certain period of time, the operating system toggles the control signal that feeds into the driver which shuts off the switch so that power feeding to the IDE device is shut off.

Abstract: System and method for implementing a clock gater circuit are described. One embodiment is a clock gater circuit comprising an output clock signal generator electrically connected between a clock input for receiving an input clock signal and a clock output; a switch for selectively enabling or disabling generation of a clock signal by the output clock signal generator; and circuitry for causing a voltage level of the clock signal generated by the output clock signal generator to maintain a current voltage thereof responsive to a qualifier signal voltage level.

Abstract: An improved reclocker circuit and router cell are provided that are particularly useful when configured into a router matrix comprising a plurality of interconnected router cells. The improved reclocker circuit includes an integral N-to-1 multiplexer (MUX), wherein N is at least three. The improved router cell includes the reclocker/MUX circuit, a switch, and a fan-out circuit. A plurality of ports are coupled to the router cell circuitry, including an input port, an output port, a plurality of expansion input ports, and a plurality of expansion output ports. The improved router cell couples either the input port or one the expansion input ports to its output port, and it also couples the input port to each of the expansion output ports. By using the improved router cells in the design of a router matrix, jitter induced by the reclocker circuits is minimized.

Abstract: A transmission gate circuit with high impedance during power off conditions, which includes a first transistor coupled between a first terminal and a second terminal and a second transistor coupled between the first terminal and the second terminal. Also included is a control circuit configured to monitor voltages on the first terminal and on a first voltage source, the control circuit configured to couple the gates of the first and second transistors to a voltage that will keep the first and second transistors off during power off conditions.

Abstract: An apparatus comprising a reference circuit, a correction circuit and an output circuit. The reference circuit may be configured to generate a bias signal. The correction circuit may be configured to correct a bias voltage of the bias signal. The output circuit may be configured to generate an output current in response to the bias signal. The bias signal may be corrected in response to the bias voltage.

Abstract: A one-way switch comprises a metal-oxide semiconductor field-effect transistor (MOSFET) and a driver. Source and drain of the transistor function as P-terminal and N-terminal of the one-way switch. The driver, such as comparator or amplifier, is used to detect the voltage difference between the source and drain of the MOSFET. When the voltage of the P-terminal is higher than that of the N-terminal, the driver 150 outputs a driving voltage to gate of the MOSFET to turn on the MOSFET. If the voltage of P-terminal is lower than that of the N-terminal, the driver 150 cannot output voltage to turn on the MOSFET, and the one-way switch is off. Therefore, the one-way switch has the characteristic of workings in one direction.

Abstract: A computing system for implementing at least one electronic circuit with gain comprises at least one two-dimensional molecular switch array. The molecular switch array is formed by assembling two or more crossed planes of wires into a configuration of devices. Each device comprises a junction formed by a pair of crossed wires and at least one connector species that connects the pair of crossed wires in the junction. The junction has a functional dimension in nanometers, and includes a switching capability provided by both (1) one or more connector species and the pair of crossed wires and (2) a configurable nano-scale wire transistor having a first state that functions as a transistor and a second state that functions as a conducting semiconductor wire. Specific connections are made to interconnect the devices and connect the devices to two structures that provide high and low voltages.

Abstract: The invention provides a semiconductor integrated circuit that can be used as either a segment driver or a common driver, where the number of wires for scanning data is reduced so that the area of the wiring is reduced and the layout is simplified. The semiconductor integrated circuit includes: a plurality of data holding devices that each hold data that is inputted via a first terminal and output the data to a second terminal or hold data that is inputted via the second terminal and output the data to the first terminal in response to the operating mode and the scanning direction; a switching device that switches the connections of the plurality of data holding devices in response to the operating mode; and a plurality of selecting devices that select one out of data outputted from the terminals of the plurality of data holding devices and data outputted from the terminals of the plurality of data holding devices in response to the operating mode and the scanning direction.

Abstract: State retention registers for use in low-power standby modes of digital IC operation are provided, wherein: a differential circuit (M1−M3; M1−M4) is used to load the shadow latch from the normal functional latch; the signal (REST, RESTZ) used to restore data from the shadow latch to the normal functional latch is a “don't care” signal while the shadow latch is retaining the data during low-power standby mode; retained data from the shadow latch is restored to the normal functional latch via a transistor gate connected to a node (N10) of the shadow latch where the retained data is provided; a power supply (VDD) other than the shadow latch's power supply (VRETAIN) powers the data restore operation; and the normal functional latch is operable independently of the operational states of the high Vt transistors (M1, M2, M5 and M6; M3, M4, M5 and M6) used to implement the state retention functionality.

Abstract: A switching device (20) is formed to generate a ramp voltage by using a capacitor (48) formed on the semiconductor die (90) with the switching device (20). The switching device (20) drives a high-power device to conduct load currents for a load. The ramp voltage is used to gradually increase the drive that is applied to the high-power device in order to gradually increase the current conducted by the high-power device.

Abstract: A switching device (20) is formed to generate a ramp voltage by using a capacitor (48) formed on the semiconductor die (90) with the switching device (20). The switching device (20) drives a high-power device to conduct load currents for a load. The ramp voltage is used to gradually increase the drive that is applied to the high-power device in order to gradually increase the current conducted by the high-power device.

Abstract: A transmission gate circuit with high impedance during power off conditions, which includes a first transistor coupled between a first terminal and a second terminal and a second transistor coupled between the first terminal and the second terminal. Also included is a control circuit configured to monitor voltages on the first terminal and on a first voltage source, the control circuit configured to couple the gates of the first and second transistors to a voltage that will keep the first and second transistors off during power off conditions.

Abstract: A circuit for controlling the switching behavior of a field effect transistor (FET) or other power switch in a power supply or converter. The circuit includes an adaptive feedback loop which controls the switching operation of the FET through application of a gate drive signal to the device. The circuit is designed to turn the switching device on or off at the optimum time to reduce the stress and power losses associated with the switching action. The circuit includes a capacitor connected to the FET switch drain to sense the falling voltage across the switch. The adaptive gate drive circuit holds the FET switch off until the drain voltage sensed by the capacitor stops decreasing. At this time, the FET switch voltage is either zero (zero-voltage switching) or has reached the minimum value of its resonant ring (low-voltage switching).

Abstract: A bus switch has an n-channel bus-switch transistor between two buses and a p-channel pullup transistor. When power is disconnected from the bus switch, and one bus is hot and has a voltage above ground, this higher voltage is conducted to the gate and substrate of the p-channel pullup transistor. This biasing keeps the p-channel transistor turned off. When power is off, a connecting p-channel transistor connects the higher voltage on the hot bus to the p-channel gate node, while an inverting p-channel transistor connects the gate node to the substrate under the p-channel transistor. Inverting transistors receive an inverse enable signal and drive the gate node when power is applied, turning on the pullup transistor when the n-channel bus-switch transistor is off, and vice-versa. The gate node is fed back and applied to the gate of a source transistor that connects power to the substrate.

Abstract: A galvanically isolating circuit for converting input voltage which is in a first potential to an output variable which is in a second potential. The circuit is characterized by a first input terminal and a second input terminal for receiving the input voltage in the first potential, and a first output terminal and a second output terminal in the second potential for generating the output variable. The circuit is further characterized by a serial capacitance section for providing galvanic isolation between the input terminals and the output terminals, first polarity switching means, which are arranged to operationally connect the input terminals to the serial capacitance section by periodically reversing the polarity, and second polarity switching means, which ate arranged to operationally connect the serial capacitance section to output terminals by periodically reversing the polarity, in synchronism with the first polarity switching means.