Abstract: A power stage of quasi-complementary symmetry, including a common-source FET and a common-drain FET, with a reduced absorption of current under the conditions of high impedance of the output. The driving node of the upper (common-drain) transistor from is decoupled from the output node of the stage, preventing the current generator Id, which discharges the control node, from absorbing current from the load connected to the output stage, during a phase of high output impedance. This is preferably realized by using a field effect transistor which has its gate connected to the output node of the stage, and is connected to provide the current drawn from the discharge generator of the driving node of the upper common-drain transistor, absorbing it from the supply node VDD instead of absorbing it from the voltage overdriven node Vb. This alternative solution avoids excessive loading of the high-voltage supply, and is particularly useful when the overdriven node Vb drives multiple output stages.

Abstract: In a method and a circuit arrangement for driving semiconductor switches in a series circuit, in which a voltage limiting device is assigned to each semiconductor switch, the power losses of the voltage limiting devices are detected by a control equipment for equalizing the voltage distribution across the semiconductor switches. The control equipment generates modified control pulses for each semiconductor switch from a common control pulse on the basis of the detected power losses of the voltage limiting devices. By this means, the power loss of the voltage limiting devices is controlled to a minimum.

Abstract: In one aspect of the present invention a gate drive circuit is disclosed. The gate drive circuit includes a high voltage and low voltage energy source, a power transistor, a switching transistor, and a charging capacitor. The charging capacitor stores energy from the low voltage energy source. The gate drive circuit further includes a circuit that biases the switching transistor OFF which causes the low voltage energy stored in the capacitor to bias the power transistor ON to transfer high voltage energy to the load. The circuit additionally biases the switching transistor ON which biases the power transistor OFF to block the transfer of high voltage energy. Finally, a protection device is included to limit the power transistor voltage to a maximum voltage level in response to the power transistor being biased ON.

Abstract: A high side switch having a MOSgated power device has a control circuit which contains a control MOSFET which is connected between the gate and source of the MOSgated power device. The input signal to turn the power device on and off is connected to a level translator circuit which is, in turn, connected to an inverter circuit which drives the gate of the control MOSFET. The control MOSFET then prevents the turn on of the power MOSFET during the turn-off process. A high negative clamp voltage causes a higher di/dt reduction of current during turn off to shorten the turn-off time. The power MOS device cannot be turned on whenever V.sub.CC is low and the output voltage is negative.

Abstract: An integrated circuit, includes an output stage with an input which is coupled to a first and a second gate of an NMOS transistor and a PMOS transistor, respectively, and an output which is connected to a first and a second supply terminal via the PMOS transistor and the NMOS transistor, respectively. The output is coupled to the first gate via a series connection of a Miller capacitor and a switching circuit. The Miller capacitor limits the rate of increase of the voltage on the output, thus preventing interference. The switching circuit is rendered non-conductive ahead of the switching over from logic low to logic high. This prevents sudden discharging of the Miller capacitor which would otherwise cause interference itself.

Abstract: The invention concerns a circuit for limiting the maximum current to be supplied to a load through a power MOS, being an improvement of the limiting circuitry which uses an equalizing capacitor. The addition of circuitry with a one-way current flow between a terminal of the equalizing capacitor and the gate terminal of the power MOS is effective to lower the voltage across the capacitor and to speed up its charging process, thereby making the current limiting action expected from the circuit a timely one. The circuitry which limits current flow to one direction may include a second MOS of the same type as the power MOS. In this way, any deviations of the power MOS from its designed operation, e.g. due to its manufacturing process variation and thermal drift phenomena, can also be compensated.

Abstract: Plug-in electrical switching devices which allow a load device to be electrically connected to and disconnected from an electrical power source at either: (a) a switched outlet electrically coupled between the power source and the load and (b) a location in the vicinity of the load.

Abstract: A three-terminal insulated-gate power electronic device includes a first, bipolar power transistor and a second, insulated-gate transistor forming a darlington pair. The bipolar power transistor has a first electrode, a second electrode, and a control electrode respectively connected to a first electrode of the insulated-gate transistor and to a first external terminal of the three-terminal device, to a second external terminal of the three-terminal device, and to one second electrode of the insulated-gate transistor.

Abstract: A more efficient driver circuit for a power output stage, comprising a power driver stage activating the power output stage; a trigger circuit having an input stage and activating the power driver stage; and a power supply stage, wherein the input stage comprises a means for the potential-separated feeding of input signals, and the power supply stage comprises a means for the potential-separated feeding of electrical power. Such a driver circuit allows short signal propagation delays, is compact and small in size and has a wide clock frequency bandwidth.

Abstract: A free running relaxation oscillator is disposed on a semiconductor integrated circuit die for generating a frequency representative of the natural frequency of the die. The natural frequency of the die changes for different operating temperatures and voltages. An optimal speed may be determined at which the die will reliably operate by measuring the natural frequency. The die may be effectively graded and matched with a similar die by correlating the natural frequency of the die with the temperature and voltage values at which the natural frequency was measured for each die. A plurality of integrated circuit dice may be connected into a digital system, and the natural frequencies of each die may be monitored so as to optimize the system operating speed, reduce system power consumption without degrading performance, and/or increase the operating speed of a slower die by changing the temperature and/or operating voltage thereof.

Abstract: A control device for controlling a double gate semiconductor device having a second gate electrode for controlling transition from a thyristor operation to a transistor operation, and a first gate electrode for controlling transition from transistor operation to an ON/OFF operation, and for controlling a current passing from a collector electrode to an emitter electrode, includes a first gate control circuit for delaying a turn-off signal to the double gate semiconductor device and applying the turn-off signal to the first gate electrode.

Abstract: In a superconducting energy storage apparatus including an AC-DC converter unit, a superconducting coil, a quench protection unit and a mechanical type persistent current switch, a self-firing type thyristor switch is connected in parallel to the mechanical type persistent current switch to be first operated in the event of an occurrence of trouble in an associated electric power system, and a control unit generates an ON instruction signal for turning on the persistent current switch so as to immediately establish a persistent current mode.

Abstract: A low inductance triaxial semiconductor switching module. The module permits high power semiconductor switching devices to operated at high frequency but with low inductance. The module incorporates compositional, geometrical and electrical symmetry in connection with a triaxial terminal subassembly having coplanar contact areas. The terminal subassembly is readily fabricated and assembled into the module. The module also includes short internal leads, a special circumferential array of substrates subassemblies, and a circular circuit board having gate and Kelvin circuit patterns.

Abstract: A gate drive circuit for a bidirectional blocking MOSFET, the bidirectional blocking MOSFET being characterized in the source region is not shorted to the body region. In one embodiment, the gate drive circuit includes diodes connected between the source/drain regions and a charge pump, the charge pump generating a gate drive voltage applied to a gate of the bidirectional blocking MOSFET. In a second embodiment, a charge pump generates a gate drive voltage which is applied to the gate of the bidirectional blocking MOSFET, and is also connected to the source/drain regions through zener diodes. In the second embodiment, the potential applied to the gate of the bidirectional blocking MOSFET is limited to a zener diode drop above the lower of the voltages of the source/drain regions. In a fourth embodiment, a charge pump generates a floating gate drive voltage which is applied to gate of the bidirectional blocking MOSFET through first and second depletion mode MOSFETS.

Abstract: An apparatus for enabling an IC pin to function in a dual mode, which apparatus includes a first switch for coupling the IC pin to an input terminal when the IC pin operates in an input mode, and a charging circuit for sourcing current to the IC pin during a charging cycle of a timer mode. The inventive apparatus further includes a discharging circuit for sinking current from the IC pin during a discharging cycle of the timer mode. In one embodiment, the inventive apparatus further includes a comparator for generating an activation signal, the activation signal being activated when a potential at the IC pin equals or exceeds a predefined voltage in the timer mode. In another embodiment, the comparator is disabled during the input mode.

Abstract: A current limit circuit (10/40) for controlling a power transistor (12) has been provided. The current limit circuit includes circuitry which is responsive to a voltage appearing across the drain and source electrodes of the power transistor for providing an appropriate voltage at the gate electrode of the power transistor when a load is de-coupled from the power transistor. This has the effect of preventing excessive transient current when the load is subsequently coupled to the power transistor. Additionally, the current limit circuit includes circuitry for limiting the current flowing through the power transistor via a sense circuit when the load is coupled to the power transistor.

Abstract: A semiconductor memory device which is capable of reducing a delay in the conversion of an input chip enable signal having a TTL level, providing a quick chip enable access and avoiding an increase in current consumption despite the quick chip enable access. The semiconductor memory device in one embodiment includes an input buffer outputting a signal having a CMOS level in response to a chip enable signal having a TTL level, and having a plurality of transistors whose gate lengths are set to first dimensions, and a second input buffer activated in response to both another input signal having a TTL level and the signal having the CMOS level, and having a plurality of transistors whose gate lengths are set to second dimensions greater than the first dimensions.

Abstract: The present invention relates to an output driver circuit and in particular, an analog output driver circuit. Up to now, relays have been used in such driver circuits for the switching the outputs from output terminals (e.g., to ground) in the event of surges in the supply voltage. In accordance with the present invention, the relay is replaced by an electronic output switch element which has, free of control, a well-defined switch behavior. The output switch element is preferably a self-conducting field-effect transistor one connection of which is connected to the output line while its other connection is connected to ground.

Abstract: A bias control circuit and an associated method in an audio output amplifier provide slow turn-on or turn-off operation of a bias voltage generation circuit, using an external bypass capacitor. A slow rate in the turn-on and turn-off operations in such a bias voltage generation circuit prevents click or pop noises. In one embodiment, two bipolar transistors each responsive to the voltage on an external capacitor are provided to gradually increase the voltage of an output node, which can be used to drive the gate terminal of an MOS transistor in the bias voltage generation circuit. Alternatively, in another embodiment, an MOS inverter, which receives as input the voltage on bypass capacitor, is provided to divert current from a conventional bias circuit. The rate at which the MOS inverter diverts current from the conventional bias circuit controls the slew rate in the turn-off operation of the bias current.

Abstract: To avoid forward biasing the diodes within an N-channel transistor, the body and source of the N-channel transistor are switchably connected via a high-voltage FET. The gates of the N-channel transistor and high-voltage transistor are connected together so that both transistors are on or off simultaneously. When both transistors are on, the high-voltage transistor shorts the body and source of the N-channel transistor. When both transistors are off, the body and source of the N-channel transistor are disconnected and a third transistor couples the body to a reference potential. The N-channel transistor and high voltage transistor share a common body in a semiconductor substrate. The source of the N-channel transistor provides an output terminal for the circuit. A number of these devices, each connected to a different supply voltage, can be connected to the same output terminal and selectively energized to form a voltage multiplexer.

Abstract: A method of efficiently turning off inductive loads includes turning off a driving switch, monitoring a circuit output during turn-off, and activating a control circuit in response to an inductive flyback voltage at the output which turns on a recirculation switch and recirculates residual load current and clamps the output thereby substantially decreasing power dissipation during inductive load turn-off.

Abstract: Synthesizer radiating systems providing efficient wideband operation incorporate a radiating element (20a), such as a loop, dipole or whip, which has dimensions which are small relative to wavelength in the radiated frequency band. Energy dissipation is substantially reduced by cycling stored energy back and forth between a radiating element (20a) having a first reactance and a storage element (22a) having the same or opposite reactance, in order to achieve energy efficiency along the lines of a narrowband tuned-circuit antenna. Wideband operation is achieved by synthesizing a representation of an input waveform (at 28) by actively controlling (30) solid-state switching devices (24), responsive to rate control and direction control parameters, which are interactive with the energy transferred between the opposite reactances. Higher efficiencies are achieved by bipolar circuits providing separate positive and negative energy transfer paths between a radiating element and a storage element.

Abstract: This invention relates to a threshold switching device which exhibits negative differential resistance, and which is made by depositing a silicon dioxide film derived from hydrogen silsesquioxane resin between at least two electrodes and then applying a voltage above a threshold voltage across the electrodes.

Abstract: An electronic switch comprising: a switch device and an on-resistance (R.sub.ON) compensation feed-back control device; wherein said Ron compensation feed-back control circuit able to bypass the current flow of said switch device to said Ron compensation feed-back control circuit when said switch device is on.

Abstract: A backplane wiring scheme is provided for use in a hub of a packet data communications system. Line cards are connected to the backplane wiring arrangement in the hub, where each line card is a coupling to a network segment, a station or a to a bridge to other stations or segments. The connection is usually in either a ring or a bus topology, and increased flexibility, reduced power consumption, and easier implementation are provided by a unique wiring scheme. Each line card has a number of receive ports (e.g., N-1) and has two transmit ports, the transmit ports including a transmit-left port and a transmit-right port. The receive ports and transmit ports are arranged in a regular linear pattern on an edge of each of said line cards.

Abstract: A system for switching an antenna formed of multiple connected segments is set forth. The various segments are connected together by a switch means having, in the preferred embodiment, one or more FETs; a gate controlled terminal is connected with a bias circuit which is biased on or off by a bias circuit triggered to switch by light. The light is coupled through an optical fiber which directs light onto a portion of the bias circuit to cause operation. The bias circuit preferably includes a photo voltaic cell.