Abstract: An image pick-up unit includes an image pick-up device; and a plurality of optical filters which are cemented together in layers and positioned in front of the image pick-up device. At least two optical filters among the plurality of optical filters, which have different optical properties, are different in shape from each other.

Abstract: A multi-layered gate for use in a CMOS or CCD imager formed with a second gate at least partially overlapping it. The multi-layered gate is a complete gate stack having an insulating layer, a conductive layer, an optional silicide layer, and a second insulating layer, and has a second gate formed adjacent to it which has a second conductive layer that extends at least partially over the surface of the multi-layered gate. The multi-layered gate has improved insulation, thereby resulting in fewer shorts between the conductive layers of the two gates. Also disclosed are processes for forming the multi-layered gate and the overlapping gate.

Abstract: The invention generally relates to the use of poly-3,3?-dialkyl-2,2?:5?,2?-terthiophenes as charge transport materials or semiconductors in electrooptical, electronic or electroluminescent devices, and to charge transport and semiconducting components and devices comprising poly-3,3?-dialkyl-2,2?:5?,2?-terthiophenes.

Abstract: An electron transfer device is implemented in a structure which is readily capable of achieving charge transfer cycle frequencies in the range of several hundred MHz or more and which can be formed by conventional semiconductor integrated circuit manufacturing processes. The device includes a substrate having a horizontal extent and a pillar on the substrate extending from the substrate vertically with respect to the horizontal extent of the substrate. The pillar is formed to vibrate laterally with respect to the vertical length of the pillar at a resonant frequency which can be several hundred MHz. Drain and source electrodes extend from the substrate vertically with respect to the horizontal extent of the substrate, and have innermost ends on opposite sides of the pillar. The pillar is free to vibrate laterally back and forth between the innermost ends of the drain and source electrodes to transfer charge between the electrodes.

Abstract: A row driver according to an embodiment drives a shared row-reset bus to one of a select voltage and a boosted voltage to select a row for readout and to reset the pixels in the row, respectively. The boosted voltage is higher than the select voltage. A row select circuit includes PMOS transistors through which a path may be opened between a supply line carrying the select voltage and the bus. A reset enable circuit includes PMOS transistors through which a path may be opened between a supply line carrying the boosted voltage and the bus. In order to prevent a parasitic diode leakage between the two supply lines during reset, the n-wells of the PMOS transistors in the row select circuit may be coupled to the supply line carrying the boost voltage.

Abstract: A solid state image pickup device of high integration, high photoelectric conversion and high transfer performances is made of: a plurality of photoelectric conversion elements disposed in a matrix shape on the surface of a semiconductor substrate, the photoelectric conversion elements in an even column being shifted by about a half of a photoelectric conversion element pitch in the even column from the photoelectric conversion elements in an odd column, and the photoelectric conversion elements in an even row being shifted by about a half of a photoelectric conversion element pitch in the even row from the photoelectric conversion elements in an odd row; a plurality of transfer channel regions formed on the semiconductor substrate, each being disposed near a corresponding photoelectric conversion element column, having a stripe plan shape, and extending and weaving along the column direction; and a plurality of transfer electrodes traversing the transfer channel regions and extending as a whole in the row di

Abstract: A charging sensor is provided to detect charging signal during the manufacturing process of integrated circuits and various semiconductor devices. In one embodiment, the charging sensor includes a charging-sensitive insulator layer and complementary elements designed to effectively provide an indicative potential drop across the charging sensitive insulator.

Abstract: A solid-state imaging device of the present invention includes a vertical charge transfer portion and a horizontal charge transfer portion that is connected to at least one end of the vertical charge transfer portion. The vertical charge transfer portion includes a vertical transfer channel region and a plurality of vertical transfer electrodes formed on the vertical transfer channel region. The horizontal charge transfer portion includes a horizontal transfer channel region, a plurality of first horizontal transfer electrodes formed on the horizontal transfer channel region, and a plurality of second horizontal transfer electrodes arranged between the plurality of first horizontal transfer electrodes. A potential below the first horizontal transfer electrode is higher than a potential below the second horizontal transfer electrode that is arranged adjacent to the first horizontal transfer electrode and backward along a transfer direction with respect to the first horizontal transfer electrode.

Abstract: To transfer signal charges at high speed with small noise, there is provided a charge transfer apparatus including a semiconductor substrate of one conductivity type, a charge transfer region of a conductivity type opposite to that of the semiconductor substrate that is formed in the semiconductor substrate and joined to the semiconductor substrate to form a diode, a signal charge input portion which inputs a signal charge to the charge transfer region, a signal charge output portion which accumulates the signal charge transferred from the charge transfer region, and a plurality of independent potential supply terminals which supply a potential gradient to the semiconductor substrate, wherein the signal charge in the charge transfer region is transferred by the potential gradient formed by the plurality of potential supply terminals.

Abstract: Isolation methods and devices for isolating pixels of an image sensor pixel. The isolation structure and methods include forming a biased gate over a field isolation region and adjacent a pixel of an image sensor. The isolation methods also include forming an isolation gate over substantial portions of a field isolation region to isolate pixels in an array of pixels.

Abstract: A semiconductor detector of electromagnetic radiation which utilizes a dual-purpose electrode which extends significantly beyond the edge of a photodiode. This configuration reduces the sensitivity of device performance on small misalignments between manufacturing steps while reducing dark currents, kTC noise, and “ghost” images. The collection-mode potential of the dual-purpose electrode can be adjusted to achieve charge confinement and enhanced collection efficiency, reducing or eliminating the need for an additional pinning layer. Finally, the present invention enhances the fill factor of the photodiode by shielding the photon-created charge carriers formed in the substrate from the potential wells of the surrounding circuitry.

Abstract: A semiconductor structure includes a base layer of a first conductivity type, a first layer of the first conductivity type arranged on the base layer and having a dopant concentration that is lower than a dopant concentration of the base layer, and a second layer of a second conductivity type being operative with the first layer in order to form a transition between the first conductivity type and the second conductivity type. A course of a dopant profile at the transition between the base layer and the first layer is set such that in an ESD case a space charge region shifted to the transition between the base layer and the first layer reaches into the base layer.

Abstract: A charge coupled device of the present invention includes a charge transfer region layer and a gate insulation film that are formed in the stated order on a semiconductor substrate, first gate electrodes formed at predetermined spaces on the gate insulation film, and second gate electrodes arranged between the first gate electrodes with at least silicon oxide films being interposed therebetween. Each silicon oxide film has constricted portions where the silicon oxide film is in contact with the gate insulation film, and electric insulation films are formed on the constricted portions so as to form sidewalls. This configuration decreases the charge transfer efficiency and increases a dielectric breakdown voltage between gate electrodes. Thus, a charge coupled device having high performance and high dielectric strength is provided.

Abstract: A solid state image device capable of improving charge transfer efficiency by reducing the interval between adjacent gate electrodes and reducing power consumption by reducing parasitic capacitances while obtaining a signal having small noise is provided. This solid state image device comprises a first gate electrode, formed on a gate insulator film, having a substantially flat upper surface and a second gate electrode formed on the gate insulator film through an insulator film having a thickness smaller than the minimum limit dimension of lithography to be adjacent to the first gate electrode without overlapping the first gate electrode.

Abstract: A solid-state image pickup device including a matrix of unit pixels, each unit pixel including five transistors, a plurality of horizontal signal lines wired on a row-by-row basis and a vertical signal line commonly wired for the plurality of the horizontal signal lines. A reset transistor resets a floating diffusion region FD, and the reset level of the reset transistor is output to the horizontal signal lines through an amplifying transistor. In succession, a signal charge of a photodiode is read out into the floating diffusion region FD through a read out transistor, and the signal level based on the signal charge is output to the horizontal signal lines through the amplifying transistor.

Abstract: A charge transfer element comprising a reverse conductive type well formed on the surface of one conductive type semiconductor substrate, the one conductive type channel region extending in one direction relative to the well, a transfer electrode formed intersecting the channel region, a floating diffusion region formed continuous from the channel region, and an output transistor having a gate connected to the floating diffusion region. In a region where the output transistor is formed, the dopant density profile in the depth direction of the semiconductor substrate exhibits the maximum value relative to a middle region.

Abstract: In a solid state image sensor, tranfer electrodes are formed by selectively etch-removing a single layer of conducting electrode material at a plurality of first regions which divide the single layer of conducting electrode material in a row direction for each one pixel. A patterned mask is formed to cover the first regions and the single layer of conducting electrode material but to expose the single layer of conducting electrode material at a second region above each of the photoelectric conversion sections, and the single layer of conducting electrode material is selectively etch-removed using the patterned mask as a mask. Thereafter, a first conductivity type impurity and a second conductivity type impurity are ion-implanted using the patterned mask and the single layer of conducting electrode material as a mask, to form the photoelectric conversion section at the second region.

Abstract: A CCD type solid state image pickup device having: a number of photoelectric conversion elements formed in and on the semiconductor substrate in a matrix configuration of rows and columns; a plurality of VCCDs each having a vertical channel region formed along each column of the photoelectric conversion elements, and charge transfer electrodes formed above the vertical channel region; an HCCD having a horizontal channel region coupled to one ends of the VCCDs, and charge transfer electrodes formed above the horizontal channel region; a floating diffusion formed in the semiconductor substrate and coupled to one end of the HCCD; and an input gate electrode of an output amplifier having a portion extending at least near to the floating diffusion, and the input gate electrode being thinner than the charge transfer electrodes.

Abstract: A pixel cell having two capacitors connected in series where each capacitor has a capacitance approximating that at of the periphery capacitors and such that the effective capacitance of the series capacitors is smaller than that of each of the periphery capacitors. The series-connected capacitors are coupled to the floating diffusion (FD) region for receiving “surplus” charge from the FD region during saturation conditions.

Abstract: An integrated memory circuit of the type of an NROM memory includes recessed bit lines formed of a material having a low ohmic resistance. By recessing the bit lines with respect to the semiconductor substrate surface of a peripheral controlling circuit for an array of memory cells allows to form the word line lithography on a perfect or almost perfect plane so that the word line formation results in a production with higher yield and, therefore, lower costs for the individual integrated memory circuit.

Abstract: A solid-state imaging device includes a plurality of vertical charge transferring portions, and a horizontal charge transferring portion connected to at least one end of the vertical charge transferring portion.

Abstract: A doping method includes the step of attaching molecules or clusters to the surface of a semiconductor substrate to enable charge transfer from the molecules or clusters to the substrate surface, thereby inducing carriers underneath the substrate surface. A semiconductor device is fabricated through attachment of molecules or clusters to the surface of a semiconductor substrate. The attachment enables charge transfer from the molecules or clusters to the substrate surface to induce carriers underneath the substrate surface.

Abstract: White defects caused by a dark-current of a solid-state imaging device is reduced by effectively bringing out gettering capability of a buried getter sink layer. A buried getter sink layer is formed by introducing to the semiconductor substrate a substance of a second element which is a congener of a first element composing a semiconductor substrate, a crystal growth layer is formed by crystal growing a substance of the first element on a surface of the semiconductor substrate, and a solid-state imaging element is formed inside and on the crystal growth layer at a lower temperature than that in the case of forming an extrinsic getter sink layer by introducing a substance of a third element of a different group from the first element on a back surface of the semiconductor substrate.

Abstract: P type well regions 31 and 32 are formed in N type well regions 21 and 22 respectively. The N type well regions 21 and 22 are formed separately each other. Charge transfer MOS transistors M2 and M3 are formed in the P type well regions 31 and 32 respectively. Thus, parasitic thyristor causing latch-up is nor formed.

Abstract: An improved imaging array (and corresponding method of operation) includes a plurality of heterojunction thyristor-based pixel elements disposed within resonant cavities formed on a substrate. Each thyristor-based pixel element includes complementary n-type and p-type modulation doped quantum well interfaces that are spaced apart from one another. Incident radiation within a predetermined wavelength resonates within the cavity of a given pixel element for absorption therein that causes charge accumulation. The accumulated charge is related to the intensity of the incident radiation. The heterojunction-thyristor-based pixel element is suitable for many imaging applications, including CCD-based imaging arrays and active-pixel imaging arrays.

Abstract: A high-density flash EEPROM (Electrically Erasable Programmable Read Only Memory) unit cell and a memory array architecture including the same are disclosed. The flash EEPROM unit cell comprises a substrate on which field oxide layers are formed for isolating unit cells, a floating gate dielectric layer formed between the adjacent field oxide layers, wherein the floating gate dielectric layer includes a first dielectric layer and a second dielectric layer which are connected in parallel between a source and a drain formed on the substrate, and the thickness of the first dielectric layer is thicker than the second dielectric layer, a floating gate formed on the floating gate dielectric layer, a control gate dielectric layer formed on the floating gate; and a control gate formed on the control gate dielectric layer.

Abstract: A semiconductor energy detector having a region for detection and charge accumulation/transfer where a two-dimensional pixel array is formed on a surface of a semiconductor substrate on which energy rays become incident, is characterized in that the region for detection and charge accumulation/transfer comprises a plurality of transfer electrodes formed in each pixel, and an excess charge removing means arranged in correspondence with one of the transfer electrodes in each pixel.

Abstract: A multi-layered gate for use in a CMOS or CCD imager formed with a second gate at least partially overlapping it. The multi-layered gate is a complete gate stack having an insulating layer, a conductive layer, an optional silicide layer, and a second insulating layer, and has a second gate formed adjacent to it which has a second conductive layer that extends at least partially over the surface of the multi-layered gate. The multi-layered gate has improved insulation, thereby resulting in fewer shorts between the conductive layers of the two gates. Also disclosed are processes for forming the multi-layered gate and the overlapping gate.

Abstract: A CCD type solid state image pickup device having: a number of photoelectric conversion elements formed in and on the semiconductor substrate in a matrix configuration of rows and columns; a plurality of VCCDs each having a vertical channel region formed along each column of the photoelectric conversion elements, and charge transfer electrodes formed above the vertical channel region; an HCCD having a horizontal channel region coupled to one ends of the VCCDs, and charge transfer electrodes formed above the horizontal channel region; a floating diffusion formed in the semiconductor substrate and coupled to one end of the HCCD; and an input gate electrode of an output amplifier having a portion extending at least near to the floating diffusion, and the input gate electrode being thinner than the charge transfer electrodes.

Abstract: In a solid-state image pick-up device in which a photoelectric converting section formed on a semiconductor substrate and a gate oxide film of a transfer path of a charge coupled device (CCD) which is close to the photoelectric converting section are constituted by a laminated film comprising a silicon oxide film (SiO) and a silicon nitride film (SiN), the gas oxide film has a single layer structure in which at least an end on the photoelectric converting section side of the gate oxide film does not contain the silicon nitride film.

Abstract: The present invention provides a solid-state image pickup apparatus which is able to easily discharge signal charges in a signal accumulating section and which is free from reduction in the dynamic range of the element, thermal noise in a dark state, an image-lag and so forth even if the pixel size of the MOS solid-state image pickup apparatus is reduced, the voltage of a reading gate is lowered and the concentration in the well is raised. The solid-state image pickup apparatus according to the present invention incorporates a p-type silicon substrate having a surface on which a p+ diffusion layer for constituting a photoelectric conversion region and a drain of a reading MOS field effect transistor are formed. A signal accumulating section formed by an n-type diffusion layer is formed below the p+ diffusion layer. A gate electrode of the MOS field effect transistor is, on the surface of the substrate, formed between the p+ diffusion layer and the drain.

Abstract: A method for forming edge-defined structures with sub-lithographic dimensions which are used to further form conduction channels and/or storage structures in memory cells. Sacrificial silicon nitride islands are deposited at low temperatures and then patterned and etched by high resolution etching techniques. Polysilicon is next deposited over the sacrificial silicon nitride islands and directionally etched to form edge-defined polysilicon dot and strip structures which are about one tenth the minimum feature size. The edge-defined polysilicon strips and dots are formed between the source and drain region of an NMOS device. Subsequent to the removal of the sacrificial silicon nitride islands, the edge-defined polysilicon strips and dots are used to mask a threshold voltage implantation in a conventional CMOS process. A conduction channel and two adjacent potential minimum dots are formed after the removal of the edge-defined polysilicon strips and dots.

Abstract: A solid-state image sensing device includes a semiconductor substrate, insulating film, electrode/interconnection, light-shielding film, planarizing film, microlens, and film thickness measuring pattern. The substrate has an image sensing region where elements including photodiodes are formed and a monitor region for film thickness measurement. The insulating film is formed on the entire substrate surface. The electrode/interconnection is selectively formed in the image sensing region on the substrate via the insulating film. The light-shielding film having an opening corresponding to a photodiode is formed in the image sensing region on the electrode/interconnection via the insulating film. The planarizing film is formed in the image sensing region on the light-shielding film and insulating film. The microlens is formed on the planarizing film in correspondence with the photodiode and opening.

Abstract: A charge-coupled device (CCD) includes first-level transfer electrodes and second-level transfer electrodes alternately arranged along a transfer channel, wherein charge storage sections underlying the first-level transfer electrodes have a larger width than barrier sections underlying the second-level transfer electrodes. First and second interconnect lines supply two-phase driving signals to the transfer electrodes. Contact plugs connecting the first interconnect line to the transfer electrodes and contact plugs connecting the second interconnect line are located at opposite sides with respect to the center line of the transfer channel.

Abstract: The present invention provides a power-thrifty IT-CCD having a charge transfer electrode area thinned for improving the light reception efficiency of a photoelectric conversion section and being capable of executing high-speed and high-sensitivity transfer without lowering withstand voltage between charge transfer electrodes. A first insulation film is formed on the surface of a silicon substrate, and inter-electrode insulation films made of silicon oxide films and charge transfer electrodes made of polycrystalline silicon films are formed on the surface of the first insulation film. The inter-electrode insulation films are formed from side walls of the polycrystalline silicon films.

Abstract: An imaging device having a CMOS photosensor array for capturing images is described in which the array is also used to input programming and/or data used to control the imaging operations. The data-input can be based upon variations in light color, value, intensity, and patterning, or any combinations of the foregoing, for the download of information to the device.

Abstract: A silicon carbide n channel MOS semiconductor device is provided which includes a silicon carbide substrate including a p base region, an n30 source region and an n+ drain region, a gate insulating film formed on a surface of the p base region, a gate electrode provided on the gate insulating film, and first and second main electrodes that allow current to flow therebetween, wherein a p− channel region is formed in a surface layer of the p base region right under the gate insulating film, such that the effective acceptor concentration measured in the vicinity of an interface between the p base region and the gate insulating film is in a range of 1×1013 to 1×1016 cm−3.

Abstract: The invention relates to a CCD of the buried-channel type comprising a charge-transport channel in the form of a zone (12) of the first conductivity type, for example the n-type, in a well (13) of the opposite conductivity type, in the example the p-type. In order to obtain a drift field in the channel below one or more gates (9, 10a) to improve the charge transfer, the well is provided with a doping profile, so that the average concentration decreases in the direction of charge transport. Such a profile can be formed by covering the area of the well during the well implantation with a mask, thereby causing fewer ions to be implanted below the gates (9, 10a) than below other parts of the channel. By virtue of the invention, it is possible to produce a gate (10a) combining a comparatively large length, for example in the output stage in front of the output gate (9) to obtain sufficient storage capacity, with a high transport rate.

Abstract: A fast frame-rate imaging device is produced by a attaching a fiberoptic block to an otherwise ordinary and inexpensive CCD. A part of the fiberoptic block is occluded so as to darken a majority of the active imaging photocells. The CCD imaging device is operated at near its maximum horizontal and vertical clock rates, but multiple image frames are defined within the one previous active photocell array field. The added dark areas in the optical field protect the recent frames still in transit within the active array area from being double exposed and thus corrupted. The serial output of the thus-modified CCD imaging device is reinterpreted to include more frames than originally at a multiple equal to the original array dimension divided by the new array dimension (m·n/m′·n′). Such a modified CCD array uses only one-fourth of the original active area, and is operable at a multiple of the original frame rate.

Abstract: A multi-layered gate for use in a CMOS or CCD imager formed with a second gate at least partially overlapping it. The multi-layered gate is a complete gate stack having an insulating layer, a conductive layer, an optional silicide layer, and a second insulating layer, and has a second gate formed adjacent to it which has a second conductive layer that extends at least partially over the surface of the multi-layered gate. The multi-layered gate has improved insulation, thereby resulting in fewer shorts between the conductive layers of the two gates. Also disclosed are processes for forming the multi-layered gate and the overlapping gate.

Abstract: A charge transfer device is disclosed wherein three pixel rows are arranged adjacently to each other. First to third pixel rows are arranged adjacently to each other, and the charge transfer device includes a first charge transfer element for reading out and transferring signal charges generated in the first pixel row and a second charge transfer element for reading out and transferring signal charges generated in the second and third pixel rows. Second readout electrodes for reading out signal charges generated in the second pixel row into the second charge transfer element are provided with one electrode placed between adjacent pixels of the third pixel row.

Abstract: In a charge pump device, occurrence of a latch up can be prevented and current capacity can be increased. An N-type epitaxial silicon layer is formed on a P-type single crystalline silicon substrate, P-type well regions are formed in the N-type epitaxial silicon layer separated from each other, and P-type lower isolation layers and P-type upper isolation layers are formed between the P-type well regions. Then a charge transfer MOS transistor is formed in each of the P-type well regions. The P-type single crystalline silicon substrate is biased to a ground potential or a negative potential.

Abstract: P-type ion implantation is done in N well 15, so as to form a charge drain control layer 17 and form a photodiode N well 16 and OFD drain 5, the result being that, even if there is variation in the potential of the photodiode N well 16 making up the photodiode, because the variation in the potential of the charge drain control layer 17 is in the same direction as the potential of the photodiode N well 16, so that variation does not occur in the maximum amount of electrical charge that can be accumulated, the result being that there is no variation in the signal in the saturation condition.

Abstract: A semiconductor device having a large-area silicide layer and fabrication method is provided. A semiconductor device, consistent with one embodiment of the invention, includes a silicon substrate, a gate insulating layer disposed over the silicon substrate, a gate electrode disposed over the gate insulating layer, and at least one active region disposed adjacent the gate electrode. Formed over the active region and in contact with the insulating layer is a silicide layer. The active region may, for example, be a source/drain region. The silicide layer generally has a surface area which is larger than that of conventional silicide layers. This, for example, reduces the resistance of the active regions of the semiconductor device and enhances device performance.

Abstract: An exposure control method for an image pickup apparatus with a CMOS image sensor comprises the steps: opening an mechanical shutter to guide incident light falling on the CMOS image sensor; generating a signal for eliminating residual image data, and initiating exposure controlled by an electronic shutter in the CMOS image sensor; generating an instruction for closing the mechanical shutter before the exposure finished; beginning to close the mechanical shutter after the exposure finished; and starting to read out the image data acquired as soon as the mechanical shutter has been closed completely.

Abstract: A charge-coupled device includes a plurality of cells for forming the charge-coupled device, each of the cells capable of retaining charge a transfer mechanism within the charge-coupled device for moving charge through the plurality of cells, an output region for receiving charge moved through the plurality of cells under control of the transfer mechanism; a floating diffusion to receive charge moved across the output region; a reset gate to remove charge from the floating diffusion and reset the floating diffusion to a reference voltage level; and a capacitance control gate adjacent to the floating diffusion for canceling capacitance coupling of the reset gate. A capacitance control gate covers a portion of the floating diffusion. The capacitance control gate voltage is adjusted to alter the capacitance of the floating diffusion. The capacitance control gate is clocked opposite that of the reset gate to cancel the capacitive effects of the reset gate.

Abstract: A coating liquid for forming an organic layer of an organic EL element by a printing method, comprising at least one organic solvent showing a vapor pressure of 500 Pa or less at a temperature for forming the organic layer, an organic EL element formed by using the coating liquid and a method of manufacturing the same.

Abstract: An active pixel cell includes electronic shuttering capability. The cell can be “shuttered” to prevent additional charge accumulation. One mode transfers the current charge to a storage node that is blocked against accumulation of optical radiation. The charge is sampled from a floating node. Since the charge is stored, the node can be sampled at the beginning and the end of every cycle. Another aspect allows charge to spill out of the well whenever the charge amount gets higher than some amount, thereby providing anti blooming.

Abstract: An image input device or a solid-state image sensing device using a CCD linear sensor includes a main sensor array and a sub sensor array. A transfer register for the sub sensor array is provided with charge sweep means for sweeping away unnecessary charges. Thus, only signals in the main sensor array are selectively read out without being affected by signals in the sub sensor array.

Abstract: A semiconductor well layer of second conductive type formed at the surface of a semiconductor substrate of first conductive type. First device isolation areas formed at the surface of the semiconductor well layer. A plurality of photoelectric conversion sections are formed in the first device isolation areas, and an output circuit section is formed at a second device isolation area in contact with the first device isolation areas. The second device isolation area has an impurity density higher than that of the semiconductor well layer. Further, a plurality of third device isolation areas of second conductive type having an impurity density higher than that of the semiconductor well layer are formed in contact with the second device isolation area, between a horizontal charge transfer section and a unnecessary charge discharging section.