Abstract: A method of manufacturing a solid-state image sensing device in which a light-sensitive sensor part for photoelectric transfer is formed on the surface of a substrate and a light shielding film for preventing light from being incident on the substrate except the light-sensitive sensor part is formed is provided. First, a transfer electrode is formed on the substrate via an insulating film and after an interlayer insulating film for covering the transfer electrode is further formed, a planarized film for covering the interlayer insulating film is formed. Next, only the location of the planarized film to be a light shielding area for forming a light shielding film is selectively etched, a concave portion is formed and a groove deep enough to reach the vicinity of the surface of the substrate is formed by etching the planarized film over the periphery of the light-sensitive sensor part and near the side of the transfer electrode.

Abstract: Passivation for capacitive sensor circuits, which overlies the capacitive sensor electrodes and is normally conformal to the electrodes and the underlying interlevel dielectric, is planarized by forming a layer of flowable oxide over the electrodes before forming the passivation. The flowable oxide, which is preferably very thin over the electrodes to minimize loss of sensitivity, provides a substantially planar upper surface, so that passivation formed on the flowable oxide is also substantially planar. Alternatively, a deposited oxide planarized by chemical mechanical polishing may be employed to planarize the surface on which a passivation stack is formed. The planarized passivation provides markedly improved scratch resistance.

Abstract: An image sensor capable of preventing the degradation of pinned photodiodes and the generation of leakage current between neighboring pinned photodiodes is provided. The disclosed image sensor contains a plurality of pixel units, each pixel unit having a photodiode region. The image sensor includes a semiconductor substrate of a first conductivity type; a device isolation layer formed in the semiconductor substrate; a field stop layer formed beneath the device isolation layer; a trench formed in the semiconductor substrate, wherein the trench surrounds the photodiode region; a first doping region of the first conductivity type formed beneath the surface of the semiconductor substrate and beneath the surfaces of the trench; an insulating member filling the trench; and a second doping region of a second conductivity type formed in the semiconductor substrate under the first doping region.

Abstract: A solid state imaging pickup device with a single-layer electrode structure which eliminates the release area at the terminal part of the charge transfer electrodes by surrounding the charge transfer electrodes with a dummy pattern, or with a pattern formed by connecting the charge transfer electrodes of a certain phase with each other at the outermost periphery. Surrounding the charge transfer electrode improves embedding performance when an insulating film is re-flowed for flattening inter-electrode gaps. This enables formation of a good metal wire or shielding film with no step-cut, thus improving the reliability of a solid state imaging pickup device.

Abstract: Increased pixel density and increased sensitivity to blue light are provided in a charge couple device employing sidewall and surface gates.

Abstract: A charge transfer device is provided which is capable of reducing a reset field-through noise in a stable manner without being affected by characteristics of transistors and without occurrence of a mustache-shaped pulse-like noise. The charge transfer device is made up of a floating diffusion region used to convert a signal charge transferred from a CCD (Charge Coupled Device) into a voltage, resetting unit used to eject the signal charge accumulated in the floating diffusion region in response to a reset pulse, a first stage source follower used to current-amplify the voltage and second stage source follower in which load is changed in response to the reset pulse and which is used to current-amplify an output voltage of the first stage source follower.

Abstract: A photon detector is obtained by using the intersubband absorption mechanism in a modulation doped quantum well(s). The modulation doping creates a very high electric field in the well which enables absorption of input TE polarized light and also conducts the carriers emitted from the well into the modulation doped layer from where they may recombine with carriers from the gate contact. Carriers are resupplied to the well by the generation of electrons across the energy gap of the quantum well material. The absorption is enhanced by the use of a resonant cavity in which the quantum well(s) are placed. The absorption and emission from the well creates a deficiency of charge in the quantum well proportional to the intensity of the input photon signal. The quantity of charge in the quantum well of each detector is converted to an output voltage by transferring the charge to the gate of an output amplifier.

Abstract: A solid-state imaging device having contacts for a charge sweeping component or the like, with which increases in dark current can be suppressed while increases in contact resistance and the production of alloy spikes can be prevented, and a method for manufacturing this device. A solid-state imaging device has a charge accumulator for producing and accumulating signal charges when light is received, and a charge transfer component for transferring these signal charges, including a conductive layer 18 formed on a substrate 10, such as a silicon layer or metal wiring; an insulating film 21 formed over the conductive layer 18; an opening CH formed over the insulating film 21 and leading to the conductive layer 18; and a wiring layer 34 composed of aluminum containing copper in an amount between 0.4 and 5 wt %, formed at least inside the opening CH contiguously with the surface of the conductive layer 18.

Abstract: A solid-state imaging device includes a semiconductor substrate including a surface region of a second conductivity type, and plural unit pixels arranged in a matrix form on the surface region of the second conductivity type. Each of the unit pixels includes a first semiconductor region of a first conductivity type separated by a preset distance from the surface of the surface region in the depth direction and accumulates signal charges obtained by photo-electrical conversion of input light, and a gate electrode formed above the surface region, adjacent to the first semiconductor region and controlling readout of the signal charge accumulated in the first semiconductor region, end portions of the gate electrode and the first semiconductor region separated by a preset distance in a horizontal direction. Thus, the signal charge can be easily read-out and occurrence of thermal noise at the dark time, dark current noise, image-lag can be suppressed.

Abstract: An active pixel cell includes electronic shuttering capability. The cell can be “shuttered” to prevent additional charge accumulation. One mode transfers the current charge to a storage node that is blocked against accumulation of optical radiation. The charge is sampled from a floating node. Since the charge is stored, the node can be sampled at the beginning and the end of every cycle. Another aspect allows charge to spill out of the well whenever the charge amount gets higher than some amount, thereby providing anti blooming.

Abstract: There is provided a solid state imaging device using a MOS image sensor of a threshold voltage modulation system employed in a video camera, an electronic camera, an image input camera, a scanner, a facsimile, or the like. In configuration, in the solid state imaging device that comprises a photo diode formed in a second semiconductor layer 15a of opposite conductivity type in a first semiconductor layer 12 and 32 of one conductivity type, and a light signal detecting insulated gate field effect transistor formed in a fourth semiconductor layer 15b of opposite conductivity type in a third semiconductor layer 12 of one conductivity type adjacently to the photo diode, a carrier pocket 25 is provided in the fourth semiconductor layer 15b, and a portion of the first semiconductor layer 12, 32 under the second semiconductor layer 15a is thicker than a portion of the third semiconductor layer 12 under the fourth semiconductor layer 15b in a depth direction.

Abstract: A barrier area is located adjacent a horizontal transfer area and spaced from a field insulating area. The barrier area includes an insulating layer and a conductor extending from the horizontal transfer layer over the surface of a semiconductor substrate, a barrier layer of a second conductivity type formed under the surface of the semiconductor substrate and adjacent a first impurity layer of a first conductivity type of the horizontal transfer area, and a second impurity layer extending from the horizontal transfer area and formed under the barrier layer. A discharge area is located between the barrier area and the field insulating area.

Abstract: A solid state imaging apparatus includes a detection capacitor storing a signal charge, and an output amplifier including a plurality of transistors, and outputting the signal charge stored in the detection capacitor as a voltage signal. A gate electrode of one of the plurality of transistors as an input transistor is connected to the detection capacitor. Also, the plurality of transistors other than the input transistor has a thinner gate insulating film than the input transistor.

Abstract: A single phase charge-couple device (CCD) transfer device in a substrate of a first conductivity type. The device includes a gated region and a photo-diode region. The gated region includes a gated part and a gate electrode insulatively spaced over the gated part. The photo-diode region includes first, second, and third diode sub-regions. The second diode sub-region is formed of a second conductivity type; the third diode sub-region is formed of the first conductivity type in the second diode sub-region; and the first diode sub-region is formed of the first conductivity type in the second diode sub-region. The first and third diode sub-regions contain different dopant concentrations. The gated part is either a buried channel gated part or a surface channel gated part. The buried channel gated part includes a channel of the second conductivity type and a first gated sub-region formed in the channel.

Abstract: Object: To provide a solid-state imaging device having contacts for a charge sweeping component or the like, with which increases in dark current can be suppressed while increases in contact resistance and the production of alloy spikes can be prevented, and to provide a method for manufacturing this device.

Abstract: It is known in charge coupled devices to use a dual layer of silicon oxide and silicon nitride as the gate dielectric. Since silicon nitride is practically impermeable to hydrogen, the nitride layer is usually provided with openings through which hydrogen can penetrate up to the surface of the silicon body during the annealing step carried out for passivating the surface. The openings in the nitride layer are provided by a known method, with gates in a first poly layer serving as a mask, in that the nitride is removed from between these gates and an oxidation step is subsequently carried out. According to the invention, the openings in the nitride layer are formed by means of a separate mask (20), such that the edges of the openings (9) in the nitride layer (8) lie at some distance from the edges of the gates.

Abstract: A CMOS imager having an improved signal to noise ratio and improved dynamic range is disclosed. The CMOS imager provides improved charge storage by fabricating a storage capacitor in parallel with the photocollection area of the imager. The storage capacitor may be a flat plate capacitor formed over the pixel, a stacked capacitor or a trench imager formed in the photosensor. The CMOS imager thus exhibits a better signal-to-noise ratio and improved dynamic range. Also disclosed are processes for forming the CMOS imager.

Abstract: A semiconductor die with an imager sensor on an integrated circuit (IC) is mated directly to a substrate, such as a printed circuit board or any traditional chip carrier. A retaining well is built by adding an elevated structure about the mated IC chip with an inexpensive epoxy compound, forming a recess in which the IC is disposed. Thereafter, a coating layer of a viscous epoxy is added to the well and allowed to cure. The coating is clear, allowing light to pass to the IC chip. The epoxy along with the substrate encapsulates the IC chip, providing an easy and inexpensive chip package. The substrate may comprise a laminate substrate that is preprinted with easily reconfigurable leads and multi-layer routing arranged to minimize noise and cross-talk. The coating, or an additional coating placed on top of or underneath the clear coating, may also perform filtering of one or more portions of the light spectrum.

Abstract: A barrier area is located adjacent a horizontal transfer area and spaced from a field insulating area. The barrier area includes an insulating layer and a conductor extending from the horizontal transfer layer over the surface of a semiconductor substrate, a barrier layer of a second conductivity type formed under the surface of the semiconductor substrate and adjacent a first impurity layer of a first conductivity type of the horizontal transfer area, and a second impurity layer extending from the horizontal transfer area and formed under the barrier layer. A discharge area is located between the barrier area and the field insulating area.

Abstract: A charge transfer device has a charge transfer region under charge transfer electrodes for stepwise conveying charge packets through potential wells to a floating diffusion region, and the charge transfer region has a boundary sub-region contracting toward the floating diffusion region, wherein the final potential well is created at a certain portion in said boundary sub-region close to the floating diffusion region so that each charge packet travels over a short distance, thereby enhancing a charge transfer efficiency.

Abstract: Solid state image sensor having photodiode regions for converting optical image signal into an electrical signal and charge coupled device regions for transferring video charges generated in the photodiode regions in one direction, including first microlens layers spaced from one another and formed over the photodiode regions to be opposite thereto for focusing lights onto the photodiode regions, and second microlens layers formed of a material having a refractive index greater than the first microlens layers on an entire surface of the first microlens layers for focusing lights incident to edge portions of the first microlens layers and spaces between the first microlens layers onto the photodiode regions.

Abstract: A method and apparatus of forming adjacent, non-overlapping CCD electrodes within an image sensing device such the electrodes are U-shaped. The device provided by the disclosed method employs a substrate with a gate dielectric layer formed on a surface of the substrate with a plurality of phases created within the CCD. A deposited silicon layer is placed on the surface of the CCD and a mask is used to cover areas other than the first set of electrodes. Etching takes places leaving the mask areas to the deposited silicon and a set of side walls to the remaining deposited silicon are then oxidized. A first set of electrodes by forming an electrode layer placed over the CCD. CMP is employed to remove remaining deposited silicon layer as well as portions of the electrode layer such that the side walls remain vertical portions to electrode layer remaining in the side walls. The process is then repeated by placing another electrode material layer and another CMP process leaving two sets of adjacent U-shaped gates.

Abstract: An optical device packaging technique involves an optical sensor that is formed on a first substrate and flip chip bonded to a second substrate. The second substrate includes a through hole or a transparent section that is aligned with the optical sensor in order to allow light to contact the optical sensor. An embodiment of an optical device structure includes an optical sensor, a first substrate, a second substrate, and a circuit board. The optical sensor is formed on or within the first substrate and the individual sensors or pixels of the optical sensor are electrically connected to contact pads that are exposed on the first substrate. The first substrate is flip chip bonded to the second substrate. The second substrate is flip chip bonded to a circuit board. Another embodiment of an optical device structure includes an optical sensor, a first substrate, and a circuit board as the second substrate.

Abstract: A charge coupled device includes first and second pluralities of column registers and first and second register segments. The first plurality of column registers are splayed with respect to and on one side of a column direction line, and the second plurality of column registers are splayed with respect to and on another side of the column direction line. The first register segment is coupled to the first plurality of column registers, and the second register segment is coupled to the second plurality of column registers. The second register segment is spaced apart from the first register segment so as to define a layout area between the first and second register segments where at least one of an isolation register element and an output node is disposed. Each column register of the first plurality of column registers includes a plurality of column element wells.

Abstract: A multi-layered gate for use in a CMOS or CCD imager formed with a second gate at least partially overlapping it. The multi-layered gate is a complete gate stack having an insulating layer, a conductive layer, an optional silicide layer, and a second insulating layer, and has a second gate formed adjacent to it which has a second conductive layer that extends at least partially over the surface of the multi-layered gate. The multi-layered gate has improved insulation, thereby resulting in fewer shorts between the conductive layers of the two gates. Also disclosed are processes for forming the multi-layered gate and the overlapping gate.

Abstract: Generally, and in one form of the invention, a monolithic solid state image-sensing device is disclosed. The device utilizes only a single layer of polysilicon deposition in its fabrication process that is split into two or more phases by very narrow gaps. The single polysilicon layer makes the fabrication process simpler and more compatible with modern semiconductor manufacturing technology. The device also incorporates a lateral anti-blooming drain structure that is formed by a self-aligned diffusion process and does not need a polysilicon gate for its proper function.

Abstract: The invention provides a CMOS image sensor that can decrease the influence of the noise charge on the OB cells that determine the darkness level and can prevent the deterioration of the image quality. A region that absorbs the noise charge in a substrate is formed at the periphery of the cell array portion. As in the photodiode, a PN junction is formed in the noise charge absorption region, and one end thereof is connected to a power source voltage. This noise charge absorption region is formed between the cell array portion and the peripheral circuit portion.

Abstract: A color CMOS image sensor including a matrix of pixels (e.g., CMOS APS cells) that are fabricated on a semiconductor substrate. A silicon-nitride layer is deposited on the upper surface of the pixels, and is etched using a reactive ion etching (RIE) process to form microlenses. A protective layer including a lower color transparent layer formed from a polymeric material, a color filter layer and an upper color transparent layer are then formed over the microlenses. Standard packaging techniques are then used to secure the upper color transparent layer to a glass substrate.

Abstract: A charge transfer structure includes an insulating film on a first semiconductor region, a plurality of transfer electrodes and a signal generating circuit. The plurality of transfer electrodes are formed on the insulating film, and each of the plurality of transfer electrodes is composed of a barrier electrode and an accumulation electrode. The signal generating circuit generates first to 2N-th (N is a positive integer more than 1) pulse signals which are supplied to every 2N transfer electrodes of the plurality of transfer electrodes in an interline mode. As a result, a signal charge can be transferred for the 2N transfer electrodes at maximum during one cycle of the first to 2N-th pulse signals.

Abstract: A charge transfer device is provided which is capable of reducing a reset field-through noise in a stable manner without being affected by characteristics of transistors and without occurrence of a mustache-shaped pulse-like noise.

Abstract: An image sensor capable of preventing the degradation of pinned photodiodes and the generation of leakage current between neighboring pinned photodiodes is provided. The disclosed image sensor contains a plurality of pixel units, each pixel unit having a photodiode region. The image sensor includes a semiconductor substrate of a first conductivity type; a device isolation layer formed in the semiconductor substrate; a field stop layer formed beneath the device isolation layer; a trench formed in the semiconductor substrate, wherein the trench surrounds the photodiode region; a first doping region of the first conductivity type formed beneath the surface of the semiconductor substrate and beneath the surfaces of the trench; an insulating member filling the trench; and a second doping region of a second conductivity type formed in the semiconductor substrate under the first doping region.

Abstract: To transfer signal charges at high speed with small noise, there is provided a charge transfer apparatus including a semiconductor substrate of one conductivity type, a charge transfer region of a conductivity type opposite to that of the semiconductor substrate that is formed in the semiconductor substrate and joined to the semiconductor substrate to form a diode, a signal charge input portion which inputs a signal charge to the charge transfer region, a signal charge output portion which accumulates the signal charge transferred from the charge transfer region, and a plurality of independent potential supply terminals which supply a potential gradient to the semiconductor substrate, wherein the signal charge in the charge transfer region is transferred by the potential gradient formed by the plurality of potential supply terminals.

Abstract: A charge storing layer of a photodiode having an N-type conductivity includes an N+-type additional implant area in the vicinity of a junction between the charge storing layer and an isolation region. The additional implant area provides an increase of stored charge and suppression of increase of the pulse voltage for a substrate shutter, and can be made to have a smaller width within a current design rule.

Abstract: A CMOS image sensor structure that includes a substrate, a sensing layer and a dopant layer. The substrate is formed using a first conductive type material. The sensing region is buried within the substrate. The sensing layer is a second type conductive material layer. The dopant layer is formed above the sensing layer. The dopant layer is a first type conductive material layer.

Abstract: A test structure for insulation-film evaluation has a CCD structure comprising a semiconductor substrate (1), a gate insulating film (2) to be evaluated which is formed across the main surface of the semiconductor substrate (1), a plurality of gate electrodes (3a-3i) equally spaced in this order on the gate insulating film (2), a wire (20) connected to the gate electrodes (3a, 3d, 3g), a wire (21) connected to the gate electrodes (3b, 3e, 3h), and a wire (22) connected to the gate electrodes (3c, 3f, 3i). The test structure further comprises a read circuit (5) including an inverter (4) and other elements connected to the output stage of the CCD structure. This test structure allows simple failure location.

Abstract: In general, the output of a buried channel CCD is provided with a floating diffusion (4), which forms a storage site to determine the size of an electric charge. For this purpose, the floating diffusion may be connected to the input of an amplifier, such as a source follower (8). The charge is transferred to the floating zone from below an output gate OG to which a DC voltage is applied. To obtain a high sensitivity, i.e. a high voltage per electron, it is important to keep the capacitance of the floating zone as small as possible. The capacitance can be reduced by narrowing the channel at the output. This method of reducing C, however, is limited in known structures because this shape of the channel may induce an electric field in the channel which counteracts the transfer to the floating zone. To suppress this effect, the gate oxide (5) below the output gate is provided with a thicker part (5b) adjoining the floating diffusion (4).

Abstract: There is disclosed a charge transfer apparatus in which with respect to a signal charge detector, a gate insulation film under an output electrode and a reset electrode is formed of one layer of a silicon oxide film. As a result, even when the device is charged up during a manufacture process, the charge injection to the gate insulation film under the output electrode and reset electrode can be prevented. Therefore, the threshold value dispersion of the output electrode or the reset electrode is suppressed, and the charge transfer apparatus with uniform characteristics can be provided. Furthermore, by forming the silicon oxide film under the output electrode and reset electrode to be thick, the capacity formed of a floating diffusion layer and the parasitic capacity of the output electrode, and the capacity formed of the floating diffusion layer and the parasitic capacity of the reset electrode are reduced.

Abstract: A retrograde well structure for a CMOS imager that improves the quantum efficiency and signal-to-noise ratio of the imager. The retrograde well comprises a doped region with a vertically graded dopant concentration that is lowest at the substrate surface, and highest at the bottom of the well. A single retrograde well may have a single pixel sensor cell, multiple pixel sensor cells, or even an entire array of pixel sensor cells formed therein. The highly concentrated region at the bottom of the retrograde well repels signal carriers from the photosensor so that they are not lost to the substrate, and prevents noise carriers from the substrate from diffusing up into the photosensor. Also disclosed are methods for forming the retrograde well.

Abstract: A semiconductor device, such as a back side illuminated CCD, is fabricated by forming an insulating layer over the front side of a body of semiconductor material, depositing a layer of high resistivity material over the front side of the insulating layer, patterning a portion of the layer of high resistivity material to form a long and narrow trace, and attaching a support member to the front side of the insulating layer. In the case of a back side illuminated CCD, the patterning of the layer of high resistivity material advantageously forms a long and narrow trace substantially confined to a peripheral area of the front side of the insulating layer and the semiconductor material is removed from the corresponding peripheral area of the back side of the insulating layer, leaving a plateau of semiconductor material that does not extend over the area that contains the long and narrow trace.

Abstract: The present invention relates to the formation, on a substrate having a display area and a peripheral area, of a gate wire including a plurality of gate lines and gate electrodes in a display area and gate pads in the peripheral area, and of a common wire, including a common signal line and a plurality of common electrodes in the display area. A gate insulating layer, a semiconductor layer, an ohmic contact layer and a conductor layer are sequentially deposited, and the conductor layer and the ohmic contact layer are patterned to form a data wire including a plurality of data lines, a source electrode and a drain electrode of the display area, and data pads of the peripheral area, and an ohmic contact layer pattern thereunder. A passivation layer is deposited and a positive photoresist layer is coated thereon. The photoresist layer is exposed to light through one or more masks having different transmittances between the display area and the peripheral area.

Abstract: A barrier area is located adjacent a horizontal transfer area and spaced from a field insulating area. The barrier area includes an insulating layer and a conductor extending from the horizontal transfer layer over the surface of a semiconductor substrate, a barrier layer of a second conductivity type formed under the surface of the semiconductor substrate and adjacent a first impurity layer of a first conductivity type of the horizontal transfer area, and a second impurity layer extending from the horizontal transfer area and formed under the barrier layer. A discharge area is located between the barrier area and the field insulating area.

Abstract: A semiconductor energy detector as disclosed herein is arranged so that an aluminum wiring pattern is formed on the front side of transfer electrodes of a CCD vertical shift register, which pattern includes meander-shaped auxiliary wirings for performing auxiliary application/supplement and additional wirings for performing auxiliary supplement of transfer voltages in a way independent of the auxiliary wirings with respective ones of such wirings being connected to corresponding transfer electrodes to thereby avoid a problem as to lead resistivities at those transfer electrodes made of polycrystalline silicon, thus achieving the intended charge transfer at high speeds with high efficiency.

Abstract: A charge coupled device has an n- type charge accumulating layer equal to or less than 5 micron in width, and the unit cells suffer from reduction of signal charge accumulated therein and an increased pulse height of a pulse signal for a substrate shutter, wherein at least one p- type local impurity region is formed in such a manner as to form a p-n junction together with the n- type charge accumulating layer and the n- type semiconductor substrate, thereby increasing the amount of signal charge accumulated in each unit cell without sacrifice of the pulse height of the pulse signal for the substrate shutter.

Abstract: A charge coupled device including: a substrate; a semiconductor layer overlying the substrate; a semiconductor layer overlying the semiconductor layer; a charge storage layer existing on the semiconductor layer and sandwiched by a pair of isolation regions; an impurity region between the semiconductor layer and the charge storage layer; a dielectric film overlying the charge storage layer and the isolation regions, and an electrode formed by a conductive film. In accordance with the present invention, the increase of the amount of the charge storage and of the higher photosensitivity can be simultaneously satisfied. The fluctuation of the characteristics of the charge coupled device in accordance with the present invention is smaller than that of the conventional charge coupled device. Further, the method of the fabrication is less complicated than that for the conventional charge coupled device.

Abstract: The invention provides a signal processing apparatus comprising clamp capacitance means for receiving, at one electrode thereof, first and second signals outputted from a signal source, a signal transfer transistor of which one main electrode is connected to an other electrode of the clamp capacitance means, signal accumulating capacitance means connected to an other main electrode of the signal transfer transistor, and reset means for fixing the potential of the signal accumulating capacitance means, wherein the potential of the signal accumulating capacitance means is fixed by the reset means while the first signal is outputted from the signal source and the signal accumulating capacitance means is maintained in a floating state while the second signal is outputted from the signal source, and the signal transfer transistor is controlled in such a manner that the potential of the main electrode of the signal transfer transistor and that of the other main electrode thereof show different saturation operations

Abstract: A multi-layered gate for use in a CMOS or CCD imager formed with a second gate at least partially overlapping it. The multi-layered gate is a complete gate stack having an insulating layer, a conductive layer, an optional silicide layer, and a second insulating layer, and has a second gate formed adjacent to it which has a second conductive layer that extends at least partially over the surface of the multi-layered gate. The multi-layered gate has improved insulation, thereby resulting in fewer shorts between the conductive layers of the two gates. Also disclosed are processes for forming the multi-layered gate and the overlapping gate.

Abstract: An active pixel is described comprising a semiconductor substrate and a radiation sensitive source of carriers in the substrate, such as for instance, a photodiode. A non-carrier storing, carrier collecting region in the substrate is provided for attracting carriers from the source as they are generated. At least one doped or inverted region of a first conductivity is provided in or on the substrate for storing the carriers before read-out. At least one non-carrier storing, planar current flow, carrier transport pathway is provided from or through the carrier collecting region to the at least one doped or inverted region to transfer the carriers without intermediate storage to the read-out electronics.

Abstract: A solid state image sensor device and a method of fabricating the same are disclosed in the present invention. A solid state image sensor device includes a semiconductor substrate, a well region in the semiconductor substrate, a horizontal charge transmission region in the well region, a plurality of insulating layers in the horizontal charge transmission region, a gate insulating layer on the entire surface including the insulating layers, a plurality of first polygates on the gate insulating layer, the first polygates being separated from each other and overlapping a portion of each insulating layer, a plurality of impurity regions in the horizontal charge transmission region at both sides of each first polygate, an interlayer insulating layer on the entire surface including the first polygates, and a plurality of second polygates on the interlayer insulating layer and overlapped with a portion of each first polygate.

Abstract: Minority carriers generated by photoelectric conversion in an isolation layer and a semiconductor region with the same conduction type as that of the isolation layer are provided with an effective diffusion length owing to a trench formed in the isolation layer and with no path, which could be a straight escape route for the minority carriers, and false signals, therefore, scarcely enters to a neighboring cell, so that smear and color interference can be suppressed.

Abstract: A solid state image sensor is provided with a primary first-conductivity-type semiconductive region which serves as a charge storage region of a photo-sensing area and a secondary first-conductivity-type semiconductive region for enlarging a charge collecting region of the photo-sensing area.