Abstract: A FinFET device structure and method for forming the same are provided. The FinFET device structure includes a first fin structure extending above a substrate, and the first fin structure includes a portion made of silicon germanium (SiGe). The FinFET device structure includes a second fin structure adjacent to the first fin structure. The FinFET device structure also includes a first liner layer formed on the outer sidewall surface of the first fin structure and a second liner layer formed on the inner sidewall surface of the first fin structure. The FinFET device structure further includes a first isolation structure formed on the substrate, and the first liner layer is between the first isolation structure and the first fin structure, and a top surface of the second liner layer is higher than a top surface of the first liner layer.

Abstract: A method includes forming an insulating structure over a substrate, wherein the substrate has a semiconductor fin separated from the insulating structure; depositing a high-? dielectric layer over the semiconductor fin and a sidewall of the insulating structure facing the semiconductor fin; etching a first portion of the high-? dielectric layer over the sidewall of the insulating structure, wherein a second portion of the high-? dielectric layer remains over the semiconductor fin; and depositing a gate electrode over the second portion of the high-? dielectric layer.

Abstract: A semiconductor device has a substrate, a first dielectric fin, and an isolation structure. The substrate has a first semiconductor fin. The first dielectric fin is disposed over the substrate and in contact with a first sidewall of the first semiconductor fin, in which a width of the first semiconductor fin is substantially equal to a width of the first dielectric fin. The isolation structure is in contact with the first semiconductor fin and the first dielectric fin, in which a top surface of the isolation structure is in a position lower than a top surface of the first semiconductor fin and a top surface of the first dielectric fin.

Abstract: The present disclosure provides an array substrate and a method of manufacturing the same and a display apparatus in which the array substrate is applied. In one embodiment, the method of manufacturing an array substrate at least includes the steps of: forming a first electrode layer, a metal gate layer and a first layer of non-oxide insulation material, the first layer of non-oxide insulation material being formed on an upper surface of the metal gate layer; forming, by using one patterning process, a pattern including a first electrode and a gate such that, after completion of the patterning process, a first non-oxide insulation layer is further formed on the gate and a first sub-electrode belonging to the first electrode layer is further formed below the gate. This method of manufacturing the array substrate is simple, which facilitates mass production of the array substrate as well as the display apparatus.

Abstract: Source and drain formation techniques are disclosed herein for fin-like field effect transistors (FinFETs). An exemplary method for forming epitaxial source/drain features for a FinFET includes epitaxially growing a semiconductor material on a plurality of fins using a silicon-containing precursor and a chlorine-containing precursor. The semiconductor material merges to form an epitaxial feature spanning the plurality of fins, where the plurality of fins has a fin spacing that is less than about 25 nm. A ratio of a flow rate of the silicon-containing precursor to a flow rate of the chlorine-containing precursor is less than about 5. The method further includes etching back the semiconductor material using the chlorine-containing precursor, thereby modifying a profile of the epitaxial feature. The epitaxially growing and the etching back may be performed only once. In some implementations, where the FinFET is an n-type FinFET, the epitaxially growing also uses a phosphorous-containing precursor.

Abstract: A finFET LDMOS semiconductor device includes a first well disposed adjacent to a second well on a substrate and a third well disposed on the substrate, wherein the second well is disposed between the first well and the third well. Additionally, the finFET LDMOS semiconductor device includes a source disposed on the first well, a fin at least partially disposed on the first well and adjacent to the source, a drain disposed on the third well, a shallow trench isolation (STI) disposed at least partially in the third well, and a STI protection structure disposed on the substrate between the second well and the third well and along a side of the STI that is closest to the source, wherein the STI protection structure is configured to discourage a drain to source current from flowing along the side of the STI that is closest to the source.

Abstract: A method for manufacturing a semiconductor device is described that comprises providing a substrate, forming a plurality of fins having a first semiconductor material, replacing a first portion of at least one of the fins with a second semiconductor material, and distributing the second semiconductor material from the first portion to a second portion of the at least one of the fins.

Abstract: A semiconductor device includes a metal gate on a substrate, in which the metal gate includes a first work function metal (WFM) layer and the first WFM layer further includes a first vertical portion, a second vertical portion, wherein the first vertical portion and the second vertical portion comprise different heights, and a first horizontal portion connecting the first vertical portion and the second vertical portion.

Abstract: Three-dimensional integrated circuit (3DIC) structures are disclosed. A 3DIC structure includes a first die and a second die bonded to the first die. The first die includes a first integrated circuit region and a first seal ring region around the first integrated circuit region, and has a first alignment mark within the first integrated circuit region. The second die includes a second integrated circuit region and a second seal ring region around the second integrated circuit region, and has a second alignment mark within the second seal ring region and corresponding to the first alignment mark.

Abstract: The present disclosure provides PMOS transistors and fabrication methods thereof. An exemplary fabrication process of a PMOS transistor includes providing a semiconductor substrate having a surface; forming a gate structure on the surface of the semiconductor substrate; forming SiGe regions in the surface of the semiconductor substrate at two sides of the gate structure by implanting Ge ions into the semiconductor substrate; forming sidewalls on side surfaces of the gate structure and portions of surfaces of the SiGe regions close to the gate structure; removing portions of the SiGe regions at two sides of the gate structure to expose portions of the semiconductor substrate; forming trenches in the semiconductor substrate by etching the exposed portions of the semiconductor substrate at the two sides of the sidewalls; and forming source/drain regions by filling the trenches with a compressive stress material.

Abstract: In an example, a wet cleaning process is performed to clean a structure having features and openings between the features while preventing drying of the structure. After performing the wet cleaning process, a polymer solution is deposited in the openings while continuing to prevent any drying of the structure. A sacrificial polymer material is formed in the openings from the polymer solution. The structure may be used in semiconductor devices, such as integrated circuits, memory devices, MEMS, among others.

Abstract: A technique relates to a semiconductor device. A first vertical fin is formed with a first gate stack and a second vertical fin with a second gate stack. The second vertical fin has a hardmask on top. The first vertical fin is adjacent to a first bottom source or drain (S/D) region and the second vertical fin is adjacent to a second bottom S/D region. The first gate stack is reduced to a first gate length and the second gate stack to a second gate length, the second gate length being greater than the first gate length because of the hardmask. The hardmask is removed. A first top S/D region is adjacent to the first vertical fin and a second top S/D region is adjacent to the second vertical fin.

Abstract: A method for fabricating an electronic device is provided to include: forming a hard mask pattern over a substrate to expose a gate formation region; forming a gate trench by etching the substrate using the hard mask pattern; forming a gate insulating layer over an inner wall of the gate trench; forming a gate electrode filling a lower portion of the gate trench in which the gate insulating layer is formed; forming an insulating material covering a resultant structure in which the gate electrode is formed; forming a gate protective layer having a top surface lower than a bottom surface of the hard mask pattern; removing the hard mask pattern; recessing the substrate so that a top surface of the substrate is lower than the top surface of the gate protective layer; and forming a conductive pattern filling a space formed by the recessing of the substrate.

Abstract: The semiconductor structure includes a plurality of FETs disposed on a semiconductor substrate, the FETs including gates with elongated shape oriented in a first direction; a first metal layer of first metal lines disposed over the gates and oriented in a second direction perpendicular to the first direction; a second metal layer of second metal lines disposed over the first metal layer and oriented in the first direction; and a third metal layer of third metal lines oriented in the second direction and disposed over the second metal layer. The first metal lines have a first pitch P1; the second metal lines have a second pitch P2; the third metal lines have a third pitch P3; and the gates have a fourth pitch P4, wherein a ratio of the second pitch over the fourth pitch P2:P4 is about 3:2.

Abstract: A method of fabricating an integrated circuit includes depositing a first dielectric material onto a semiconductor surface of a substrate having a gate stack thereon including a gate electrode on a gate dielectric. The first dielectric material is etched to form sidewall spacers on sidewalls of the gate stack. A top surface of the first dielectric material is chemically converted to a second dielectric material by adding at least one element to provide surface converted sidewall spacers. The second dielectric material is chemically bonded across a transition region to the first dielectric material.

Abstract: A semiconductor device including a first insulating interlayer on a substrate; a second insulating interlayer on the first insulating interlayer; a gate structure extending through the first insulating interlayer and the second insulating interlayer on the substrate, a lower portion of the gate structure having a first width, and an upper portion of the gate structure having a second width that is greater than the first width and that gradually increases from a bottom toward a top thereof; and a spacer structure on a sidewall of the gate structure, a width of an upper portion of the spacer structure being less than a width of a lower portion of the spacer structure.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to scaled memory structures with middle of the line cuts and methods of manufacture The structure comprises: a plurality of fin structures formed on a substrate; a plurality of gate structures spanning over adjacent fin structures; a cut in adjacent epitaxial source/drain regions; and a cut in contact material formed adjacent to the plurality of gate structures, which provides separate contacts.

Abstract: A method for manufacturing an interconnect structure is provided, and the method is as below. A dielectric layer is deposited over a substrate. The dielectric layer is etched to form a recess. A dummy adhesion layer is deposited on sidewalls of the recess. A conductive layer is formed in the recess. The dummy adhesion layer is removed to expose a portion of the conductive layer.

Abstract: A circuit includes a first current source that provides a current and a resistive branch in series with the first current source that provides a first voltage value and a second voltage value. A capacitive device is coupled with a voltage node having a voltage value, and a switching network alternates between charging the capacitive device to have the voltage value increase to the first voltage value, and discharging the capacitive device to have the voltage value decrease to the second voltage value.

Abstract: A method of manufacturing a semiconductor device includes forming a plurality of fins by forming a plurality of first device isolating trenches repeated at a first pitch in a substrate, forming a plurality of fin-type active areas protruding from a top surface of a first device isolating layer by forming the first device isolating layer in the plurality of first device isolating trenches, forming a plurality of second device isolating trenches at a pitch different from the first pitch by etching a portion of the substrate and the first device isolating layer, and forming a second device isolating layer in the plurality of second device isolating trenches, so as to form a plurality of fin-type active area groups separated from each other with the second device isolating layer therebetween.

Abstract: Semiconductor structures are provided. A semiconductor structure includes a bottom substrate having a first region and a second region; an insulation layer formed on the bottom substrate in the first region; a top substrate on side surface of the trench and the insulation layer; a first fin portion formed over the insulation layer, and a gate structure crossing the first fin portion. The first fin portion is electrically isolated from the bottom substrate through the insulation layer to reduce the leakage current at the bottom of the first fin portion. The gate structure covers part of side and top surfaces of the first fin portion.

Abstract: A structure and method for implementation of dummy gate structures within multi-gate device structures includes a semiconductor device including an isolation region that separates a first and second active region. The first active region is adjacent to a first side of the isolation region and the second active region is adjacent to a second side of the isolation region. A device including a source, a drain, and a gate is formed within the first active region. One of the source and drain regions are disposed adjacent to the isolation region. A dummy gate is formed at least partially over the isolation region and adjacent to the one of the source and drain regions. In various examples, the gate includes a first dielectric layer having a first thickness and the dummy gate includes a second dielectric layer having a second thickness greater than the first thickness.

Abstract: A semiconductor device with a FINFET, which provides enhanced reliability. The semiconductor device includes a first N channel FET and a second N channel FET which are coupled in series between a wiring for output of a 2-input NAND circuit and a wiring for a second power potential. In plan view, a local wiring is disposed between a first N gate electrode of the first N channel FET and a second N gate electrode of the second N channel FET which extend in a second direction, and crosses a semiconductor layer extending in a first direction and extends in the second direction. The local wiring is coupled to a wiring for heat dissipation.

Abstract: Methods of self-aligned multiple patterning. A mandrel line is formed over a hardmask layer, and forming a block mask is formed over a first portion of the mandrel line that is linearly arranged between respective second portions of the mandrel line. After forming the first block mask, the second portions of the mandrel line are removed with an etching process to cut the mandrel line and expose respective portions of the hardmask layer. A second portion of the mandrel line is covered by the block mask during the etching process to define a mandrel cut in the mandrel line.

Abstract: A production of contact zones for a transistor device including the steps of: a) forming at least one layer made of a compound based on semiconductor and metal on one or more first semiconductor region(s) of a first N-type transistor and on one or more second semiconductor region(s) of a second P-type transistor resting on a same substrate, the first regions being based on a III-V type material whereas the second semiconductor regions are based on another material different from the III-V material, the semiconductor of the compound being an N-type dopant of the III-V material, b) carrying out at least one thermal annealing so as to form on the first semiconductor regions first contact zones and on the second semiconductor regions second contact zones based on a semiconductor and metal compound while increasing the N-doping of the III-V material.

Abstract: A first p type semiconductor region is provided between an n type drift region surrounding a drain region and an n type buried region, and a second p type semiconductor region is provided between the first p type semiconductor region and a p type well region surrounding a source region so as to overlap the first p type semiconductor region and the p type well region. Negative input breakdown voltage can be ensured by providing the first p type semiconductor region over the n type buried region. Further, potential difference between the source region and the first p type semiconductor region can be increased and the hole extraction can be performed quickly. Also, a path of hole current flowing via the second p type semiconductor region can be ensured by providing the second p type semiconductor region. Thus, the on-breakdown voltage can be improved.

Abstract: This technology provides an electronic device and a method for fabricating the same. An electronic device in accordance with an implementation of this document may include a semiconductor memory, wherein the semiconductor memory may include: one or more variable resistance elements each exhibiting different resistance states for storing data, wherein each variable resistance element may include: a Magnetic Tunnel Junction (MTJ) structure including a free layer having a changeable magnetization direction, a pinned layer having a fixed magnetization direction and a tunnel barrier layer interposed between the free layer and the pinned layer; a seed layer disposed under the MTJ structure to facilitate a growth of the pinned layer or the free layer; and an amorphous metallic carbon layer disposed under the seed layer.

Abstract: When a memory cell (MC) is downsized by reducing the distance between a drain region (12a) and a source region (12b) on the surface of a fin (S2) with a high impurity concentration inside the fin (S2), the shape of the fin (S2) can be set such that a potential difference between a memory gate electrode (MG) and the fin (S2) is reduced to suppress the occurrence of disturbance. Accordingly, the memory cell (MC) achieves downsizing and suppression of the occurrence of disturbance.

Abstract: A semiconductor device includes at least one semiconductor fin on an upper surface of a substrate. The at least one semiconductor fin includes a channel region interposed between opposing source/drain regions. A gate stack is on the upper surface of the substrate and wraps around sidewalls and an upper surface of only the channel region. The channel region is a dual channel region including a buried channel portion and a surface channel portion that completely surrounds the buried channel.

Abstract: A method of manufacturing a semiconductor structure includes the following steps. A first raised portion is formed on a semiconductor substrate. The height of the first raised portion is reduced, and a dielectric material is formed over the first raised portion. The dielectric material is annealed such that the first raised portion is tilted.

Abstract: A fin-like field-effect transistor (FinFET) device is disclosed. The device includes a semiconductor substrate having a source/drain region, a plurality of isolation regions over the semiconductor substrate and a source/drain feature in the source/drain region. The source/drain feature includes a multiple plug-type portions over the substrate and each of plug-type portion is isolated each other by a respective isolation region. The source/drain feature also includes a single upper portion over the isolation regions. Here the single upper portion is merged from the multiple plug-type portions. The single upper portion has a flat top surface facing away from a top surface of the isolation region.

Abstract: A packaged unidirectional power transistor comprises a package with a number of pins which provide a voltage and/or current connection between the outside and the inside. Inside the package, a bidirectional vertical power transistor is present with a controllable bidirectional current path, through a body of the bidirectional vertical power transistor, between a first current terminal of the bidirectional vertical power transistor connected to the first current pin and a second current terminal of the bidirectional vertical power transistor connected to the second current pin. A control circuit connects the control pin to the body terminal and the control terminal to drive the body and the control terminal, which allows current through the body in a forward direction, from the first current terminal to the second terminal, as a function of the control voltage, and to block current in a reverse direction regardless of the voltage.

Abstract: A semiconductor device includes a plurality of spaced apart fins, a dielectric material layer positioned between each of the plurality of spaced apart fins, and a common gate structure positioned above the dielectric material layer and extending across the fins. A continuous merged semiconductor material region is positioned on each of the fins and above the dielectric material layer, is laterally spaced apart from the common gate structure, extends between and physically contacts the fins, has a first sidewall surface that faces toward the common gate structure, and has a second sidewall surface that is opposite of the first sidewall surface and faces away from the common gate structure. A stress-inducing material is positioned in a space defined by at least the first sidewall surface, opposing sidewall surfaces of an adjacent pair of fins, and an upper surface of the dielectric material layer.

Abstract: In some embodiments, a field effect transistor (FET) structure comprises a body structure, dielectric structures, a gate structure and a source or drain region. The gate structure is formed over the body structure. The source or drain region is embedded in the body structure beside the gate structure, and abuts and is extended beyond the dielectric structure. The source or drain region contains stressor material with a lattice constant different from that of the body structure. The source or drain region comprises a first region formed above a first level at a top of the dielectric structures and a second region that comprises downward tapered side walls formed under the first level and abutting the corresponding dielectric structures.

Abstract: A semiconductor device includes a base substrate including an NMOS region and a PMOS region. The PMOS region includes a first P-type region and a second P-type region. The semiconductor device also includes an interlayer dielectric layer, a gate structure formed through the interlayer dielectric layer and including an N-type region gate structure formed in the NMOS region, a first gate structure formed in the first P-type region and connected to the N-type region gate structure, and a second gate structure formed in the second P-type region and connected to the first gate structure. The direction from the N-type region gate structure to the second gate structure is an extending direction of the gate structure, and along a direction perpendicular to the extending direction of the gate structure, the width of the first gate structure is larger than the width of the second gate structure.

Abstract: Vertical field effect transistors (FETs) with minimum pitch and methods of manufacture are disclosed. The structure includes at least one vertical fin structure and gate material contacting with the at least one vertical fin structure. The structure further includes metal material in electrical contact with the ends of the at least one vertical fin.

Abstract: Various methods and structures for fabricating a strained semiconductor fin of a FinFET device. A strained semiconductor fin structure includes a substrate, a semiconductor fin disposed on the substrate, the semiconductor fin having two fin ends, and a stressor material cladding wrapped around a portion of each of the two fin ends forming a strained semiconductor fin that includes at least one strained channel fin having stressor cladding wrapped around at least one end of the strained channel fin thereby straining the at least one strained channel fin. The stressor cladding can be a compressive nitride stressor to compressively strain a compressively strained silicon germanium fin. The stressor cladding can be a tensile nitride stressor to tensily strain a tensily strained silicon fin.

Abstract: A semiconductor device includes a first active pattern extending in a first direction on a first region and a second region of a substrate, a first dummy gate electrode extending in a second direction crossing the first active pattern between the first region and the second region, a contact structure contacting the first dummy gate electrode and extending in the first direction, and a power line disposed on the contact structure and electrically connected to the contact structure. The power line extends in the first direction. The contact structure overlaps with the power line when viewed in a plan view.

Abstract: The present invention provides a display substrate and a manufacturing method thereof, and a flexible display device having the display substrate, which belong to the field of display technology, and can solve the problem of poor reliability of display substrates due to the damage to thin film transistors when the existing display substrates are bent. In the display substrate provided by the present invention, by introducing stress absorption units made of resin material into the display substrate, the stress generated by the display substrate being bent is released by the resin material, and thin film transistors on the display substrate are thus less likely to be damaged, so that the reliability of the whole display substrate is improved.

Abstract: The present disclosure provides a display panel and a display device. The display panel includes a plurality of sub-pixels divided into sub-pixels of a first type, sub-pixels of a second type, sub-pixels of a third type and sub-pixels of a fourth type, each type of sub-pixels being configured to display a different color. An area of an aperture region of any of the fourth-sub-pixel type is smaller than an area of an aperture region of each sub-pixel of the first-sub-pixel type, the second-sub-pixel type and the third-sub-pixel type. Each pixel group also includes at least two display elements. Each of the display elements is associated with one of the sub-pixels in the pixel group, and the at least two display elements are disposed within the non-aperture region of the fourth sub-pixel type.

Abstract: A method is provided for fabricating a structure including a two-dimensional material. The method includes a step of providing an electrically-conducting substrate and a step of forming a solid organic spacer layer on the electrically-conducting substrate. The method further includes depositing the two-dimensional material on the spacer layer. A structure formed according to the method includes an electrically-conducting substrate and a layer of a two-dimensional material. A solid organic spacer layer is arranged between the electrically-conducting substrate and the layer of the two-dimensional material.

Abstract: A gate structure includes at least one spacer defining a gate region over a semiconductor substrate, a gate dielectric layer disposed on the gate region over the semiconductor substrate, a first work function metal layer disposed over the gate dielectric layer and lining a bottom surface of an inner sidewall of the spacer, and a filling metal partially wrapped by the first work function metal layer. The filling metal includes a first portion and a second portion, wherein the first portion is between the second portion and the semiconductor substrate, and the second portion is wider than the first portion.

Abstract: A method for fabricating a semiconductor device includes: forming a gate trench in a semiconductor substrate; forming a gate dielectric layer over a bottom surface and sidewalls of the gate trench; forming a first work function layer over the gate dielectric layer; doping a work function adjustment element to form a second work function layer which overlaps with the sidewalls of the gate trench; forming a gate conductive layer that partially fills the gate trench; and forming doped regions inside the semiconductor substrate on both sides of the gate trench.

Abstract: A memory device includes six field effect transistors (FETs) formed with semiconductor nanowires arranged on a substrate in an orientation substantially perpendicular to the substrate. The semiconductor nanowires have bottom contacts, gate contacts separated in a direction perpendicular to the substrate from the bottom contacts, and top contacts separated in a direction perpendicular to the substrate from the gate contacts. The necessary connections are made among the bottom, gate, and top contacts to form the memory device using first, second, and third metallization layers, the first metallization layer being separated in a direction perpendicular to the substrate from the top contacts, the second metallization layer being separated in a direction perpendicular to the substrate from the first metallization layer, and the third metallization layer being separated in a direction perpendicular to the substrate from the second metallization layer.

Abstract: A semiconductor device includes a gate structure formed over a channel region of the semiconductor device, a source/drain region adjacent the channel region, and an electrically conductive contact layer over the source/drain region. The source/drain region includes a first epitaxial layer having a first material composition and a second epitaxial layer formed over the first epitaxial layer. The second epitaxial layer has a second material composition different from the first composition. The electrically conductive contact layer is in contact with the first and second epitaxial layers. A bottom of the electrically conductive contact layer is located below an uppermost portion of the first epitaxial layer.

Abstract: A semiconductor device may include a first active fin, a plurality of second active fins, a first source/drain layer structure, and a second source/drain layer structure. The first active fin may be on a first region of a substrate. The second active fins may be on a second region of the substrate. The first and second gate structures may be on the first and second active fins, respectively. The first source/drain layer structure may be on a portion of the first active fin that is adjacent to the first gate structure. The second source/drain layer structure may commonly contact upper surfaces of the second active fins adjacent to the second gate structure. A top surface of the second source/drain layer structure may be further from the surface of the substrate than a top surface of the first source/drain layer structure is to the surface of the substrate.

Abstract: A semiconductor device has a semiconductor substrate. A silicon germanium layer is disposed on the semiconductor substrate. The silicon germanium layer has a first silicon-to-germanium ratio. A first gate structure is disposed on the silicon germanium layer, and the first gate structure includes an interfacial layer on the silicon germanium layer. The interface layer has a second silicon-to-germanium ratio substantially the same as the first silicon-to-germanium ratio of the silicon germanium layer. The first gate structure also includes a high-dielectric layer on the interfacial layer and a first gate electrode on the high-? dielectric layer.

Abstract: Semiconductor device structures are provided. The semiconductor device structure includes a first semiconductor wire over a semiconductor substrate. The first semiconductor wire has a first width and a first thickness. The semiconductor device structure also includes a first gate stack surrounding the first semiconductor wire. The semiconductor device structure further includes a second semiconductor wire over the semiconductor substrate. The first semiconductor wire and the second semiconductor wire include different materials. The second semiconductor wire has a second width and a second thickness. The first width is greater than the second width. The first thickness is less than the second thickness. In addition, the semiconductor device structure includes a second gate stack surrounding the second semiconductor wire.

Abstract: A thin film transistor (TFT) structure includes a metal oxide semiconductor layer, a gate, a source, a drain, a gate insulation layer, and a passivation layer. The metal oxide semiconductor layer has a crystalline surface which is constituted by a plurality of grains separated from one another. An indium content of the grains accounts for at least 50% of all metal elements of the crystalline surface of the metal oxide semiconductor layer. The gate is disposed on one side of the metal oxide semiconductor layer. The source and the drain are disposed on the other side of the metal oxide semiconductor layer. The gate insulation layer is disposed between the gate and the metal oxide semiconductor layer. The passivation layer is disposed on the gate insulation layer, and the crystalline surface of the metal oxide semiconductor layer is in direct contact with the gate insulation layer or the passivation layer.

Abstract: An output buffer circuit for avoiding voltage overshoot includes an input stage, an output bias circuit, an output stage, a clamp circuit, and a control unit. The input stage includes a positive input terminal, for receiving an input voltage, and a negative input terminal. The input stage generates a current signal according to the input voltage. The output bias circuit is coupled to the input stage, for generating a dynamic bias according to the current signal. The output stage is coupled to the input stage and the output bias circuit, including an output terminal, reversely coupled to the positive input terminal, and at least one output transistor, coupled to the output bias circuit and the output terminal, for providing a driving current to the output terminal according to the dynamic bias to generate an output voltage.