Inorganic Layer (epo) Patents (Class 257/E21.266)

  • Patent number: 8222705
    Abstract: Disclosed herein is a solid-state image pickup device including: a trench formed in an insulating film above a light-receiving portion; a first waveguide core portion provided on an inner wall side of the trench; a second waveguide core portion filled in the trench via the first waveguide core portion; and a rectangular lens formed of the same material as that of the second waveguide core portion and provided integrally with the second waveguide core portion.
    Type: Grant
    Filed: May 7, 2010
    Date of Patent: July 17, 2012
    Assignee: Sony Corporation
    Inventors: Akiko Ogino, Yukihiro Sayama, Takayuki Shoya, Masaya Shimoji
  • Patent number: 8222635
    Abstract: An electronic device includes at least a substrate, an area on the substrate which has to be protected against moisture and/or oxygen, at least one contact, and an encapsulation layer system including at least a first inorganic layer. The at least one contact extends from the sealed area to a part of the substrate not sealed by the encapsulation layer system. The contact includes a shunt, which is an interruption bridged by an electrically conductive bridge. The first inorganic layer of the encapsulation system is applied so that it is in direct physical contact with the electrically conductive bridge. The bridge has a structure and shape which can be sealingly covered by the encapsulation layer system and is made from a material through which no moisture and/or oxygen can penetrate.
    Type: Grant
    Filed: March 20, 2007
    Date of Patent: July 17, 2012
    Assignee: OTB Solar B.V.
    Inventors: Bas Jan Emile Van Rens, Ruediger Lange
  • Publication number: 20120178266
    Abstract: Compositions and methods for forming titanium-containing thin films are provided. The compositions comprise at least one precursor selected from the group consisting of (methylcyclopentadienyl)Ti(NMe2)3, (ethylcyclopentadienyl)Ti(NMe2)3, (isopropylcyclopentadienyl)Ti(NMe2)3, (methylcyclopentadienyl)Ti(NEt2)3, (methylcyclopentadienyl)Ti(NMeEt)3, (ethylcyclopentadienyl)Ti(NMeEt)3 and (methylcyclopentadienyl)Ti(OMe)3; and at least one liquification co-factor other than the at least one precursor; wherein the at least one liquification co-factor is present in amount sufficient to co-act with the at least one precursor, and in combination with the at least one precursor, forms a liquid composition.
    Type: Application
    Filed: July 19, 2010
    Publication date: July 12, 2012
    Applicant: SIGMA-AIDRICH CO. LLC
    Inventors: Peter Nicholas Heys, Rajesh Odedra, Andrew Kingsley
  • Publication number: 20120175751
    Abstract: Disclosed are group IV metal-containing precursors and their use in the deposition of group IV metal-containing films{nitride, oxide and metal) at high process temperature. The use of cyclopentadienyl and imido ligands linked to the metal center secures thermal stability, allowing a large deposition temperature window, and low impurity contamination. The group IV metal (titanium, zirconium, hafnium)-containing fvm depositions may be carried out by thermal and/or plasma-enhanced CVD, ALD, and pulse CVD.
    Type: Application
    Filed: July 14, 2010
    Publication date: July 12, 2012
    Inventors: Julien Gatineau, Changhee Ko
  • Publication number: 20120171874
    Abstract: The present invention is a process of plasma enhanced cyclic chemical vapor deposition of silicon nitride, silicon carbonitride, silicon oxynitride, silicon carboxynitride, and carbon doped silicon oxide from alkylaminosilanes having Si—H3, preferably of the formula (R1R2N)SiH3 wherein R1 and R2 are selected independently from C2 to C10 and a nitrogen or oxygen source, preferably ammonia or oxygen has been developed to provide films with improved properties such as etching rate, hydrogen concentrations, and stress as compared to films from thermal chemical vapor deposition.
    Type: Application
    Filed: February 27, 2012
    Publication date: July 5, 2012
    Applicant: Air Products and Chemicals, Inc.
    Inventors: Hareesh Thridandam, Manchao Xiao, Xinjian Lei, Thomas Richard Gaffney, Eugene Joseph Karwacki, JR.
  • Publication number: 20120161288
    Abstract: In one embodiment, a method for forming a non-conductive crystalline oxide layer on an AlSb crystal includes heat treating an AlSb crystal in a partial vacuum atmosphere at a temperature conducive for air adsorbed molecules to desorb, surface molecule groups to decompose, and elemental Sb to evaporate from a surface of the AlSb crystal and exposing the AlSb crystal to an atmosphere comprising oxygen to form a crystalline oxide layer on the surface of the AlSb crystal. In another embodiment, a method for forming a non-conductive crystalline oxide layer on an AlSb crystal includes heat treating an AlSb crystal in a non-oxidizing atmosphere at a temperature conducive for decomposition of an amorphous oxidized surface layer and evaporation of elemental Sb from the AlSb crystal surface and forming stable oxides of Al and Sb from residual surface oxygen to form a crystalline oxide layer on the surface of the AlSb crystal.
    Type: Application
    Filed: December 22, 2010
    Publication date: June 28, 2012
    Applicant: Lawrence Livermore National Security, LLC
    Inventors: John William Sherohman, Jick Hong Yee, Arthur William Coombs, III, Kuang Jen J. Wu
  • Publication number: 20120146196
    Abstract: A semiconductor device includes a dielectric layer in which zirconium, hafnium, and a IV group element are mixed. A method for fabricating a capacitor includes forming a bottom electrode, forming the dielectric layer and forming a top electrode over the dielectric layer.
    Type: Application
    Filed: September 13, 2011
    Publication date: June 14, 2012
    Inventors: Kee-Jeung LEE, Kwon Hong, Kyung-Woong Park, Ji-Hoon Ahn
  • Publication number: 20120108077
    Abstract: Disclosed is a substrate processing apparatus that includes: a substrate supporting member that supports a substrate; a processing chamber capable of housing the substrate supporting member; a rotating mechanism that rotates the substrate supporting member; a carrying mechanism that carries out the substrate supporting member from the processing chamber; a material gas supply system that supplies material gas into the processing chamber; a nitrogen-containing-gas supply system that supplies nitrogen containing gas into the processing chamber; and a controller that controls the material gas supply system, the nitrogen-containing-gas supply system, the carrying mechanism, and the rotating mechanism, after forming a nitride film on the substrate by using the material gas and the nitrogen containing gas, to carry out the substrate supporting member that supports the substrate while being rotated from the processing chamber.
    Type: Application
    Filed: September 14, 2011
    Publication date: May 3, 2012
    Applicant: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Yukinao KAGA, Tatsuyuki SAITO, Masanori SAKAI, Takashi YOKOGAWA
  • Patent number: 8163584
    Abstract: The beam bending of a MEMS device is minimized by reducing interfacial strength between a sacrificial layer and a MEMS structure.
    Type: Grant
    Filed: April 11, 2008
    Date of Patent: April 24, 2012
    Assignee: International Business Machines Corporation
    Inventors: Minhua Lu, Nils D. Hoivik, Christopher Jahnes, John M. Cotte, Hongqing Zhang
  • Publication number: 20120088373
    Abstract: A dielectric containing a titanium silicon oxide film and a method of fabricating such a dielectric provide a dielectric for use in a variety of electronic devices. Embodiments may include a dielectric containing a titanium silicon oxide film arranged as one or more monolayers. Embodiments may include structures for capacitors, transistors, memory devices, and electronic systems with dielectrics containing a titanium silicon oxide film, and methods for forming such structures.
    Type: Application
    Filed: December 12, 2011
    Publication date: April 12, 2012
    Inventors: Kie Y. Ahn, Leonard Forbes
  • Patent number: 8133768
    Abstract: The present invention provides a method of manufacturing an electronic apparatus, such as a lighting device having light emitting diodes (LEDs) or a power generating device having photovoltaic diodes. The exemplary method includes depositing a first conductive medium within a plurality of channels of a base to form a plurality of first conductors; depositing within the plurality of channels a plurality of semiconductor substrate particles suspended in a carrier medium; forming an ohmic contact between each semiconductor substrate particle and a first conductor; converting the semiconductor substrate particles into a plurality of semiconductor diodes; depositing a second conductive medium to form a plurality of second conductors coupled to the plurality of semiconductor diodes; and depositing or attaching a plurality of lenses suspended in a first polymer over the plurality of diodes. In various embodiments, the depositing, forming, coupling and converting steps are performed by or through a printing process.
    Type: Grant
    Filed: September 15, 2009
    Date of Patent: March 13, 2012
    Assignees: NthDegree Technologies Worldwide Inc, The United States of America as represented by the Unites States National Aeronautics and Space Administration
    Inventors: William Johnstone Ray, Mark D. Lowenthal, Neil O. Shotton, Richard A. Blanchard, Mark Allan Lewandowski, Kirk A. Fuller, Donald Odell Frazier
  • Publication number: 20120045904
    Abstract: Embodiments of the disclosure generally provide methods of forming a hydrogen free silicon containing layer in TFT devices. The hydrogen free silicon containing layer may be used as a passivation layer, a gate dielectric layer, an etch stop layer, or other suitable layers in TFT devices, photodiodes, semiconductor diode, light-emitting diode (LED), or organic light-emitting diode (OLED), or other suitable display applications. In one embodiment, a method for forming a hydrogen free silicon containing layer in a thin film transistor includes supplying a gas mixture comprising a hydrogen free silicon containing gas and a reacting gas into a plasma enhanced chemical vapor deposition chamber, wherein the hydrogen free silicon containing gas is selected from a group consisting of SiF4, SiCl4, Si2Cl6, and forming a hydrogen free silicon containing layer on the substrate in the presence of the gas mixture.
    Type: Application
    Filed: August 20, 2011
    Publication date: February 23, 2012
    Applicant: APPLIED MATERIALS, INC.
    Inventor: Soo Young Choi
  • Publication number: 20120040162
    Abstract: A method of forming a high-k dielectric material including forming at least two portions of titanium dioxide, the at least two portions of titanium dioxide comprising a first portion comprising amorphous titanium dioxide and a second portion comprising rutile titanium dioxide. A method of forming a high-k dielectric material including forming a first portion of titanium dioxide at a temperature of from about 150° C. to about 350° C. and forming a second portion of titanium dioxide at a temperature of from about 350° C. to about 600° C. A high-k dielectric material is also disclosed.
    Type: Application
    Filed: August 11, 2010
    Publication date: February 16, 2012
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Tsai-Yu Huang, Ching-Kai Lin
  • Publication number: 20120032311
    Abstract: An in-situ process is described incorporating plasma enhanced chemical vapor deposition comprising flowing at least one of a Si, Si+C, B, Si+B, Si+B+C, and B+C containing precursor, and a N containing precursors at first times and removing the N precursor at second times and starting the flow of an oxidant gas and a porogen gas into the chamber. A dielectric layer is described comprising a network having inorganic random three dimensional covalent bonding throughout the network which contains at least one SiCN, SiCNH, SiN, SiNH, BN, BNH, CBN, CBNH, BSiN, BSiNH, SiCBN and SiCBNH as a first component and a low k dielectric as a second component adjacent thereto.
    Type: Application
    Filed: August 9, 2010
    Publication date: February 9, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Stephen M. Gates, Alfred Grill, Son V. Nguyen, Satyanarayana V. Nitta
  • Publication number: 20120003814
    Abstract: Methods and systems are disclosed for performing a passivation process on a silicon-on-insulator wafer in a chamber in which the wafer is cleaved. A bonded wafer pair is cleaved within the chamber to form the silicon-on-insulator (SOI) wafer. A cleaved surface of the SOI wafer is then passivated in-situ by exposing the cleaved surface to a passivating substance. This exposure to a passivating substance results in the formation of a thin layer of oxide on the cleaved surface. The silicon-on-insulator wafer is then removed from the chamber. In other embodiments, the silicon-on-insulator wafer is first transferred to an adjoining chamber where the wafer is then passivated. The wafer is transferred to the adjoining chamber without exposing the wafer to the atmosphere outside the chambers.
    Type: Application
    Filed: June 16, 2011
    Publication date: January 5, 2012
    Applicant: MEMC ELECTRONIC MATERIALS, INC.
    Inventors: Michael J. Ries, Dale A. Witte, Anca Stefanescu, Andrew M. Jones
  • Publication number: 20110318941
    Abstract: A solar cell includes a first electrode located over a substrate, at least one p-type semiconductor absorber layer located over the first electrode, the p-type semiconductor absorber layer comprising a copper indium selenide (CIS) based alloy material, an n-type semiconductor layer located over the p-type semiconductor absorber layer, an insulating aluminum zinc oxide layer located over the n-type semiconductor layer, the insulating aluminum zinc oxide having an aluminum content of 100 ppm to 5000 ppm and a second electrode over the insulating aluminum layer, the second electrode being transparent and electrically conductive. The insulating aluminum zinc oxide having an aluminum content of 100 ppm to 5000 ppm, may be deposited by pulsed DC, non-pulsed DC, or AC sputtering from an aluminum doped zinc oxide having an aluminum content of 100 ppm to 5000 ppm.
    Type: Application
    Filed: September 1, 2011
    Publication date: December 29, 2011
    Inventors: Chris Schmidt, Bruce Hachtmann
  • Publication number: 20110300717
    Abstract: Embodiments of the invention describe methods for forming fluorocarbon (CF) films for semiconductor devices. According to one embodiment, the method includes providing a substrate, depositing a CF film on the substrate, generating, in the absence of a plasma, a treatment gas containing a gaseous specie having a molecular dipole, and treating the CF film with the treatment gas containing the gaseous specie having the molecular dipole to reduce the number of dangling bonds in the CF film. According to some embodiments, the method further includes depositing a second CF film on the treated CF film. According to some embodiments, the CF films may be deposited using a microwave plasma source containing a radial line slot antenna (RLSA).
    Type: Application
    Filed: June 3, 2011
    Publication date: December 8, 2011
    Applicant: TOKYO ELECTRON LIMITED
    Inventor: Yoshiyuki Kikuchi
  • Publication number: 20110298028
    Abstract: Embodiments of a dielectric layer containing a hafnium tantalum titanium oxide film structured as one or more monolayers include the dielectric layer disposed in an integrated circuit. Embodiments of methods of fabricating such a dielectric layer provide a dielectric layer for use in a variety of electronic devices. An embodiment may include forming hafnium tantalum titanium oxide film using a monolayer or partial monolayer sequencing process such as atomic layer deposition.
    Type: Application
    Filed: August 12, 2011
    Publication date: December 8, 2011
    Inventors: Kie Y. Ahn, Leonard Forbes
  • Patent number: 8063452
    Abstract: A gate insulating film having a high dielectric constant, a semiconductor device provided with the gate insulating film, and a method for manufacturing such film and device are provided. The semiconductor device is provided with a group 14 (IVA) semiconductor board and a first oxide layer. The first oxide layer is composed of MO2 existing on the board, where M is a first metal species selected from the group 4 (IVB); and M?xOy, where M? is a second metal species selected from the group 3 (IIIB) and a group composed of lanthanide series, and x and y are integers decided by the oxidation number of M.
    Type: Grant
    Filed: August 30, 2005
    Date of Patent: November 22, 2011
    Assignee: The University of Tokyo
    Inventors: Akira Toriumi, Koji Kita, Kazuyuki Tomida, Yoshiki Yamamoto
  • Patent number: 8030139
    Abstract: A method of producing a thin film transistor includes a gate electrode formation step that forms a gate electrode on a substrate, a gate insulating layer formation step that forms a gate insulating layer on the substrate in such a manner as to cover the gate electrode formed in the gate electrode formation step, a source/drain electrodes formation step that forms a source electrode and a drain electrode on the gate insulating layer, and a semiconductor layer formation step that applies an aqueous solution for semiconductor layer formation which is an aqueous solution comprising at least a single wall carbon nanotube and a surfactant between the source electrode and the drain electrode formed in the source/drain electrodes formation step by a coating process to form a semiconductor layer comprising the single wall carbon nanotube.
    Type: Grant
    Filed: March 25, 2009
    Date of Patent: October 4, 2011
    Assignee: Brother Kogyo Kabushiki Kaisha
    Inventors: Takeshi Asano, Taishi Takenobu, Masashi Shiraishi
  • Publication number: 20110227142
    Abstract: Memories, systems, and methods for forming memory cells are disclosed. One such memory cell includes a charge storage node that includes nanodots over a tunnel dielectric and a protective film over the nanodots. In another memory cell, the charge storage node includes nanodots that include a ruthenium alloy. Memory cells can include an inter-gate dielectric over the protective film or ruthenium alloy nanodots and a control gate over the inter-gate dielectric. The protective film and ruthenium alloy can be configured to protect at least some of the nanodots from vaporizing during formation of the inter-gate dielectric.
    Type: Application
    Filed: March 22, 2010
    Publication date: September 22, 2011
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: D.V. Nirmal Ramaswamy, Matthew N. Rocklein, Rhett Brewer
  • Publication number: 20110217850
    Abstract: Methods of fabricating an oxide layer on a semiconductor substrate are provided herein. The oxide layer may be formed over an entire structure disposed on the substrate, or selectively formed on a non-metal containing layer with little or no oxidation of an exposed metal-containing layer. The methods disclosed herein may be performed in a variety of process chambers, including but not limited to decoupled plasma oxidation chambers, rapid and/or remote plasma oxidation chambers, and/or plasma immersion ion implantation chambers. In some embodiments, a method may include providing a substrate comprising a metal-containing layer and non-metal containing layer; and forming an oxide layer on an exposed surface of the non-metal containing layer by exposing the substrate to a plasma formed from a process gas comprising a hydrogen-containing gas, an oxygen-containing gas, and at least one of a supplemental oxygen-containing gas or a nitrogen-containing gas.
    Type: Application
    Filed: May 18, 2011
    Publication date: September 8, 2011
    Applicant: APPLIED MATERIALS, INC.
    Inventors: RAJESH MANI, NORMAN TAM, TIMOTHY W. WEIDMAN, YOSHITAKA YOKOTA
  • Publication number: 20110183527
    Abstract: In a method of forming a layer, a precursor composition including a metal and a ligand chelating to the metal is stabilized by contacting the precursor composition with an electron donating compound to provide a stabilized precursor composition onto a substrate. A reactant is introduced onto the substrate to bind to the metal in the stabilized precursor composition. The stabilized precursor composition is provided onto the substrate by introducing the precursor composition onto the substrate after the electron donating compound is introduced onto the substrate. The electron donating compound is continuously introduced onto the substrate during and after the precursor composition is introduced.
    Type: Application
    Filed: February 25, 2011
    Publication date: July 28, 2011
    Inventors: Youn-Joung Cho, Youn-Soo Kin, Kyu-Ho Cho, Jung-Ho Lee, Jae-Hyoung Choi, Seung-Min Ryu
  • Publication number: 20110171836
    Abstract: Methods for forming a film on a substrate in a semiconductor manufacturing process. A reaction chamber a substrate in the chamber are provided. A ruthenium based precursor, which includes ruthenium tetroxide dissolved in a mixture of at least two non-flammable fluorinated solvents, is provided and a ruthenium containing film is produced on the substrate.
    Type: Application
    Filed: January 20, 2011
    Publication date: July 14, 2011
    Applicant: Air Liquide Electronics U.S. LP
    Inventors: Bin Xia, Ashutosh Misra
  • Publication number: 20110165780
    Abstract: A method of forming ruthenium-containing films by atomic layer deposition is provided. The method comprises delivering at least one precursor to a substrate, the at least one precursor corresponding in structure to Formula I: (L)Ru(CO)3 wherein L is selected from the group consisting of a linear or branched C2-C6-alkenyl and a linear or branched C1-6-alkyl; and wherein L is optionally substituted with one or more substituents independently selected from the group consisting of C2-C6-alkenyl, C1-6-alkyl, alkoxy and NR1R2; wherein R1 and R2 are independently alkyl or hydrogen.
    Type: Application
    Filed: May 29, 2009
    Publication date: July 7, 2011
    Applicant: Sigma-Aldrich Co.
    Inventors: Ravi Kanjolia, Rajesh Odedra, Jeff Anthis, Neil Boag
  • Patent number: 7972980
    Abstract: A method of forming a conformal dielectric film having Si—N bonds on a semiconductor substrate by plasma enhanced chemical vapor deposition (PECVD) includes: introducing a nitrogen- and hydrogen-containing reactive gas and a rare gas into a reaction space inside which a semiconductor substrate is placed; applying RF power to the reaction space; and introducing a hydrogen-containing silicon precursor as a first precursor and a hydrocarbon gas as a second precursor in pulses into the reaction space wherein a plasma is excited, thereby forming a conformal dielectric film doped with carbon and having Si—N bonds on the substrate.
    Type: Grant
    Filed: May 12, 2010
    Date of Patent: July 5, 2011
    Assignee: ASM Japan K.K.
    Inventors: Woo Jin Lee, Akira Shimizu
  • Patent number: 7939453
    Abstract: A method of producing an organic transistor which can form directly an organic semiconductor layer in pattern by simple processes and can produce an organic transistor excellent in transistor characteristics.
    Type: Grant
    Filed: February 26, 2009
    Date of Patent: May 10, 2011
    Assignees: Dai Nippon Printing Co., Ltd., Riken
    Inventors: Masataka Kano, Kazuhito Tsukagoshi, Takeo Minari
  • Patent number: 7923383
    Abstract: This invention relates to a method of treating a semiconductor wafer and in particular, but not exclusively, to planarisation. The method consists of depositing a liquid short-chain polymer formed from a silicon containing bas or vapour. Subsequently water and OH are removed and the layer is stabilised.
    Type: Grant
    Filed: March 28, 2003
    Date of Patent: April 12, 2011
    Assignee: Tokyo Electron Limited
    Inventors: Knut Beekmann, Guy Patrick Tucker
  • Patent number: 7919416
    Abstract: A method of forming a conformal dielectric film having Si—N bonds on a semiconductor substrate by plasma enhanced chemical vapor deposition (PECVD) includes: introducing a nitrogen- and hydrogen-containing reactive gas and an additive gas into a reaction space inside which a semiconductor substrate is placed; applying RF power to the reaction space; and introducing a hydrogen-containing silicon precursor in pulses into the reaction space wherein a plasma is excited, thereby forming a conformal dielectric film having Si—N bonds on the substrate.
    Type: Grant
    Filed: January 21, 2009
    Date of Patent: April 5, 2011
    Assignee: ASM Japan K.K.
    Inventors: Woo-Jin Lee, Akira Shimizu, Atsuki Fukazawa
  • Publication number: 20110062561
    Abstract: A method of manufacturing a semiconductor device comprising: forming a p type region and an n type region in a main surface of a semiconductor substrate, the p type region and the n type region being insulated from each other with an element-isolation region; forming a first insulating film on the p type region and on the n type region, the first insulating film being made of any one of a silicon oxide film and a silicon oxynitride film; forming a lanthanum oxide film on the first insulating film on the p type region; forming a second insulating film both on the lanthanum oxide film on the p type region and on the first insulating film on the n type region, the second insulating film containing any one of hafnium and zirconium; and forming a titanium nitride film on the second insulating film, the titanium nitride film satisfying TixNy where x/y<1.
    Type: Application
    Filed: September 10, 2010
    Publication date: March 17, 2011
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Nao AKIYAMA, Seiji INUMIYA
  • Patent number: 7902001
    Abstract: Provided is a sacrifice layer formed on a first substrate. A thin film laminated body is formed on the sacrifice layer. A separation groove exposing the sacrifice layer is formed to divide the thin film laminated body into at least one thin film device. The sacrifice layer is partially removed using a dry etching process. After the partial removal of the sacrifice layer, a remaining sacrifice layer region maintains the thin film device on the first substrate. A supporting structure is temporarily joined to the thin film device. The thin film device joined to the supporting structure is separated from the first substrate. Then, the remaining sacrifice layer is removed. The thin film device joined to the supporting structure is joined to a second substrate. Finally, the supporting structure is separated from the thin film device.
    Type: Grant
    Filed: June 5, 2009
    Date of Patent: March 8, 2011
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Sang Jin Kim, Yongsoo Oh, Hwan-Soo Lee
  • Publication number: 20110042790
    Abstract: A method of double patterning a semiconductor structure with a single material which after patterning becomes a permanent part of the semiconductor structure. More specifically, a method to form a patterned semiconductor structure with small features is provided which are difficult to obtain using conventional exposure lithographic processes. The method of the present invention includes the use of patternable low-k materials which after patterning remain as a low-k dielectric material within the semiconductor structure. The method is useful in forming semiconductor interconnect structures in which the patternable low-k materials after patterning and curing become a permanent element, e.g., a patterned interlayer low-k material, of the interconnect structure.
    Type: Application
    Filed: August 24, 2009
    Publication date: February 24, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Qinghuang Lin
  • Publication number: 20110028002
    Abstract: A method of forming a semiconductor device includes the following processes. A metal nitride film is formed with a thickness of 3 nm or less over a substrate. The metal nitride film is oxidized to form a metal oxide film. A set of the formation of the metal nitride film and the oxidation of the metal nitride film is repeated, to form a stack of the metal oxide films over the substrate.
    Type: Application
    Filed: July 27, 2010
    Publication date: February 3, 2011
    Applicant: ELPIDA MEMORY, INC.
    Inventor: Toshiyuki HIROTA
  • Publication number: 20110012238
    Abstract: A dielectric capping layer having a dielectric constant of less than 4.2 is provided that exhibits a higher mechanical and electrical stability to UV and/or E-Beam radiation as compared to conventional dielectric capping layers. Also, the dielectric capping layer maintains a consistent compressive stress upon post-deposition treatments. The dielectric capping layer includes a tri-layered dielectric material in which at least one of the layers has good oxidation resistance, is resistance to conductive metal diffusion, and exhibits high mechanical stability under at least UV curing. The low k dielectric capping layer also includes nitrogen content layers that contain electron donors and double bond electrons. The low k dielectric capping layer also exhibits a high compressive stress and high modulus and is stable under post-deposition curing treatments, which leads to less film and device cracking and improved device reliability.
    Type: Application
    Filed: July 14, 2009
    Publication date: January 20, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Stephan A. Cohen, Alfred Grill, Thomas J. Haigh, JR., Xiao H. Liu, Son V. Nguyen, Thomas M. Shaw, Hosadurga Shobha
  • Publication number: 20110003482
    Abstract: Provided is a method of manufacturing a semiconductor device. In the method, an aluminium-containing insulation film is formed on an electrode film of a substrate by alternately repeating a process of supplying an aluminium precursor into a processing chamber in which the substrate is accommodated and exhausting the aluminium precursor from the processing chamber and a process of supplying an oxidizing or nitriding precursor into the processing chamber and exhausting the oxidizing or nitriding precursor from the processing chamber; and a high permittivity insulation film different from the aluminium-containing insulation film is formed on the aluminium-containing insulation film by alternately repeating a process of supplying a precursor into the processing chamber and exhausting the precursor from the processing chamber and a process of supplying an oxidizing precursor into the processing chamber and exhausting the oxidizing precursor from the processing chamber.
    Type: Application
    Filed: June 28, 2010
    Publication date: January 6, 2011
    Applicant: HITACHI-KOKUSAI ELECTRIC INC.
    Inventors: Arito Ogawa, Sadayoshi Horii, Taketoshi SATO, Hideharu Itatani, Nobuyuki MISE, Osamu Tonomura
  • Publication number: 20100330814
    Abstract: Methods for processing substrates are provided herein. In some embodiments, a method for processing a substrate includes providing a substrate having an oxide layer disposed thereon, the oxide layer including one or more defects; and exposing the oxide layer to a plasma formed from a process gas comprising an oxygen-containing gas to repair the one or more defects. In some embodiments, the oxide layer may be formed on the substrate. In some embodiments, forming the oxide layer further comprises depositing the oxide layer atop the substrate. In some embodiments, forming the oxide layer further comprises thermally oxidizing the surface of the substrate to form the oxide layer. In some embodiments, a processing temperature is maintained at about 700 degrees Celsius or below during the thermal oxidation of the surface.
    Type: Application
    Filed: June 22, 2010
    Publication date: December 30, 2010
    Applicant: APPLIED MATERIALS, INC.
    Inventors: Yoshitaka Yokota, Christopher S. Olsen, Agus Sofian Tjandra, Yonah Cho, Matthew S. Rogers
  • Publication number: 20100320547
    Abstract: A stack of a high-k gate dielectric and a metal gate structure includes a lower metal layer, a scavenging metal layer, and an upper metal layer. The scavenging metal layer meets the following two criteria 1) a metal (M) for which the Gibbs free energy change of the reaction Si+2/y MxOy?2x/y M+SiO2 is positive 2) a metal that has a more negative Gibbs free energy per oxygen atom for formation of oxide than the material of the lower metal layer and the material of the upper metal layer. The scavenging metal layer meeting these criteria captures oxygen atoms as the oxygen atoms diffuse through the gate electrode toward the high-k gate dielectric. In addition, the scavenging metal layer remotely reduces the thickness of a silicon oxide interfacial layer underneath the high-k dielectric. As a result, the equivalent oxide thickness (EOT) of the total gate dielectric is reduced and the field effect transistor maintains a constant threshold voltage even after high temperature processes during CMOS integration.
    Type: Application
    Filed: June 18, 2009
    Publication date: December 23, 2010
    Applicant: International Business Machines Corporation
    Inventors: Takashi Ando, Changhwan Choi, Martin M. Frank, Vijay Narayanan
  • Patent number: 7855121
    Abstract: Provided are a method of forming an organic semiconductor thin film and a method of manufacturing a semiconductor device using the. According to example embodiments, a method of forming an organic semiconductor thin film at least may include exposing a lower substrate coated with an organic semiconductor solution using a method of generating a shearing stress to the portion of the lower substrate coated with the organic semiconductor solution. A guide structure may be formed adjacent to the organic semiconductor solution.
    Type: Grant
    Filed: March 27, 2009
    Date of Patent: December 21, 2010
    Assignees: Samsung Electronics Co., Ltd., The Board of Trustees of the Laland Stanford Junior University
    Inventors: Do Hwan Kim, Sangyoon Lee, Hector Alejandro Becerril Garcia, Mark Roberts, Zhenan Bao, Zihong Liu
  • Publication number: 20100283106
    Abstract: A semiconductor device in which a semiconductor layer is formed on an insulating substrate with a front-end insulating layer interposed between the semiconductor layer and the insulating substrate is provided which is capable of preventing action of an impurity contained in the insulating substrate on the semiconductor layer and of improving reliability of the semiconductor device. In a TFT (Thin Film Transistor), boron is made to be contained in a region located about 100 nm or less apart from a surface of the insulating substrate so that boron concentration decreases at an average rate being about 1/1000-fold per 1 nm from the surface of the insulating substrate toward the semiconductor layer.
    Type: Application
    Filed: July 22, 2010
    Publication date: November 11, 2010
    Applicants: NEC CORPORATION, NEC LCD TECHNOLOGIES, LTD.
    Inventor: Shigeru MORI
  • Publication number: 20100279515
    Abstract: A method for forming an atomic deposition layer is provided, which includes: (a) performing a first water pulse on a substrate; (b) performing a precursor pulse on the hydroxylated substrate, wherein the precursor reacts with the hydroxyl groups and forms a layer; (c) purging the substrate with an inert carrier gas; (d) exposing the layer to a second water pulse for at least about 3 seconds so that the layer has a minimum of 70 percent of surface hydroxyl groups thereon; (e) purging the layer with the inert carrier gas; and (f) repeating steps (b) to (e) to form a resultant atomic deposition layer.
    Type: Application
    Filed: June 3, 2010
    Publication date: November 4, 2010
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chen-Hua YU, Liang-Gi YAO
  • Publication number: 20100244206
    Abstract: A method of forming a device includes providing a substrate, forming an interfacial layer on the substrate, depositing a high-k dielectric layer on the interfacial layer, depositing an oxygen scavenging layer on the high-k dielectric layer and performing an anneal. A high-k metal gate transistor includes a substrate, an interfacial layer on the substrate, a high-k dielectric layer on the interfacial layer and an oxygen scavenging layer on the high-k dielectric layer.
    Type: Application
    Filed: March 31, 2009
    Publication date: September 30, 2010
    Applicant: International Business Machines Corporation
    Inventors: Huiming Bu, Michael P. Chudzik, Wei He, Rashmi Jha, Young-Hee Kim, Siddarth A. Krishnan, Renee T. Mo, Naim Moumen, Wesley C. Natzle
  • Publication number: 20100221923
    Abstract: A semiconductor device includes: a structure comprising at least two heterogeneous layers having different stress levels; and a stress relief layer disposed between the two heterogeneous layers to relive a difference in the stress levels. The stress relief layer may include: a first layer formed over a first heterogeneous layer; a second layer formed over the first layer; and a third layer formed between the second layer and a second heterogeneous layer.
    Type: Application
    Filed: March 31, 2010
    Publication date: September 2, 2010
    Inventors: Hyun AHN, Jeong-Hoon PARK
  • Patent number: 7759205
    Abstract: Methods for producing a semiconductor device are provided. In one embodiment, a method includes the steps of: (i) fabricating a partially-completed semiconductor device including a substrate, a source/drain region in the substrate, a gate stack overlaying the substrate, and a sidewall spacer adjacent the gate stack; (ii) utilizing an anisotropic etch to remove an upper portion of the sidewall spacer while leaving intact a lower portion of the sidewall spacer overlaying the substrate; (iii) implanting ions in the source/drain region; and (iv) annealing the semiconductor device to activate the implanted ions. The step of annealing is performed with the lower portion of the sidewall spacer intact to deter the ingress of oxygen into the substrate and minimize under-oxide regrowth proximate the gate stack.
    Type: Grant
    Filed: January 16, 2009
    Date of Patent: July 20, 2010
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Kingsuk Maitra, John Iacoponi
  • Publication number: 20100176442
    Abstract: A dielectric containing a titanium silicon oxide film disposed in an integrated circuit and a method of fabricating such a dielectric provide a dielectric for use in a variety of electronic devices. Embodiments include a dielectric containing a titanium silicon oxide film arranged as one or more monolayers. Embodiments include structures for capacitors, transistors, memory devices, and electronic systems with dielectrics containing a titanium silicon oxide film, and methods for forming such structures.
    Type: Application
    Filed: March 24, 2010
    Publication date: July 15, 2010
    Inventors: Kie Y. Ahn, Leonard Forbes
  • Patent number: 7754503
    Abstract: A plasma of a gas containing an impurity is produced through a discharge in a vacuum chamber, and a plurality of substrates are successively doped with the impurity by using the plasma, wherein a plasma doping condition of a subject substrate is adjusted based on an accumulated discharge time until the subject substrate is placed in the vacuum chamber.
    Type: Grant
    Filed: January 9, 2008
    Date of Patent: July 13, 2010
    Assignee: Panasonic Corporation
    Inventors: Yuichiro Sasaki, Katsumi Okashita, Keiichi Nakamoto, Hiroyuki Ito, Bunji Mizuno
  • Publication number: 20100173467
    Abstract: A thin film is used in a semiconductor device manufacturing process. The thin film contains silicon, germanium, and oxygen.
    Type: Application
    Filed: May 19, 2008
    Publication date: July 8, 2010
    Applicant: Tokyo Electron Limited
    Inventors: Yoshihiro Kato, Noriaki Fukiage
  • Publication number: 20100136789
    Abstract: A method is provided for depositing a dielectric barrier film including a precursor with silicon, carbon, oxygen, and hydrogen with improved barrier dielectric properties including lower dielectric constant and superior electrical properties. This method will be important for barrier layers used in a damascene or dual damascene integration for interconnect structures or in other dielectric barrier applications. In this example, specific structural properties are noted that improve the barrier performance.
    Type: Application
    Filed: November 23, 2009
    Publication date: June 3, 2010
    Applicant: Air Products and Chemicals, Inc.
    Inventors: Laura M. Matz, Raymond Nicholas Vrtis, Mark Leonard O'Neill, Dino Sinatore
  • Publication number: 20100081241
    Abstract: A semiconductor device includes an operating layer made of a semiconductor and a silicon nitride film formed on the operating layer with the use of a mixed gas that includes mono-silane gas, hydrogen gas, and nitrogen gas, by a plasma CVD apparatus, under a condition that a flow rate of the hydrogen gas is 0.2 percent to 5 percent to an overall flow rate.
    Type: Application
    Filed: December 4, 2009
    Publication date: April 1, 2010
    Applicant: EUDYNA DEVICES INC.
    Inventor: Norikazu IWAGAMI
  • Publication number: 20100075507
    Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes providing a substrate, forming an interfacial layer on the substrate by treating the substrate with radicals, and forming a high-k dielectric layer on the interfacial layer. The radicals are selected from the group consisting of hydrous radicals, nitrogen/hydrogen radicals, and sulfur/hydrogen radicals.
    Type: Application
    Filed: August 31, 2009
    Publication date: March 25, 2010
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Che-Hao Chang, Cheng-Hao Hou, Chen-Hua Yu, Tai-Bor Wu
  • Publication number: 20100062614
    Abstract: Embodiments of the invention provide a method for treating the inner surfaces of a processing chamber and depositing a material on a during a vapor deposition process, such as atomic layer deposition (ALD) or by chemical vapor deposition (CVD). In one embodiment, the inner surfaces of the processing chamber and the substrate may be exposed to a reagent, such as a hydrogenated ligand compound during a pretreatment process. The hydrogenated ligand compound may be the same ligand as a free ligand formed from the metal-organic precursor used during the subsequent deposition process. The free ligand is usually formed by hydrogenation or thermolysis during the deposition process. In one example, the processing chamber and substrate are exposed to an alkylamine compound (e.g., dimethylamine) during the pretreatment process prior to conducting the vapor deposition process which utilizes a metal-organic chemical precursor having alkylamino ligands, such as pentakis(dimethylamino) tantalum (PDMAT).
    Type: Application
    Filed: September 8, 2008
    Publication date: March 11, 2010
    Inventors: Paul F. Ma, Joseph F. Aubuchon, Mei Chang, Steven H. Kim, Dien-Yeh Wu, Norman M. Nakashima, Mark Johnson, Roja Palakodeti