Abstract: A display controller includes: a first memory that stores multiple frames of the image data; a second memory having a smaller storage capacity than that of the first memory, storing at least one frame of the image data; and a memory data switching circuit that outputs, either the image data read out from the first memory, the image data read out from the second memory, or the mixed data wherein the image data for single scanning read out from the first memory and the image data read out from the second memory are mixed. The display controller provides to the display driver, either the image data read out from the first memory, the image data red out from the second memory, or the mixed data.

Abstract: A format conversion apparatus which converts image data of a band interleave format into image data of a band separate format is provided. The apparatus includes a memory which stores image data of a band interleave format; and a converting module which reads the memory by increasing a read address of the memory for each stride, and converts the image data of the band interleave format into image data of a band separate format.

Abstract: A graphics processor 20 includes a graphics object list building unit 28 that determines the location of each draw call in a scene to be rendered and generates a list of draw calls for each sub-region (tile) that the scene to be rendered is divided into. The draw call lists are stored in a memory 23. A graphics object selection unit 29 of a renderer 22 of the graphics processor 20 then determines which draw call is to be rendered next by considering the draw call list 26 stored in the memory 23 for the sub-region (tile) of the scene that is currently being rendered.

Abstract: Time-lapsing mirror methods and related systems.

Abstract: A warning device in a vehicle includes at least one output unit for outputting at least one warning. A training mode for calling up warnings may be started via an input unit, in which the warnings are output following a call-up without a situation, for which a warning should be output, actually having to exist. Due to this fact, the driver may intuitively inform him/herself about the warning outputs.

Abstract: A system and method for effectively storing compressed information in an electronic device includes a memory device coupled to the electronic device for storing the compressed information. A compression module sequentially performs a forward write procedure to store first components of the compressed information. The forward write procedure begins at a top location of the memory device. The compression module concurrently performs a reverse write procedure to store second components and third components of the compressed information sequentially in an interlaced configuration. The reverse write procedure begins at a bottom location of the memory device.

Abstract: An exemplary method for performing a bit block transfer (bitblt) includes receiving one or more graphics parameters specifying the bitblt and generating a specialized bitblt function to perform the bitblt. The specialized bitblt function includes a one or more code blocks selected from a superset of code blocks based on the graphics parameters. A system includes a specialized bit block transfer (bitblt) function generator generating a specialized bitblt function to perform a specified bitblt. The specialized bitblt function includes intermediate language code corresponding to one or more graphics parameters specifying the bitblt. A translator translates the specialized bitblt function into machine-specific language code.

Abstract: A data record method using a touch panel is disclosed. The touch panel can be separated from a computer. The computer and the touch panel store data having plural records respectively. The method includes the steps: (A) determining if the touch panel is connected with the computer at work; (B) executing a synchronization procedure for data synchronization between the computer and the touch panel when connecting; and (C) displaying data stored in the touch panel when not connecting.

Abstract: A high-speed ring topology. In one embodiment, two base chip types are required: a “drawing” chip, LoopDraw, and an “interface” chip, LoopInterface. Each of these chips have a set of pins that supports an identical high speed point to point unidirectional input and output ring interconnect interface: the LoopLink. The LoopDraw chip uses additional pins to connect to several standard memories that form a high bandwidth local memory sub-system. The LoopInterface chip uses additional pins to support a high speed host computer host interface, at least one video output interface, and possibly also additional non-local interconnects to other LoopInterface chip(s).

Abstract: A display having a screen, and memory for storing picture data is disclosed. In one embodiment, the screen includes a plurality of pixels, the pixels in a first mode of the display being controlled by the picture data stored in the memory, and in a second mode of the display being controlled by picture data received from an external processing unit.

Abstract: Methods and systems of presenting video on a computer display having a visible display area are hereby disclosed. At least one video input is received from a video source. A video corresponding to the video put is displayed in a viewing region of the display. The viewing region can be of a size that occupies a fractional portion of the visible display area. The video can be displayed in a translucent fashion so that the video is visible and so that other content displayed on the computer display is visible through the video. After a period of user inactivity, the video can be displayed in an opaque fashion so that other content displayed on the computer display is hidden under the video.

Abstract: An image processing apparatus, able to suppress occurrence of a penalty such as page miss and able to efficiently draw an image, provided with a triangle transfer control device for judging whether a triangle is inside/outside a page, detecting a page where a triangle may be drawn, preparing a list of pages where triangles will be drawn, taking out a page from this list, outputting the triangle data and the corresponding drawing page data to a triangle drawing device so as to draw the object (triangle) for only the interior of the region of that page, erasing the output drawing page from the prepared list, and outputting triangle data and corresponding drawing page data until there are no longer pages on the list so as to draw all triangles in the pages.

Abstract: Methods and associated systems that allow a plurality of real-time multimedia applications to operate concurrently within a computer system with constrained primary memory. In particular, the methods and systems of the present invention allow for a plurality of real-time multimedia applications to operate concurrently while adapting to changing memory constraints imposed by the dynamic allocation and release of primary memory in a shared primary memory space.

Abstract: A digital photo frame includes: at least one storage device for storing a digital photo; a display device for displaying the digital photo; a light-sensing component disposed on the display device, and for detecting an intensity of environmental brightness and sending a signal; and a processing unit for processing the digital photo stored in the storage device and displaying the photo in the display device, and opening or closing a backlight module of the display device according to the signal from the light-sensing component. With this configure, the digital photo frame of the invention may save electric energy.

Abstract: A system and method for the display and control of virtual environments in a single pipe graphics memory controller hub using picture-in-picture. The system has a first virtual machine to render on a primary framebuffer, where the primary framebuffer has a picture-in-picture. The system also has a second virtual machine to render on a fake framebuffer. The operating system of the first virtual machine is different from the operating system of the second virtual machine. The system also has a driver. The driver to pass an offset address to an interface abstraction layer of the second virtual machine, where the offset address is to the beginning of the picture-in-picture. The driver to scale down the output of the fake framebuffer such that its contents will fit into the picture-in-picture and the driver to transfer the scaled down output onto the primary framebuffer at the offset address. By using hardware interrupts from a keyboard or mouse, control can switch between the primary and secondary systems (e.g.

Abstract: A printer includes a direct memory access controller (DMA), a video processor, and a video signal generator. A frequency synthesizer connects to the video signal generator. Configuration registers bidirectionally connect to the DMA, video processor, the video signal generator and the frequency synthesizer. A data bus electrically connects the DMA and the configuration registers.

Abstract: Methods and apparatuses for effectively clearing stencil buffers at high speed using surrogate stencil buffer clearing. A hardware register tracks the number of surrogate clears of the stencil buffer since the last actual clear. Bits are reserved in each stencil register for storing the surrogate clear number that cleared other stencil registers the last time the stencil register held an assigned value. A comparison between the contents of the hardware register and the reserved bits in each stencil register determines if each stencil register should be assigned a cleared value. If the numbers do not match the stencil register is assigned a predetermined surrogate clear value. In some applications the number of reserved bits is fixed, while in other applications the number of reserved bits can be set, either by a designer or by software.

Abstract: In a system comprising a plurality of processors and a memory shared by at least a subset of the processors, a method for processing video data includes the steps of: (a) a first one of the processors receiving a first video frame and storing the first video frame in the memory; (b) the first one of the processors receiving at least a second video frame, receipt of the second video frame initiating a release of the first video frame from the memory; (c) the first one of the processors sending the first and second video frames to a second one of the processors together for processing by the second one of the processors; (d) the second one of the processors generating an output video frame based at least on the first and second video frames; (e) storing the output video frame in the memory by overwriting an available memory location therein, the output video frame becoming a new first video frame; and (f) repeating steps (b) through (e) until all video frames to be processed have been received.

Abstract: A display control system for controlling display of images on a plurality of display units, the plurality of display units being arranged in an array, includes a determining unit determining whether or not information of interest is being displayed; a first recording control unit controlling recording of a first image displayed on the display units when the determining unit determines that the information of interest is being displayed; a second recording control unit controlling recording of a second image displayed on the display units when a user performs a recording operation; and a display control unit controlling display of the first image or the second image on the display units.

Abstract: An image-capturing apparatus is provided having a storage control device, a writing speed measuring device, and a selecting device. The storage control device writes image data into memory devices. The writing speed measuring device measures the writing speed of the memory devices by writing dummy data into the memory devices. The selecting device compares the writing speeds of the memory devices, and selects the memory device having the fastest writing speed. The storage control device stores image data in the selected memory device.

Abstract: A non-blocking always visible display application is provided to copy and save first pixel values corresponding to a first display screen area, blend the copied first pixel values with second pixel values corresponding to a non-blocking always visible display to generate third pixel values, and replace the original first pixel values with the third pixel values to effectuate display of the non-blocking always visible display. In one embodiment, the application further monitors for display operations that impact the first display screen area, and re-blend accordingly. In one embodiment, the re-blending and replacement are advantageously delayed. In another embodiment, the application further intercepts and causes cursor events to be handled properly, based at least in part on a current blending bias between the non-blocking always visible display, and the underlying display windows.

Abstract: Compressed memory systems are provided to reduce latency associated with accessing compressed memory using stratified compressed memory architectures and memory organization protocols in which a region of compressed main memory is allocated as a direct access memory (DAM) region for storing uncompressed data items. The uncompressed data items in the DAM region can be directly accessed, speculatively, to serve access requests to main memory, requiring access to compressed memory in the event of a DAM miss.

Abstract: An image display system includes an information processing apparatus and an image display apparatus. The information processing apparatus includes: an image processing unit that acquires image information and executes predetermined image processing for the acquired image information; a processed image in o mat ion acquisition command unit that gives an acquisition command to an image display apparatus connected with the information processing apparatus such that information is transmittable and receivable to and from the information processing apparatus via an information transmitting unit, which acquisition command commands the image display apparatus to acquire the processed image information processed by the image processing unit; and an information transmitting unit that transmits the processed image information and the acquisition command to the image display apparatus.

Abstract: Systems and method for providing shared attribute evaluation circuits in a graphics processing unit are provided. One embodiment can be described as a system for evaluating attributes in a graphics processing unit having a plurality of processing stages. The system can include an evaluation block, configured to process a plurality of attributes corresponding to a plurality of pixels and a plurality of FIFO buffers, each configured between one of the plurality of processing stages and the evaluation block. An embodiment can further include a shared buffer, configured to store the plurality of attributes or pointers during the attribute processing and processing priority logic, configured to determine a plurality of priorities corresponding to the plurality of attributes.

Abstract: In order to reduce degradation of the processing performance of the data processor due to use of a part of the main memory as a display frame buffer, when an access request to the memory 200 is generated from the CPU 310, the memory controller 400 holds it once, requests the display controller 560 to stop the access to the memory 200 which is in execution, when data to the access executed already is transferred from the memory 200, holds it, and transfers the access request from the CPU bus 310 which is held by the memory 200. When the access from the CPU bus 310 ends, the memory controller 400 restarts the access stopped in the display controller 560 and passes the held data to the display controller 560.

Abstract: The present invention allows highly efficient high-speed data processing based on dynamic data federation among a plurality of data display means, without increasing the data volume in the individual data display means. A user data display section has a classification and component specific information table, which is extracted from a three-dimensional component database and a two-dimensional component database, and a component attribute data table associated thereto. A federation control section controls data federation among a three-dimensional component data display section, two-dimensional component data display section and user data display section.

Abstract: Techniques are described for processing computerized images with a graphics processing unit (GPU) using an extended vertex cache. The techniques include creating an extended vertex cache coupled to a GPU pipeline to reduce an amount of data passing through the GPU pipeline. The GPU pipeline receives an image geometry for an image, and stores attributes for vertices within the image geometry in the extended vertex cache. The GPU pipeline only passes vertex coordinates that identify the vertices and vertex cache index values that indicate storage locations of the attributes for each of the vertices in the extended vertex cache to other processing stages along the GPU pipeline. The techniques described herein defer the setup of attribute gradients to just before attribute interpolation in the GPU pipeline. The vertex attributes may be retrieved from the extended vertex cache for attribute gradient setup just before attribute interpolation in the GPU pipeline.

Abstract: There is disclosed a display device which is driven by a two-field drive scheme. That is, brightness corresponding to one frame of image is obtained in two scans. The display screen is divided into plural regions. One of the regions is driven by a black insertion method. The other region is driven by a pseudo-normal drive method. In this method, an image based on the same display data is displayed twice. The display data is converted such that the gamma characteristics of the pseudo-normally driven region are substantially equal to the gamma characteristics of the region driven by the black insertion method. If necessary, each individual pixel in the boundary region between the region driven by the black insertion method and the region driven by the pseudo-normal drive method is displayed black or white. The boundary region has a width of at least two pixels.

Abstract: Image data storage areas of a plurality of pages are allocated for each of a plurality of display planes capable of superimposed display, and display output processing is performed while switching between the image data storage areas is being performed for each display plane. In such a display system, versatile switching between image data storage areas is enabled without heavily loading a central processing unit. Attribute bits of a TRAP command indicating the termination of drawing of one display plane are provided with display switching enable bits indicating whether to perform switching between image data storage areas for each display plane. For display planes corresponding to the display switching enable bits of “1”, switching to an image data storage area from which image data is read is performed at timing synchronous with a next vertical synchronous signal.

Abstract: A portable data processing device with one touch control and a switching method thereof apply to the portable data processing device with a touch pad and a built-in one touch control official system, and users can directly press the key on the touch pad to execute the corresponding application program or function.

Abstract: A multimedia data reproduction apparatus comprises the following: a resizer for resizing a decoded multimedia data according to information corresponding to a display definition; a memory for storing the resized multimedia data; and a memory controller for allocating the memory to store the resized multimedia data according to the information. The memory controller can allocate the memory in response to various display definitions.

Abstract: Apparatus, systems and methods for handling portrait mode oriented display surfaces without requiring expensive hardware in the display sub-system are disclosed. For example, an apparatus is disclosed such that the rendering of graphics data to the portrait mode display surfaces is redirected at rendering time such that there is no need for adding complicated hardware in the display part of the graphics adapter in order to handle conventional displays—all of which have no circuitry to deal with data natively stored in a portrait mode surface. Additionally, an apparatus to handle direct surface access of a surface through a surface lock which has already been rotated is already described. This can either be done by copying of surface data or by an optimized proposed apparatus which eliminates this copy. Other implementations are also disclosed.

Abstract: Embodiments of the invention generally provide a method for configuring an overlay window in a volatile memory device. In one embodiment, the method includes receiving a first command which provides at least a portion of a base address for the overlay window, wherein the overlay window comprises a range of memory addresses, and receiving a second command which provides a size of the overlay window. An access command received by the volatile memory device is used to access a memory array of the volatile memory device if an address of the access command is outside of the overlay window. The access command received by the volatile memory device is used to access a memory location outside of the memory array if the address of the access command is within the overlay window.

Abstract: In one embodiment of the present invention, a system for displaying images in at least one display window on a display unit includes a display processor configured to generate graphics commands from a received input. A graphics processing unit is coupled to the display processor and includes rendering engine configured to generate graphic data from the graphics commands, an internal memory coupled to the rendering engine, and a general purpose I/O coupled to the rendering engine and configured to transmit messages from the graphics processing unit. A graphics logic device is coupled to the graphics processing unit. The graphics logic device is configured to initiate a transfer of graphic data for an update of a display window from the internal memory to the display unit upon receipt of a message indicative of an available update to the display window.

Abstract: Disclosed are methods and systems that allow video applications to merge their outputs for display and to transform the outputs of other applications before display. A graphics arbiter tells applications the estimated time when the next frame will be displayed on a display screen. Applications tailor their output to the estimated display time. When output from a first application is incorporated into a scene produced by a second application, the graphics arbiter “offsets” the estimated display time it gives to the first application in order to compensate for the latency caused by the second application's processing of the first application's output. A set of overlay buffers parallels the traditional buffers used to prepare frames for the display screen. In composing a frame, the screen merges video information from a traditional buffer with that from an overlay buffer, conserving display resources at the final point in the display composition process.

Abstract: Disclosed are methods and systems that allow video applications to merge their outputs for display and to transform the outputs of other applications before display. A graphics arbiter tells applications the estimated time when the next frame will be displayed on a display screen. Applications tailor their output to the estimated display time. When output from a first application is incorporated into a scene produced by a second application, the graphics arbiter “offsets” the estimated display time it gives to the first application in order to compensate for the latency caused by the second application's processing of the first application's output. A set of overlay buffers parallels the traditional buffers used to prepare frames for the display screen. In composing a frame, the screen merges video information from a traditional buffer with that from an overlay buffer, conserving display resources at the final point in the display composition process.

Abstract: A game apparatus includes a first LCD and a second LCD. The first LCD and the second LCD are arranged in either side of a predetermined axis. A computer of the game apparatus respectively displays a first character image and a second character image on the first LCD and the second LCD, and further respectively displays a first message image and a second message image on the first LCD and the second LCD. Then, in response to a predetermined operation performed via a touch panel, etc., at least one of the first message image and the second message image respectively displayed on the first LCD and the second LCD is updated.

Abstract: A graphics processing system performs filtering of oversampled data during a scanout operation. Sample values are read from an oversampled frame buffer and filtered during scanout; the filtered color values (one per pixel) are provided to a display device without an intervening step of storing the filtered data in a frame buffer. In one embodiment, the filtering circuit includes a memory interface configured to read data values corresponding to sample points from a frame buffer containing the oversampled data; and a filter configured to receive the data values provided by the memory interface, to compute a pixel value from the data values, and to transmit the pixel value for displaying by a display device, wherein the filter computes the pixel value during a scanout operation.

Abstract: A method for delayed frame buffer merging. The method includes accessing a polygon that relates to a group of pixels stored at a memory location, wherein each of the pixels has an existing color. A determination is made as to which of the pixels are covered by the polygon, wherein each pixel includes a plurality of samples. A coverage mask is generated corresponding the samples that are covered by the polygon. The group of pixels is updated by storing the coverage mask and a color of the polygon in the memory location. At a subsequent time, the group of pixels is merged into a frame buffer.

Abstract: A computer graphics system is provided that includes a memory to store image data, a bin pointer list to store information regarding a plurality of image subscenes, and a pointer cache system to maintain data regarding the plurality of image subscenes. The pointer cache system may include a tag array section, a data array section and a decoupling section.

Abstract: A method, system, and computer readable medium including instructions for processing single definition or high definition video data to produce an two dimensional and three dimensional effects to occur at a future time. The effects are created in a video processing system using multiple threads.

Abstract: The invention discloses a screen control system including a panel, a magnetic member, at least three magnetic inductive (MI) sensors, and a processing unit. The magnetic member is used for indicating a specific position on the panel. Each of the MI sensors is located under the panel and used for sensing magnetic field of the magnetic member corresponding to the specific position. Afterward, each MI sensor will convert the sensed magnetic field into an output voltage correspondingly. The processing unit is coupled to each of the MI sensors and the panel. According to all of the output voltages, the processing unit will calculate a coordinate corresponding to the specific position. Accordingly, the screen control system is capable of displaying the specific position indicated by the magnetic member for the user.

Abstract: A method and system for protecting digital images copied from a video RAM, including the steps of transmitting stored pixel data from a computer memory to a video RAM, identifying protected pixel data within the stored pixel data, modifying the stored pixel data, thereby generating modified pixel data within which individual pixel datum is recognizable as being protected or unprotected, and, in response to pixel data being copied from the video RAM, replacing individual pixel datum copied from the video RAM, that is protected, with substitute pixel datum.

Abstract: An arithmetic logic unit (ALU) in a graphics processor is described. The ALU includes circuitry for performing an operation using a first set of pixel data. The first set of pixel data is resident in a pipeline register coupled to the circuitry. A temporary register is coupled to the circuitry. The temporary register can receive a result of the operation. The temporary register allows a result generated using one set of pixel data to be used with a subsequent set of pixel data in the same ALU. The result of the operation can thus be used in a second operation with a second set of pixel data that resides in the pipeline register after the first set of pixel data.

Abstract: A method for utilizing software to implement multiple power-up graphics in a single computer platform. The computer platform receives a power-up graphic mode and determined whether the power-up graphic mode is multiple graphic mode or general graphic mode. The computer platform then displays corresponding power-up graphics according to the power-up mode during power-up, implementing multiple power-up graphics to match IA functions or satisfy user preference.

Abstract: A secondary frame buffer is provided for use by classic applications designed to paint directly to a frame buffer. Classic applications paint their windows to the secondary frame buffer, not to the primary frame buffer. A compositor reads window data from the secondary frame buffer and paints it to the primary frame buffer. The compositor also reads window data written to back buffers by other applications and paints that data to the primary frame buffer. Since the compositor maintains visible region data for all windows, the windows are correctly painted to the primary frame buffer whether they are from the back-buffered windows or from classic applications. In addition, optimizations in classic applications that cause classic windows to be inappropriately painted over newer style windows no longer have this effect, since the compositor is responsible for painting legacy windows to the frame buffer, not the applications themselves.

Abstract: A data-playing controller includes a register for storing a plurality of control parameters, a first-in-first-out buffer (FIFO) for storing data, and a control circuit capable of accessing a memory dynamically. The register can be electrically connected to a data-playing device. The control circuit can store the control parameters via the FIFO to the memory first, and then transfer the control parameters stored in the memory via the FIFO to the register during a synchronizing blank period.

Abstract: Disclosed herein is an image processing apparatus, including: first storage means for storing data in a unit of a word; second storage means for storing data in a unit of a word, address information for managing writing and reading out of the data of a unit of a word and a correction flag which indicates, in a unit of a word, whether or not it is necessary to correct the data, in an associated relationship with each other; and supplying means for reading out and supplying the data of a unit of a word, corresponding address information and a corresponding correction flag stored in the second storage means to the first storage means; the first storage means referring to the address information to correct the data of a unit of a word corresponding to the correction flag to the data of a unit of a word.

Abstract: When a contention is detected between a memory write address and a display read address in a memory circuit which stores display data, a host retry pulse generating circuit generates a display read signal and a display line data transfer signal based on a memory write clock, and supplies these to the memory circuit while supplying the display line data transfer signal to a line latch circuit. Alternatively, upon detection of the contention above, a same line re-display read processing circuit performs same line re-display read processing without moving to the next line, and supplies a display read signal and a display line data transfer signal to the memory circuit while supplying the display line data transfer signal to the line latch circuit.

Abstract: A display system and method are provided. The system typically includes a display configured to control visible light, as well as to sense an optical signal projected thereon, the display being adapted to freeze a projected image by storing the optical signal associated with the live projected image in memory associated with the display and controlling visible light corresponding to the stored optical signal to form a frozen projection image.