Abstract: A chipset is electrically connected with an external graphic module, which generates a first graphic signal and outputs it to the chipset. The chipset includes an internal graphic module and a control module. The internal graphic module generates a second graphic signal, and the control module receives the first graphic signal and the second graphic signal. The control module divides the first graphic signal into at least two first graphic sub-signals and divides the second graphic signal into at least two second graphic sub-signals, respectively. When under a first output mode, the control module simultaneously outputs one of the first graphic sub-signals and one of the second graphic sub-signals.

Abstract: A graphics processor 1 includes after its tile rendering logic 40, a transaction elimination unit 5 that includes data block generation logic 41 and block comparison logic 43. The block generation logic 41 generates data blocks from the rendered tiles produced by the tile rendering logic 40. The data blocks are then stored in buffers 42. Comparison logic 43 then compares a new data block with the previous data block (which will already be stored in the buffers 42), and generates an output metadata bit indicating whether the blocks can be considered to be the same or not, on the basis of the comparison. The meta-data output bits are stored appropriately in a meta-data bitmap 45 in main memory 2 that is associated with the output data array in question. If the blocks are determined to be different by the comparison logic then the new data block is written from the buffers 42 to the frame buffer 44 in the main memory 2.

Abstract: A method of operating a Linear Complementarity Problem (LCP) solver is disclosed, where the LCP solver is characterized by multiple execution units operating in parallel to implement a competent computational method adapted to resolve physics-based LCPs in real-time.

Abstract: A video decoder organizes and stores pixel lines of a reference picture into first and second memory devices. The video decoder then reads portions of a pixel block from the first and second memory devices and processes such a pixel block for generating a subsequent picture. By reading from the first and second memory device with time overlap, latency is minimized for faster video decoding.

Abstract: Computer systems and methods that utilize a GPU whose operation is able to switch between ECC and non-ECC memory operations on demand. The computer system includes a graphics processing unit and a memory controller and local memory that are functionally integrated with the graphics processing unit. The memory controller has at least two operating modes comprising a first memory access mode that uses error checking and correction when accessing the local memory, and a second memory access mode that does not use error checking and correction when accessing the local memory. The memory controller is further operable to switch the operation of the memory controller between the first and second memory access modes without rebooting the computer system.

Abstract: A medical apparatus comprises a user interface for setting parameters and includes: a screen for visualizing values of said parameters, a main control unit connected to the interface, a first memory and a video memory both connected to the main control unit for storing data corresponding to images on screen; the main control unit allows setting of a new value for a parameter, displays the new value on a screen region, stores the new value in the first memory, captures from the video memory data representative of said screen region, verifies from said representative data if the displayed value corresponds to the value in the first memory. A method for setting up a medical apparatus is also disclosed.

Abstract: A video processing device may comprise one or more processors and/or circuits for use in a video processing device, in which the one or more processors and/or circuits may comprise a video scaler, a memory, a scaler engine, a clock selection circuit. The one or more processors and/or circuits are operable to receive a video image and select a video input clock or a display output clock for upscaling the received video image, or select the video input clock or the display output clock for downscaling the received video image based on a determination of whether the video image is to be downscaled or upscaled. The one or more circuits may be operable to downscale the received video image to generate a first scaled video image, and/or upscale the received video image to generate a second scaled video image, based on the selection.

Abstract: A method of organizing memory for storage of texture data, in accordance with one embodiment of the invention, includes accessing a size of a mipmap level of a texture map. A block dimension may be determined based on the size of the mipmap level. A memory space (e.g., computer-readable medium) may be logically divided into a plurality of whole number of blocks of variable dimension. The dimension of the blocks is measured in units of gobs and each gob is of a fixed dimension of bytes. A mipmap level of a texture map may be stored in the memory space. A texel coordinate of said mipmap level may be converted into a byte address of the memory space by determining a gob address of a gob in which the texel coordinate resides and determining a byte address within the particular gob.

Abstract: A display controller coupled to a display device by way of a display interface and to a host device by way of a data port that includes a processor arranged to process executable instructions and associated data, a single memory device for storing the executable instructions and associated data and EDID corresponding to the display device, and a bridge portion coupling the single memory device to the host device by way of the data port, wherein the bridge portion is always in a powered on state thereby providing access to the single memory device by the host device even when the display controller is in a powered off state such as during a boot up process when the display controller is in the powered off state.

Abstract: Herein described are at least a method and a system to enhance the display of video by using response time feedback compensation. The system and method may be used in a display within a television set, for example. The method comprises processing first image data gray level values from a first frame memory and processing second image data gray level values from a second frame memory, wherein the second image data gray level values are obtained one frame period prior to the first image data gray level values. The method further comprises outputting alternate image data from a second look-up table, wherein the second look-up table uses third image data gray level values from a third frame memory and current input image data gray level values obtained from a current frame. An exemplary system comprises one or more circuits operable for, at least performing the aforementioned method.

Abstract: A computer-implemented method, apparatus, and article of manufacture provide the ability to store image data for use in a real-time compositing computer application. A storage tile size is determined based on disk input/output (I/O) hardware testing. A processing tile size is determined based on graphics I/O testing. An image is obtained and processing tiles (of the processing tile size) are mapped over the image. A center of the image is used as a point of origin for the processing tiles. The processing tiles are mapped to storage tiles. The storage tile point of origin is located at a lower left corner of the processing tiles. Each storage tile is configured to contain complete processing tiles that are stored in the storage tiles based on the storage tile size, processing tile size, and the mappings.

Abstract: Embodiments described herein provide a programmable mapping scheme for mapping information to resources of a system. In an embodiment, a programmable lattice method operates to map information to resources of a system. For example, the programmable lattice method can be used to map pixel data to graphics processing resources of a graphics processing system. In another embodiment, a programmable hybrid method operates to map information to resources of a system. For example, the programmable hybrid method can be used to map pixel data to graphics processing resources of a graphics processing system. The mapping methods described are applicable to any multi-dimensional array processing (e.g., 2D and 3D). The methods provide a uniform distribution of resources and tend to reduce resource collisions when allocating information to a resource.

Abstract: An apparatus and methods for scheduling and executing commands issued by a first processor, such as a CPU, on a second processor, such as a GPU, are disclosed. In one embodiment, a method of executing processes on a graphics processing unit (GPU) includes monitoring one or more buffers in a memory, selecting a first subset from the one or more buffers for execution on the GPU based on a workload profile of the GPU, and executing the first subset on the GPU. The GPU may also receive a priority ordering of the one or more buffers, where the selecting is further based on the received priority ordering. By performing prioritization and scheduling of commands in the GPU, system performance is enhanced.

Abstract: A method for histogram calculation using a graphics processing unit (GPU), comprises storing image data in a two-dimensional (2D) texture domain; subdividing the domain into independent regions or tiles; calculating in parallel, in a GPU, a plurality of tile histograms, one for each tile; and summing up in parallel, in the GPU, the tile histograms so as to derive a final image histogram.

Abstract: A system and method of pre-fetching data in a network includes displaying first data to a user, the first data being upstream of other data in a data flow. Before receiving a request from the user to view a second data, retrieving the second data and storing the retrieved second data in a memory device. After a request to display the second data is received from the user, using the stored second data for displaying to the user.

Abstract: An apparatus has a first attribute setting unit which sets first attribute information of image data, a second attribute setting unit which sets second attribute information of the image data, and an input-output controller which writes and reads out image data to and from an external storage medium. The first attribute information is stored in the image data, and the second attribute information is stored in an area in the external storage medium, which is used to manage the image data to be written in the external storage medium.

Abstract: A display panel drive circuit including a shift register including unit circuits connected in cascade, each of the unit circuits outputting a signal line selection signal, is so configured that: each of the unit circuits receives a clock signal nd either a signal line selection signal outputted from another-stage unit circuit or a start pulse signal, and the clock signal has a returned portion following an activation portion thereof, the returned portion including a first region that is sloped and a second region that is sloped more steeply than the first region. With the configuration, it is possible to realize a display panel drive circuit and a display panel driving method each of which (i) restrains an occurrence of a poor gate-on pulse signal, (ii) improves a pixel charging rate, and (iii) allows a clock signal to have higher frequency.

Abstract: A method, module and device for displaying graphical information on a screen are provided. In at least one embodiment, the method includes composing resulting image data from at least one application service, and transmitting the resulting image data to the screen. Further, in at least one embodiment, the composing of the resulting image data includes identifying items associated with each of the at least one application service, determining at least one item that is in a visible state, fetching information associated with the at least one item that is in a visible state, and calculating the resulting image data from the fetched information.

Abstract: Embodiments provide techniques for the analysis of graphics applications. For instance, an apparatus may include a graphics application program interface (API), a graphics engine, and a graphics analysis tool. The graphics analysis tool may receive multiple draw calls issued to the graphics API, and arrange the draw calls into multiple sequences, each sequence corresponding to a particular render target. From this information various analysis tasks may be performed. For instance, overdraw images may be generated. Such overdraw images may be enhanced to improve their dynamic range. Also, pixel histories may be generated based on corresponding pixel selections. The effect of draw calls on selected pixels may also be determined. Further, such tasks may be performed on a per render target basis.

Abstract: The present invention relates to an integrated, composite hybrid electric device in which various devices are formed as a single unit on one flexible substrate, and a fabrication method thereof. More particularly, the present invention a hybrid electric device in which a display device, a vibration-generating (or vibration-sensing) device, and a non-volatile memory device are formed on a single flexible piezoelectric polymer substrate into a single unit by using a flexible piezoelectric polymer substrate whose both surfaces are thinly deposited with a patterned transparent oxidation electrode, and a fabrication method thereof.

Abstract: A graphics system utilizes page table entries to provide information on the storage format used to store graphics data. The page table entries, in turn, may be used for address translation. Exemplary kinds of storage format information include compression mode, a packing mode for storing Z data in tiles or color data in tiles, and a mode for allocating tile data among partitions in a partitioned memory.

Abstract: A device includes a display screen a processor to render a display of a portion of a logical image on the screen. The logical image is larger than that which can be displayed on the display screen of the device. As the device is maneuvered through space, different portions of the logical image are displayed, and the user may interact with these portions as desired.

Abstract: A display timing setting unit determines the timing of rendering an image by raster scanning. A pixel reading unit reads a pixel according to timing information output from the display timing setting unit. An area of interest information input unit enters information for identifying an arbitrary area of interest within an image. An area of interest identifying unit determines whether the pixel is included in the area of interest based on the timing information output by the display timing setting unit. A finite-bit generation unit generates a finite bit series by subjecting information on the pixel to mapping transformation when the pixel is included in the area of interest.

Abstract: A graphics processor is provided. The graphics processor includes a memory storing image data for presentation and a display memory region in communication with the memory, the display memory region supplying image data to a display panel for presentation. The graphics processor includes bandwidth control logic configured to monitor a lag between an output from the display memory region and an input into the display memory region. The bandwidth control logic is further configured to prevent a level of the display memory from decrementing when the lag between the output and the input is capable of causing corruption on the display panel due to a lack of data from the display memory region. A method for avoiding a buffer under run and a device are included.

Abstract: A system for displaying a digital video sequence includes a graphics processing unit (GPU) and a display device. The GPU receives and modifies the digital video sequence to compensate for perceived blur based on motion between frames of the digital video sequence. The display device displays the modified digital video sequence. A method and computer readable medium having computer readable code is also provided.

Abstract: In an active matrix type display device including two source line side drivers for driving a plurality of pixel TFTs, one gate line side driver, two line memories respectively including at least first and second memories, and a controller for controlling the first and second line memories, storing and transmitting of picture data of the two line memories are switched to transmit the data to the two source line side drivers at the same time.

Abstract: A memory device includes a memory and a control circuit. The memory includes cells arranged in a matrix of rows and columns. The cells are grouped into banks, and each of the banks contains at least one column of the cells. The control circuit instructs a read operation in units of rows and a write operation in units of cells, and inhibits the read operation in units of the banks when the write operation is carried out to a specific one of the cells of a specific one of the banks.

Abstract: A memory for a graphics processor is provided. The memory includes a write first-in-first-out (FIFO) region of the memory for receiving pixel data, and a read FIFO region for accessing the pixel data received into the memory through the write FIFO. The memory has a memory controller having write assembly logic for rearranging the pixel data received by the write FIFO for storage in the memory. The write assembly logic is configured to write data representing a first pixel and a second pixel across a plurality of data segments in the memory, where corresponding bit locations for the data representing the first pixel and the data representing the second pixel are contiguous. A graphics controller having the memory and a method for preventing data corruption from being displayed during an underflow are included.

Abstract: A graphics device delivers a graphics address to a graphics memory switch that includes a graphics random access memory translator and a graphics memory page table. The graphics memory address is delivered to the graphics memory switch via a point-to-point, packet based interconnect. The graphics memory switch generates a physical system memory address and delivers the physical address to a root complex. The physical system memory address is delivered to the root complex via a point-to-point, packet based interconnect.

Abstract: The present disclosure discusses methods and apparatus for controlling the video playback in a video playback system. In particular, a method for controlling video playback includes receiving a flip call to display video data from a flip queue buffer. Processing of the video data is then initiated. Flip acknowledgement information is issued in response to receiving the flip call information and prior to completion of the processing of video data to be displayed from the flip queue buffer. By issuing flip acknowledgement information regardless of whether the processing of the video data has been completed, video flip calls can continue to be issued at a constant rate and other processing can continue without waiting, thus resulting in better and smoother video playback and economizing processing resources. Additionally, a decision whether or not to drop a particular video frame is made based on whether a flip queue buffer from a predetermined number of flip queue buffers is available.

Abstract: An exemplary method for performing a bit block transfer (bitblt) includes receiving one or more graphics parameters specifying the bitblt and generating a specialized bitblt function to perform the bitblt. The specialized bitblt function includes a one or more code blocks selected from a superset of code blocks based on the graphics parameters. A system includes a specialized bit block transfer (bitblt) function generator generating a specialized bitblt function to perform a specified bitblt. The specialized bitblt function includes intermediate language code corresponding to one or more graphics parameters specifying the bitblt. A translator translates the specialized bitblt function into machine-specific language code.

Abstract: In one embodiment there is provided, a display driver system, comprising, at least one display driver; a magnetic random access memory (MRAM) macro; and a display driver interface coupling the MRAM macro and the at least one display driver.

Abstract: A plurality of memory circuits and a logic circuit. The plurality of memory circuits may be configured to store a plurality of pixels. The pixels may be used in a motion estimation stage of a video encoder. The logic circuit may be configured to (i) control which of the pixels are stored in which of the plurality of memory banks and (ii) control accessing of the plurality of pixels.

Abstract: A system and method are provided for drawing graphics, such as to display a user interface on a display of a mobile device. A graphics stack is used to store pre-computed coordinate values to improve performance for drawing graphics, such as to display a user interface on a display of a mobile device.

Abstract: In a video application, a method and system provide different sizes of data-fetch where the data transfer rate between a decoder and an external memory (e.g., DDR memory) is extremely high, as for example in HDTV systems. The invention in one form divides a reference frame into different tiles where each tile is hierarchically divided into smaller tiles to a level where the minimum tile size is the same as the fixed burst size of the DDR memory. The method also provides for arranging the biggest tiles into different banks and pages so that even if the block to be fetched falls across tile boundaries, the latency penalty in the tile transition will be minimized. The invention provides advantages also for progressive and interlaced data fetch.

Abstract: A system for processing video data includes a host processor, a first media processing device coupled to a first buffer, the first media processing device configured to perform a first processing task on a frame of video data, and a second media processing device coupled to a second buffer, the second media processing device configured to perform a second processing task on the processed frame of video data. The architecture allows the two devices to have asymmetric video processing capabilities. Thus, the first device may advantageously perform a first task, such as decoding, while the second device performs a second task, such as post processing, according to the respective capabilities of each device, thereby increasing processing efficiency relative to prior art systems. Further, one driver may be used for both devices, enabling applications to take advantage of the system's accelerated processing capabilities without requiring code changes.

Abstract: Methods and apparatuses to create and manage volatile graphics objects in a video memory are disclosed. An object is created and marked as volatile. The volatile object is stored in a video memory of a graphics subsystem. A volatile marking indicates that data for an object is not to be paged out from the video memory to make room for other data. The video memory space occupied by the volatile object is indicated as a volatile storage, in a data structure. Another object is written into at least a portion of the video memory space, which is occupied by the volatile object, without paging out data for the volatile object. In one embodiment, at least a portion of the volatile object is referenced or used while another object is formed. The volatile object may be discarded after being referenced or used to form another object.

Abstract: An image display adjustment system comprises a display setup application executable by a processor and configured to, in response to detecting at least one characteristic associated with a display device, automatically cause an adjustment image to be displayed on the display device and an image adjustment process to be performed for the display device using the adjustment image.

Abstract: Task and data management systems methods and apparatus are disclosed. A processor event that requires more memory space than is available in a local storage of a co-processor is divided into two or more segments. Each segment has a segment size that is less than or the same as an amount of memory space available in the local storage. The segments are processed with one or more co-processors to produce two or more corresponding outputs.

Abstract: A system, method and computer program product are provided for branching during graphics processing. Initially, a first operation is performed on data. In response to the first operation, a branching operation is performed to a second operation. The first operation and the second operation are associated with instructions selected from a predetermined instruction set.

Abstract: A display method of an OSD and a display system are provided herein. In the display method, a plurality of symbols are respectively compressed into a plurality of codewords according to an encoding process, and the codewords are stored in a memory module. A plurality of index values respectively corresponding to the symbols are established in a codebook and the codebook is stored in the memory module, wherein the index values are address information of storing the codewords in the memory module. The index value corresponding to a designation symbol of the symbols is searched out from the codebook according to an input command corresponding to the designation symbol, and a decoding process is performed on the codeword corresponding to the designation symbol from the memory module for displaying the designation symbol on the display. Therefore, a storage space of the memory module is reduced by compressing the symbols.

Abstract: A liquid crystal display and a driving method thereof are provided. The liquid crystal display includes a liquid crystal display panel, a register for storing pixel information of a problem pattern and polarity pattern information, a block pattern recognition unit for comparing input data with the problem pattern to count the number of problem patterns contained in the input data and comparing the count value with a first threshold value, a line pattern recognition unit for determining the line containing the problem pattern as a problem line, a frame pattern recognition unit for comparing the number of problem lines with a second threshold value, and determining the frame containing the input data as a problem frame, a polarity control signal generating unit for generating vertical and horizontal polarity control signals, and source drive integrated circuits (ICs) for controlling the vertical and horizontal polarities of data voltages supplied to the data lines.

Abstract: A display apparatus include a connector, a readable/writable EDID storage to store EDID, and a controller to control the EDID storage to be write-protected from error data transmitted from a computer through the connector. With this configuration, the display apparatus and a method of controlling the same can prevent error data from being stored in an EDID storage.

Abstract: To display a row of characters in the VGA alphanumeric mode, the ASCII and attribute bits for all such characters are retrieved from the main memory and stored in a local cache memory. The font and unused bits that are also retrieved from the memory during the retrieval of ASCII and attribute bits are discarded. The stored ASCII and attribute bits for each such character is then used to compute the address of the associated font bits in the main memory. Next, for each character, the font bits are retrieved from the main memory using a burst read operation and using the computed address for that font. The font bits associated with all the characters in the row are stored in the local cache memory and are subsequently scanned out to be used in the display of the characters.

Abstract: A method for dividing a display into zones at system initialization for tracking which zones have any pixels revised so that, when the time comes to update the display, only the zones requiring revision (that is, those zones in which any pixel has been revised) are copied from shadow memory to the frame buffer for display on the display device. The memory for tracking these zones can be allocated at initialization and held since it is relatively small. Consequently, a significant performance gain may be achieved by avoiding the shortcomings of the existing methods in the art notwithstanding the fact that some “clean” pixels in each zone having even a single changed pixel are also rewritten to the frame buffer.

Abstract: A display module for displaying information on a screen, using a display data structure, wherein the display data structure is a doubly linked list. A display space in defined in video memory and the display space is filled by sequentially copying at least a portion of a set of characters from the display data structure into the video memory.

Abstract: In one embodiment of the present invention, a system for displaying images in at least one display window on a display unit includes a display processor configured to generate graphics commands from a received input. A graphics processing unit is coupled to the display processor and includes rendering engine configured to generate graphic data from the graphics commands, an internal memory coupled to the rendering engine, and a general purpose I/O coupled to the rendering engine and configured to transmit messages from the graphics processing unit. A graphics logic device is coupled to the graphics processing unit. The graphics logic device is configured to initiate a transfer of graphic data for an update of a display window from the internal memory to the display unit upon receipt of a message indicative of an available update to the display window.

Abstract: Provided is a method and apparatus for detecting multi moving objects in high resolution image sequences and performs moving objects on a screen using a general image collecting apparatus. The present invention provides a method of effectively removing the background of moving objects like motion of a leaf or reflection of a wave in an outdoor environment using a statistical method and uses a GPU installed in a general computer to process high resolution image sequences at high speed.

Abstract: Techniques for improved command level remoting are disclosed.

Abstract: A method for managing image processing data buffers for processes having overlap input data between iterations includes loading a data buffer with an initial input data array and performing an image data array operation on the input data array. The method repeats the following steps for plural iterations including loading the data buffer with new input data forming a new input data array for a next iteration and performing the input data array operation on the new input data array. The overlap data consists of pixels at an end of each scan line. Loading new input data includes loading pixels following the overlap data for each scan line.