Abstract: An apparatus of an aspect includes a plurality of cores and shared core extension logic coupled with each of the plurality of cores. The shared core extension logic has shared data processing logic that is shared by each of the plurality of cores. Instruction execution logic, for each of the cores, in response to a shared core extension call instruction, is to call the shared core extension logic. The call is to have data processing performed by the shared data processing logic on behalf of a corresponding core. Other apparatus, methods, and systems are also disclosed.

Abstract: Embodiments described herein provide for extending media playback. In an example implementation, during playback of one or more first media items populated in a queue, a control system extends playback time of the queue. Extending playback time of the queue may involve determining when the one or more first media items will be finished playing; and before the first media items are finished playing, determining one or more second media items that correspond in substantial likeness to the one or more first media items and sending an instruction that causes the first playback device to insert the determined one or more second media items into the queue such that play time of the queue is extended.

Abstract: Embodiments of the present disclosure measure a state of a storage group within a storage array. The embodiments also increase or decrease a compression ratio corresponding to input/output (I/O) operations on the storage group based on a target data reduction ratio (DRR) of the storage array, an expected performance envelope, and a compressibility factor of the storage group.

Abstract: A system is provided to receive a request to write data to a storage device, wherein the data is associated with a file name and a file path. The system performs a hash function on an input based on the file name and the file path to obtain a hash value, wherein the hash function comprises a plurality of hash methods performed on the input. The system maps the hash value to a physical location in the storage device, and writes the data to the physical location in the storage device.

Abstract: A controller includes: a command queue scheduler for queuing normal commands, and providing a priority order to a suspend command, when the suspend command is input; a data input/output component for outputting data in response to a data output signal output the command queue scheduler, and stopping the output of the data in response to a data output stop signal; and a data monitor for dividing data input to the data input/output component into a plurality of data groups, and monitoring information of a data group including data currently output from the data input/output component. The data input/output component outputs data up to the currently output data included in the data group and then stops the output of the data, in response to the data output stop signal. The command queue scheduler outputs the suspend command, when the output of the data group is stopped.

Abstract: One example method includes receiving a set of filesystem parameters, creating a simulated filesystem based on the filesystem parameters, receiving a set of target characteristics for a file collection, based on the target characteristics, slicing a datastream into a grouping of data slices, populating the simulated files with the data slices to create the file collection and forward or reverse morphing the file collection from one generation to another without rewriting the entire file collection.

Abstract: A method and a device for determining a strategy for data placement within an SSD are provided. The method for determining a strategy for data placement within a Solid State Drive SSD, includes acquiring an optimization target and workload metric data that is pre-collected for a time period; selecting a machine learning model and a training data strategy according to the optimization target; selecting feature data from the workload metric data for the time period according to the selected training data strategy, and training the selected machine learning model based on the selected feature data; determining, in each subsequent predicting time, a strategy for data placement for a predicting time period corresponding to the predicting time according to the workload metric data for the time period and the workload metric data that is collected in the predicting time by using the trained machine learning model.

Abstract: Transaction activity of a cache maintaining content may be monitored to determine periods of transaction activity below a first threshold amount of transactions. A period of anticipated transaction activity above a second threshold amount of transactions may be determined. A period of anticipated transaction activity below the first threshold may be selected based upon the monitored periods of transaction activity below the first threshold and the determined period of anticipated transaction activity above the second threshold. Content then may be evicted from the cache during the selected period of anticipated transaction activity.

Abstract: In an embodiment a method includes providing a table including a plurality of data records (R1 . . . Rn) corresponding to a plurality of profile data, providing a master profile including fields to be personalized (F1 . . . Fk . . . Fp) corresponding to one or more of the data records (R1 . . . Rn) to store the different types of personalization values (V1 . . . Vm), combining the one or more of the data records (R1 . . . Rn) in the table with the master profile by inserting the personalization values (V1 . . . Vm) in the fields to be personalized (F1 . . . Fk . . . Fp) to obtain respective personalized profile packages, coding the one or more of the data records (R1 . . . Rn) to obtain encoded data records (CRi), applying the coding to the offset table to obtain encoded data offset (COi) and combining for each record (Ri) the encoded data record (CRi) and the data offset (OCi) in an encoded personalization record (URi).

Abstract: A nonvolatile memory device includes a first pin that receives a first signal, a second pin that receives a second signal, third pins that receive third signals, a fourth pin that receives a write enable signal, a memory cell array, and a memory interface circuit that obtains a command, an address, and data from the third signals in a first mode and obtains the command and the address from the first signal and the second signal and the data from the third signals in a second mode. In the first mode, the memory interface circuit obtains the command from the third signals and obtains the address from the third signals. In the second mode, the memory interface circuit obtains the command from the first signal and the second signal and obtains the address from the first signal and the second signal.

Abstract: Systems and methods for network security are provided. Various embodiments of the present technology provide systems and methods for an identity security gateway agent that provides for privileged access. Embodiments include a system and method that uses a single sign-on (SSO) (or similar) mechanism to facilitate a user accessing web-based service providers, but separates the assertion and entire SSO process from the user credential.

Abstract: A memory device includes a memory array comprising a plurality of planes, a primary plane driver circuit comprising components to support read operations, program operations, and erase operations on any of the plurality of planes, and a secondary plane driver circuit comprising components to support read operations on an associated one of the plurality of planes. The primary plane driver circuit is configured to perform a first read operation on a first plane of the plurality of planes and the secondary plane driver circuit is configured to perform a second read operation on a second plane of the plurality of planes concurrently with the first read operation.

Abstract: A unified cache subsystem includes a data memory configured as both a shared memory and a local cache memory. The unified cache subsystem processes different types of memory transactions using different data pathways. To process memory transactions that target shared memory, the unified cache subsystem includes a direct pathway to the data memory. To process memory transactions that do not target shared memory, the unified cache subsystem includes a tag processing pipeline configured to identify cache hits and cache misses. When the tag processing pipeline identifies a cache hit for a given memory transaction, the transaction is rerouted to the direct pathway to data memory. When the tag processing pipeline identifies a cache miss for a given memory transaction, the transaction is pushed into a first-in first-out (FIFO) until miss data is returned from external memory. The tag processing pipeline is also configured to process texture-oriented memory transactions.

Abstract: Files can be managed to mitigate undesirable reading of files from secondary storage component (SSC) associated with a storage system comprising primary storage component (PSC). File management component (FMC) can determine file identifiers for files stored in SSC and store them in reference files associated with such files. FMC can determine file identifiers for files stored in PSC and store them in a file entry data store. In response to a client request, FMC can determine whether a local file stored in PSC is a copy of an archived file stored in SSC based on whether the respective file identifiers of the archived file and local file or snapshot of the local file match. If there is a suitable match, FMC can read the snapshot of the local file and provide it to client device; if not, FMC can read the archived file and provide it to client device.

Abstract: A cache management circuit that includes a predictive adjustment circuit configured to predictively generate cache control information based on a cache hit-miss indicator and the retention ranks of accessed cache lines to improve cache efficiency is disclosed. The predictive adjustment circuit stores the cache control information persistently, independent of whether the data remains in cache memory. The stored cache control information is indicative of prior cache access activity for data from a memory address, which is indicative of the data's “usefulness.” Based on the cache control information, the predictive adjustment circuit controls generation of retention ranks for data in the cache lines when the data is inserted, accessed, and evicted.

Abstract: Embodiments are disclosed for a method for dynamic access paths. The method includes generating real-time statistics (RTS) estimates based on a log of a database. Further, the method includes generating access paths based on a structured query language command and the RTS estimates. The method also includes training a machine learning model to map the RTS estimates to the access paths.

Abstract: A non-transitory computer-readable medium for sharing protected content, comprising instruction stored thereon. When executed on a processor, the instruction performs steps of deriving a shared secret, processing the shared secret using a secure hash algorithm 256 cryptographic hash to produce a primary encryption key, and encrypting a secondary encryption key using the primary encryption key. When the shared secret is derived between a private key and a public key of a first user, encrypting the protected content using the secondary encryption key, and transmitting the encrypted protected content to a server to be accessed by the second user. When the shared secret is derived between the private key of the first user and a public key of a second user, transmitting the secondary encryption key to the second user. The second user uses the secondary encryption key to decrypt the encrypted protected content on the server.

Abstract: A memory system, a memory controller and an operating method are disclosed. By dividing a read count table including read count values respectively for a plurality of memory blocks into one or more read count table segments each including one or more read count values of a resolution, and managing one or more flags respectively corresponding to the read count table segments, and set the flag corresponding to the read count table segment in which at least one read count value is changed among the read count table segments, it is possible to minimize additional operational costs required to recover the read count table upon occurrence of an SPO.

Abstract: Prior to an update of an operating system of a computing device, a configuration operation is performed with respect to a particular processor of the computing device, such that the particular processor is indicated to the operating system as being in an offline state while an application runs at the particular processor. The operating system is then updated. The update comprises a time interval in which the operating system is unavailable and the application performs one or more computations at the particular processor. After the update, the application is restarted.

Abstract: An integrated circuit (IC) card of an embodiment includes a communicator, a storage storing biometric authentication information, an acquirer, and a processor. The communicator communicates with a terminal device. The acquirer acquires biometric information of a user. The processor collates the biometric information of the user acquired by the acquirer with the biometric authentication information stored in the storage and stores a collation result into the storage at an activation time.

Abstract: A method of increasing operational life time of SSD RAID and a storage equipment using same, the method including: configuring a data storage device to have a plurality of storage areas, each storage area including a plurality of stripes, and each stripe including an individual block of a plurality of solid state disks, where at least one block in each stripe is a check bit block, the other blocks are data blocks; and configuring two neighboring stripes in each storage area to form a composite stripe according to a plurality of index combinations in a mapping table, where the composite stripe includes two neighboring blocks in each solid state disk, and the composite stripe is divided into a stripe writing area and an empty stripe area, so that each solid state disk in each storage area has a reserved space.

Abstract: An approach is provided for reducing command bus traffic between memory controllers and PIM-enabled memory modules using special PIM commands. The term “special PIM command” is used herein to describe embodiments and refers to a PIM command for which the corresponding module-specific command information is provided to memory modules via a non-command bus data path. A memory controller generates and issues a special PIM command to multiple PIM-enabled memory modules via a command bus and provides module-specific command information (e.g., address information) for the special PIM command to the PIM-enabled memory modules via the non-command bus data path that is shared by the PIM-enabled memory modules and the memory controller.

Abstract: Embodiments of the disclosure provide systems and methods for allocating memory space in a memory device. The system can include: a memory device for providing the memory space; and a compiler component configured for: receiving a request for allocating a data array having a plurality of data elements in the memory device, wherein each of the plurality of data elements has a logical address; generating an instruction for allocating memory space for the data array in the memory device based on the request; generating device addresses for the plurality of data elements in the memory device based on logical addresses of the plurality of data elements; and allocating the memory space for the data array in the memory device based on the device addresses and the instruction.

Abstract: Disclosed are a non-volatile memory device and a method of operating the non-volatile memory device. A non-volatile memory device in which m logical pages are stored in a single physical page includes: a plurality of registers configured to be included in a flash translation layer (FTL) and to store at least part of the data of a write command received from a file system; and a controller configured to control operations of the plurality of registers based on the write command; wherein each of the plurality of registers is further configured to have a storage space associated with the size of the m logical pages; and wherein the controller is further configured to program the data of the write command into the non-volatile memory device and to store the data of the write command in the plurality of registers.

Abstract: A method includes loading each section of an executable program code into a respective page of memory, configuring permissions for a first page including a first section of the executable program code to enable execution of the first section loaded into the first page. The first section associated with a first label. The method also includes configuring permissions for a second page of the memory including a second section of the executable program code to disable execution of the second section loaded into the second page. The second section associated with a second label. Responsive to a determination that a transition from the first section to the second section is allowed during execution of the executable program code, the method also includes changing the permissions of the second page to enable execution of the second section of the executable program code.

Abstract: A system, method, and machine-readable storage medium for analyzing a state of a data object are provided. In some embodiments, the method includes receiving, at a storage device, a metadata request for the data object from a client. The data object is composed of a plurality of segments. The method also includes selecting a subset of the plurality of segments and obtaining a segment state for each segment of the subset. Each segment state indicates whether the respective segment is accessible via a backing store. The method further includes determining a most restrictive state of the one or more segment states and sending state information to the client in response to the metadata request, the state information being derived from the most restrictive state.

Abstract: A virtual storage volume that includes storage space on potentially many different physical disks may be mounted at a compute node. In order to replicate the virtual storage volume to a target compute node, a sequence of snapshots may be created that capture the state of the virtual storage volume at a sequence of points in time. The data associated with these snapshots may be transferred to the target compute node. When the difference between the snapshots is sufficiently small, the target virtual storage volume may be resynchronized.

Abstract: A module with a functional unit for generating a data stream with a data output for outputting the data stream to a serialization unit provided for receiving a data stream from a serialization unit of a first series. A serialization unit of a second series is set up to serialize the data stream and output it through the data output, and a configuration data input receives configuration data defining a first register configuration of a serialization unit. A mapping of register addresses of the serialization unit of the first series to register addresses of the serialization unit of the second series can be stored in a data memory of the module. The configuration unit is set up to read in the configuration data, to use the mapping, and to configure the registers of the serialization unit of the second series according to the configuration of the second register.

Abstract: A method for data migration is provided. The method includes the following. A communication connection with a source migration terminal is established. A file list on the source migration terminal is acquired after the source migration terminal is accessed. First operations and second operations are executed in parallel. The first operations include reading out files on the source migration terminal according to the file list and storing the files read out on a migration terminal. The second operations include displaying the file list, receiving selection of a non-migrated file in the file list, and deleting the non-migrated file after the non-migrated file is migrated from the source migration terminal to the migration terminal and stored in the migration terminal. A terminal is further provided.

Abstract: Data can be captured from a live web application to populate a demo application. In an example, automated input is provided to user interface touch points of a live application, and corresponding responses are captured. These responses are reformatted into a convention of the demo application, and used to populate demo response files. Then, when a demo application operates, it retrieves, processes, and displays information in these demo response files.

Abstract: A method and a system for data migration on a multi-tiered storage system are provided. The method can include receiving a migration task indicating a dataset to migrate. The method can further include building a plurality of buffers onto at least one high-performance storage tier. The high-performance storage tier can be based on the read speed of that tier. The method can also include referencing a shadow mapping to locate physical data from the dataset stored on a first buffer. The method can include migrating the physical data from the first buffer to a migration destination. The method can further include deallocating the first buffer. The deallocation can allow allocation of additional physical data onto the first buffer for migration.

Abstract: In an embodiment, a processor includes a buffer in an interface unit. The buffer may be used to accumulate coprocessor instructions to be transmitted to a coprocessor. In an embodiment, the processor issues the coprocessor instructions to the buffer when ready to be issued to the coprocessor. The interface unit may accumulate the coprocessor instructions in the buffer, generating a bundle of instructions. The bundle may be closed based on various predetermined conditions and then the bundle may be transmitted to the coprocessor. If a sequence of coprocessor instructions appears consecutively in a program, the rate at which the instructions are provided to the coprocessor (on average) at least matches the rate at which the coprocessor consumes the instructions, in an embodiment.

Abstract: A memory array controller includes memory media scanning logic to sample a bit error rate of memory blocks of a first memory device. A data management logic may then move data from the first memory device to a second memory device if the bit error rate matches a threshold level. The threshold level is derived from a configurable data retention time parameter for the first memory device. The configurable data retention time parameter may be received from a user or determined utilizing various known machine learning techniques.

Abstract: A data storage system implements aggregation, bifurcation, and/or reduction techniques to improve the efficiency of processing data storage requests. Data storage requests and/or their associated payloads may be aggregated based on one or more parameters. Data to be the stored and the associated commands may be separated so as to optimize a system's throughput and latency for each. Furthermore, extraneous commands and requests may be reduced or eliminated based on heuristics associated with the requests and the data.

Abstract: A method of processing transactions associated with a command in a storage system is provided. The method includes receiving, at a first authority of the storage system, a command relating to user data. The method includes sending a transaction of the command, from the first authority to a second authority of the storage system, wherein a token accompanies the transaction and writing data in accordance with the transaction as permitted by the token into a partition that is allocated to the second authority in a storage device of the storage system.

Abstract: A firmware-based system and method for detecting an indicator of an override condition during a Unified Extensible Firmware Interface (UEFI) Secure Boot sequence. The indicator of the override condition may be detected based upon the pressing of a specialized button, designated key or keys or other received input that indicates both physical presence of the user and the desire, on the current boot, to bypass UEFI Secure Boot. An embodiment may work for only a single boot, not require access into a setup application, and may be accessed by externally accessible features of the computer system.

Abstract: A method is provided in one example embodiment and may include determining at a parent content node that a plurality of recipient content nodes are to receive a same content; generating, based on a determination that the same content is available at the parent content node, a multi-delivery header comprising a plurality of identifiers, wherein each identifier of the plurality of identifiers indicates each recipient content node that is to receive the same content; appending the multi-delivery header to one or more packets of an Internet Protocol (IP) flow associated with the same content; and transmitting packets for the IP flow to each of the plurality of the recipient content nodes.

Abstract: A memory system may include: a nonvolatile memory device; a volatile memory suitable for storing write data; and a controller suitable for: allocating a normal write buffer in the volatile memory when normal write data are inputted, allocating a first write buffer in the volatile memory when first write data, which are grouped into a first transaction and first total size information on a total size of the first transaction, are inputted, allocating a second write buffer in the volatile memory when second write data, which are grouped into a second transaction and second total size information on a total size of the second transaction, are inputted, managing sizes of the first and second write buffers to change them in response to the first and second total size information, respectively, and managing a size of the normal write buffer to fix it to a set size.

Abstract: Memory access circuitry (26) enforces ownership rights for memory regions. A given memory region is associated with an owner realm specified from multiple realms, each realm corresponding to a portion of at least one software process executed by processing circuitry (8). The owner realm has a right to exclude other realms from accessing data within the memory region. Realm management circuitry (20) accesses a realm management tree storing realm management data for at least two realms in a tree structure having a variable number of levels. The realms are identified using a realm identifier which has a variable number of variable length bit portions each providing an index into a given level of the realm management tree.

Abstract: Proposed are concepts for predicting workload of an application. Resource usage of a first application is monitored to obtain resource usage data associated with the first application. A workload signature for the first application is generated based on the obtained resource usage data, wherein the workload signature comprises information relating to static and time variant resource usage of the first application. Resource usage of a second application is predicted based on the workload signature of the first application.

Abstract: Systems and methods that may be implemented in a Unified Extensible Firmware Interface (UEFI) pre-boot environment time to dynamically locate and load bootable images stored in one or more operating system (OS) partitions on a system storage device/s (e.g., HDD, SSD) that is formatted with an advanced filesystem (e.g., such as NTFS, EXT3, etc.). An OS-based filesystem-independent method may be provided to access OS filesystem data during UEFI pre-boot time. Individual selected boot images stored across multiple OS filesystem partitions may be located and loaded to boot from UEFI pre-boot.

Abstract: An apparatus is provided that includes a set of registers, and an interface of a computing block. The computing block includes one of a physical layer block or a media access control layer block. The interface includes one or more pins to transmit asynchronous signals, one or more pins to receive asynchronous signals, and a set of pins to communicate particular signals to access the set of registers, where a set of control and status signals of a defined interface are mapped to respective bits of the set of registers.

Abstract: A dataset's uniqueness level may be calculated by analyzing a dataset to determine a uniqueness level. In cases where the uniqueness level may be too low for a particular purpose, meaning when the dataset may not provide enough anonymity, the dataset may be adjusted by recomputing the dataset with different resolutions of spatial data, temporal data, content data, and relationship data. By adjusting the resolution or accuracy of the data elements, the uniqueness level may thereby be adjusted. An error calculation may be determined by comparing the adjusted dataset to the original data, and the error value may represent the consistency of the data to the original data. The uniqueness level may be used as an assurance level of anonymity, which may be advertised when a dataset is sold or transferred to a third party for analysis.

Abstract: An illustrative embodiment disclosed herein is an apparatus including a processor having programmed instructions that identify a bucket identifier corresponding to a bucket. The bucket identifier includes a prefix. The processor has programmed instructions that determine that the prefix matches a predetermined prefix, assign an expiry duration to the bucket, and, after the expiry duration, delete the bucket identifier.

Abstract: In one embodiment, a task control block (TCB) for allocating cache storage such as cache segments in a multi-track cache write operation may be enqueued in a wait queue for a relatively long wait period, the first time the task control block is used, and may be re-enqueued on the wait queue for a relatively short wait period, each time the task control block is used for allocating cache segments for subsequent cache writes of the remaining tracks of the multi-track cache write operation. As a result, time-out suspensions caused by throttling of host input-output operations to facilitate cache draining, may be reduced or eliminated. It is appreciated that wait classification of task control blocks in accordance with the present description may be applied to applications other than draining a cache. Other features and aspects may be realized, depending upon the particular application.

Abstract: A system and method is provided for implementing platform security on a consumer electronic device having an open development platform. The device is of the type which includes an abstraction layer operable between device hardware and application software. A secured software agent is provided for embedding within the abstraction layer forming the operating system. The secured software agent is configured to limit access to the abstraction layer by either blocking loadable kernel modules from loading, blocking writing to the system call table or blocking requests to attach debug utilities to certified applications or kernel components.

Abstract: The present teaching relates to concurrent database operation. In one example, a plurality of requests which includes a scan request to obtain first data associated with a plurality of first keys stored in a database is received concurrently. A global version number is updated upon receipt of the scan request. The first data associated with the plurality of first keys is obtained based on the updated global version number. The first data is provided in response to the scan request.

Abstract: Implementations of the present disclosure include associating a first transaction executed within a database system with a first transaction control block (TCB) index, setting a status of the first transaction to active and a lock status of the first transaction to holding in response to a first set of locks being established for the first transaction, the first set of locks including one or more locks that each inhibit access to a respective resource within the database system, providing a lock table that records, for a set of locks within the database system, a set of lock owners including one or more transactions identified based on respective TCB indexes and a wait queue, and determining that the first transaction has completed, and in response setting the status of the first transaction to indicate completion of the transaction and the lock status of the first transaction to released.

Abstract: An identity system for the Internet of Things (IOT) that enables users and machines to identify, authenticate and interact with products and collectibles without relying on a third-party-controlled authentication service. The system includes wireless tamperproof tags coupled to products and an open registry database where a chain of ownership of the items is able to be stored. The open registry enables public access to the item identity and data combined with item registration anonymity.

Abstract: The present disclosure relates to systems, non-transitory computer-readable media, and methods for dynamically controlling ephemeral messaging threads and ephemeral message duration settings across computing devices while improving security by maintaining end-to-end encryption. In particular, in one or more embodiments, the disclosed systems can transmit encrypted ephemeral messages, including ephemeral message duration settings and ephemeral setting timestamps. The disclosed systems can decrypt received messages on receiving client devices and dynamically apply ephemeral message duration settings to different message threads. For example, the disclosed systems can modify existing duration settings at a receiving client device to match a received ephemeral message duration setting based on determining that the received ephemeral setting timestamp predates an existing setting timestamp.