Abstract: Described herein are a method and device for transferring data in a computer system. The device includes a host processor, a plurality of first memory architectures, a switch, a redundant array of independent drives (RAID) assist unit; and a second memory architecture. The host processor is configured to send a data transfer command to the RAID assist unit via the switch. The RAID assist unit is configured to create a set of parallel memory transactions between the plurality of first memory architectures and the second memory architecture, execute the set of parallel memory transactions via the local switch and absent interaction with the host processor; and notify the host processor upon completion of data transfer. In an implementation, the plurality of first memory architectures is non-volatile memories (NVMs) and the second memory architecture is local memory.

Abstract: Disclosed is a management system for managing a memory device having sub-chips each having a container area and a data area. A CPU selects a target sub-chip according to respective temperature of the sub-chips. When the CPU intends to access a first original data in one of the data areas, a hot date tracking device acquires a first original address of the first original data from the CPU. When the first original address is recorded in one of a plurality of tracking layers, the CPU is indicated to access a first copied data corresponding to the first original data in the container area of the target sub-chip according to a current tracking layer recording the first original address. When the first original address is not recorded in the tracking layers, the CPU accesses the first original data in the data area according to the first original address.

Abstract: The nonvolatile memory module includes at least one nonvolatile memory, and a device controller including a RAM to store data exchanged between a host and the at least one nonvolatile memory and a DIMM controller to control data exchange between the RAM and the at least one nonvolatile memory. An allocation for an access area at an access to the RAM is performed during a write transaction in which data is recorded at the RAM and is released during a read transaction of the recorded data.

Abstract: Mechanisms are provided, in a processor, for executing instructions that are younger than a previously dispatched synchronization (sync) instruction is provided. An instruction sequencer unit of the processor dispatches a sync instruction. The sync instruction is sent to a nest of one or more devices outside of the processor. The instruction sequencer unit dispatches a subsequent instruction after dispatching the sync instruction. The dispatching of the subsequent instruction after dispatching the sync instruction is performed prior to receiving a sync acknowledgement response from the nest. The instruction sequencer unit performs a completion of the subsequent instruction based on whether completion of the subsequent instruction is dependent upon receiving the sync acknowledgement from the nest and completion of the sync instruction.

Abstract: Systems, apparatus, and computer-implemented methods are provided for the hybridization of cache memory utilizing both magnetic and solid-state memory media. A solid-state cache controller apparatus can be coupled to a host computing system to maximize efficiency of the system in a manner that is transparent to the high-level applications using the system. The apparatus includes an associative memory component and a solid-state cache control component. Solid-state memory is configured to store data blocks of host read operations. If a host-read operation is requested, the controller communicates with a solid-state cache memory controller to determine whether a tag array data structure indicates a cached copy of the requested data block is available in solid-state memory.

Abstract: A file storage method and device are provided. The method includes: receiving a storage request for a to-be-stored file (S101); determining a target key for storing the to-be-stored file (S102); obtaining to-be-stored metadata of the to-be-stored file according to the determined target key (S103), wherein the to-be-stored metadata includes: fixed sub-metadata and variable sub-metadata; and storing the to-be-stored metadata in a metadata database, storing the fixed sub-metadata in a name of the determined target key, storing the variable sub-metadata in a preset storage area corresponding to the determined target key, and storing the to-be-stored file in a value of the determined target key (S104). By applying the file storage and device, the recovery of metadata is effectively ensured, while a storage space of a storage terminal is saved.

Abstract: An embodiment of a semiconductor package apparatus may include technology to attempt to program data in a first portion of a nonvolatile memory, determine if the attempt was successful, and recover the data to a second portion of the nonvolatile memory with an internal data move operation if the attempt is determined to be not successful. Other embodiments are disclosed and claimed.

Abstract: Namespace planning of non-volatile memory that takes advantage of multi-channel accessing and considers multi-channel properties is provided. A data storage device includes a non-volatile memory and a controller. The controller accesses the non-volatile memory through multiple channels. When performing namespace planning on the non-volatile memory, the controller makes each assigned channel correspond to just one namespace.

Abstract: A mainframe computing system includes a central processor complex, and a plurality of billing entities, each billing entity having a respective capacity limit, and a workload manager that schedules work requested by the plurality of billing entities on the central processor complex and tracks, by billing entity, a rolling average of service units. The mainframe computing system also includes a dynamic capping policy for the central processor complex that identifies a maximum service unit limit, a subset of the plurality of billing entities, and, for each identified billing entity, information from which to determine a service unit entitlement value. The mainframe computing system also includes a dynamic capping master that adjusts the respective capacity limits of the subset of the plurality of billing entities at scheduled intervals based on the dynamic capping policy to favor billing entities having high-importance workload within the maximum service unit limit.

Abstract: Technologies are disclosed herein for blocking access to some firmware variables during runtime. These firmware variables may be disallowed from runtime access (e.g., read/write access), by placing an indication of the firmware variables on a runtime blocklist. Upon completion of booting, runtime firmware services may access the runtime blocklist to determine if a firmware variable is to be accessed during runtime. In some cases, a firmware variable may be disallowed from runtime access by inclusion in the runtime blocklist, even if that firmware variable has an attribute that indicates that it is runtime accessible. The runtime blocklist may be generated based at least in part on indications of the firmware variables to be blocked during runtime. Additionally, runtime accessible firmware variables may be exposed to higher-level software, such as an O/S, if the firmware variables are not included in the runtime blocklist.

Abstract: A semiconductor device includes a command synthesis circuit synchronized with a first division clock signal to shift a command based on an offset signal and synchronized with a second division clock signal to generate a command synthesis signal from the shifted command. The semiconductor device also includes a strobe control signal synthesis circuit synchronized with the second division clock signal to generate a strobe synthesis signal from a strobe control signal. The semiconductor device further includes a drive control circuit generating a drive control signal from any one of the command synthesis signal and a drive signal based on the strobe synthesis signal.

Abstract: In a data processing network comprising a Request, Home and Slave Nodes coupled via a coherent interconnect, a Home Node performs a read transaction in response to a read request from a Request Node. In a first embodiment, the transaction is terminated in the Home Node upon receipt of a read receipt from a Slave Node, acknowledging a read request from the Home Node. In a second embodiment, the Home Node sends a message to the Request Node indicating that a read transaction has been ordered in the Home Node and further indicating that data for the read transaction is provided in a separate data response. The transaction is terminated in the Home Node upon receipt of an acknowledge from the Request Node of this message. In this manner, the transaction is terminated in the Home Node without waiting for acknowledgement from the Request Node of completion of the transaction.

Abstract: Methods, systems, and computer program products are included for querying and retrieving objects from images. An example method includes traversing a persistent local mirror overlay filesystem (PLMO FS) to determine whether one or more objects of a requested image already exist on a local data storage device. If so, an I/O hit is determined, and the objects are not pulled from the registry. Conversely, if the objects are not found on the local data storage device, an I/O miss is determined, and the objects are pulled from the registry. A local copy of the requested image is then built using the already locally-existing I/O-hit objects and the newly retrieved I/O-missed objects, such that the local copy of the requested image is a mirror of the original requested image in the registry.

Abstract: Example implementations involve a plurality of servers, network, and storage systems, wherein some of the servers may execute data programs and store primary data in the memory of the servers. Some of the servers may also execute a standby data program. Storage devices may provide for a snapshot volume, a log volume, and a recovery volume, and executes a recovery program to store a recovery image into the recovery volume from the data of the snapshot volume and the log volume. On failure of the server, the standby data program loads the recovery image of the recovery volume, which can reduce the time to commit logs to the snapshot image.

Abstract: A distributed file system may be configured with file blocks of a first type and file blocks of a second type, from allocation units that comprise a logical volume containing the file system. File blocks of the second type may be defined from one or more file blocks of the first type. A thick file may be instantiated with a number of allocation units totaling a size greater than or equal to a specified file size of the thick file. The allocation units may be allocated to the thick file in units of file blocks of the first type or file blocks of the second type, depending on the specified file size of the thick file.

Abstract: A mechanism is provided for efficient coherence state modification of cached data stored in a range of addresses in a coherent data processing system in which data coherency is maintained across multiple caches. A tag search structure is maintained that identifies address tags and coherence states of cached data indexed by address tags. In response to a request from a device internal to or external from the coherence network, the tag search structure is searched to identify address tags of cached data for which the coherence state is to be modified and requests are issued in the data processing system to modify a coherence state of cached lines with the identified address tags. The request from the external device may specify a range of addresses for which a coherence state change is sought. The tag search structure may be implemented as search tree, for example.

Abstract: An information handling system includes a planar board and a peripheral interface device. The planar board includes a central processing unit, a baseboard management controller, and an interface logic circuit. The peripheral interface device includes a microcontroller and a serial communication interface device. The peripheral interface device is coupled to a peripheral device. The information handling system also includes an interconnect to couple signals from the planar board to the peripheral interface device. The interconnect includes a single wire to couple first information from the interface logic circuit to the peripheral interface device and to couple second information from the serial communication interface device to the interface logic circuit. The first information includes a first power control command.

Abstract: Examples of the present disclosure describe systems and methods for sharing memory using a multi-ring shared, traversable and dynamic database. In aspects, the database may be synchronized and shared between multiple processes and/or operation mode protection rings of a system. The database may also be persisted to enable the management of information between hardware reboots and application sessions. The information stored in the database may be view independent, traversable, and resizable from various component views of the database. In some aspects, an event processor is additionally described. The event processor may use the database to allocate memory chunks of a shared heap to components/processes in one or more protection modes of the operating system.

Abstract: Exemplary embodiments provide the ability to associate multiple collections of metadata to objects. In one embodiment, a storage system comprises: a processor; a memory; at least one object, each object including content data; system metadata associated with each object; and a plurality of named collections of user-defined metadata associated with each object. Each named collection of the plurality of named collections is separately addressable by a request. In some embodiments, at least one named collection of user-defined metadata of one object of the at least one object includes an access control list, and the access control list of a named collection specifies permissible access to the named collection. The one object has an object-level access control list which specifies permissible access to the one object and which is different from the access control list for the named collection associated with the one object.

Abstract: A method of operating a data storage device includes receiving size information of a region needed for a data transaction from a host, calculating the sum of a size of a first region available in an invisible region-to-user and a size of a second region available in a visible region-to-user based on the size information, and communicating a response indicating possibility of the data transaction to the host based on a calculation result.

Abstract: A computer-implemented method includes identifying a query, including one or more predicates and one or more branches, wherein one or more branches includes one or more legs. The computer-implemented method further includes, for each branch, in parallel: determining a risk, determining a return row threshold, estimating a number of return rows; terminating access if the return rows exceed the threshold. The computer-implemented method further includes, for each leg, in parallel: determining a leg return row threshold; accessing the leg; fetching one or more return rows into one or more leg return row pages; terminating access if the return rows exceed the threshold; intersecting one or more leg return row pages into one or more intersected leg return row pages; and applying the one or more predicates to the one or more intersected leg return row pages. The method may be embodied in a corresponding computer system or computer program product.

Abstract: According to some embodiments, a backup storage system receives a request from a client for writing a data segment associated with a file object stored to a storage system. In response to the request, the system writes the data segment to one of many storage units of the storage system. The system determines whether the data segment is associated with a file region of the file object that is frequently accessed. The system writes the data segment in a first of many of write-evict units (WEUs) stored in a solid state device (SSD) operating as a cache memory device for caching data, after it is determined that the data segment is associated with the frequently accessed file region.

Abstract: A storage device includes nonvolatile memory devices arranged in groups, and a controller connected with the groups respectively through channels. The controller is configured to generate an access request for a nonvolatile memory device among the nonvolatile memory devices, and transmit, based on the access request, access requests respectively to two or more groups, among the groups, respectively through two or more channels, among the channels.

Abstract: A system is proposed to enable a hardware based host controller to perform operations related to Host-aware Performance booster (HPB). The host controller may retrieve a command packet from a host memory targeting a logical address of a storage location of the storage device, may retrieve a physical address of the storage device mapped to the logical address from the address map, and may send the command packet to the storage device. The sent command packet may have the physical address incorporated therein.

Abstract: Enhanced data buffer control in data systems is presented herein. In one example, a method of handling data buffer resources in a graphics processor includes establishing a pool of available memory pages tracked by memory pointers for use in a growable data structure. Responsive to requests by at least a shader unit of the graphics processor for space in the growable data structure in which to write shader data, the method includes providing to the shader unit at least write pointers to locations within memory pages from the growable data structure in accordance with data sizes indicated in the requests. Responsive to exceeding a threshold fullness of the growable data structure, the method includes allocating at least one further memory page from the pool of available memory pages for inclusion in the growable data structure.

Abstract: A method and system performs instruction scheduling in an out-of-order microprocessor pipeline. The method and system selects a first set of instructions to dispatch from a scheduler to an execution module, wherein the execution module comprises two types of execution units. The first type of execution unit executes both a first and a second type of instruction and the second type of execution unit executes only the second type. Next, the method selects a second set of instructions to dispatch, which is a subset of the first set and comprises only instructions of the second type. The method determines a third set of instructions, which comprises instructions not selected as part of the second set. Further, the method dispatches the second set for execution using the second type of execution unit and dispatching the third set for execution using the first type of execution unit.

Abstract: According to one embodiment, a memory system manages a plurality of management tables corresponding to a plurality of first blocks in a nonvolatile memory. Each management table includes a plurality of reference counts corresponding to a plurality of data in a corresponding first block. The memory system copies, based on a first management table corresponding to a copy-source block for garbage collection, only data corresponding to reference counts of non-zero from the copy-source block to a copy-destination block, and associates physical addresses respectively indicating locations in the copy-destination block, in which the data are copied, with respective intermediate addresses corresponding to the copied data.

Abstract: According to one embodiment, a memory system manages a plurality of management tables corresponding to a plurality of first blocks in a nonvolatile memory. Each management table includes a plurality of reference counts corresponding to a plurality of data in a corresponding first block. The memory system copies a set of data included in a copy-source block for garbage collection and corresponding respectively to reference counts belonging to a first reference count range to a first copy-destination block, and copies a set of data included in the copy-source block and corresponding respectively to reference counts belonging to a second reference count range having a lower limit higher than an upper limit of the first reference count range to a second copy-destination block.

Abstract: A data processing apparatus comprises register rename circuitry for mapping architectural register specifiers specified by instructions to physical registers to be accessed in response to the instructions. Available register control circuitry controls which physical registers are available for mapping to an architectural register specifier by the register rename circuitry. For at least one group of two or more physical registers, the available register control circuitry controls availability of the registers based on a group tracking indication indicative of whether there is at least one pending access to any of the physical registers in the group.

Abstract: There is provided with an information processing apparatus and a method of controlling the same. The apparatus sets a naming rule for an image file and determines whether or not the set naming rule satisfies a predetermined condition. If it is determined that the naming rule does not satisfy the predetermined condition, the information processing apparatus warns a user. On the other hand, if it is determined that the naming rule satisfies the predetermined condition, the information processing apparatus generates a file name of the image file in accordance with the set naming rule, and stores the image file with the file name.

Abstract: Systems and methods for providing object versioning in a storage system may support the logical deletion of stored objects. In response to a delete operation specifying both a user key and a version identifier, the storage system may permanently delete the specified version of an object having the specified key. In response to a delete operation specifying a user key, but not a version identifier, the storage system may create a delete marker object that does not contain object data, and may generate a new version identifier for the delete marker. The delete marker may be stored as the latest object version of the user key, and may be addressable in the storage system using a composite key comprising the user key and the new version identifier. Subsequent attempts to retrieve the user key without specifying a version identifier may return an error, although the object was not actually deleted.

Abstract: A video compression method and a video compressor are provided to solve problems of huge resource consumption and high costs caused by performing both H.264 compression and HEVC compression. The method specifically includes: reading video signal data by using a sliding window to generate bitstream data, where bitstream data generated by reading the video signal data according to a first format is first bitstream data, and bitstream data generated by reading the video signal data according to a second format is second bitstream data; and coding the bitstream data to generate a bitstream, where a bitstream generated by coding the first bitstream data is a first bitstream, and a bitstream generated by coding the second bitstream data is a second bitstream, where the second format is a format preset according to the first format. The present invention is applied to video signal compression.

Abstract: One or more techniques and/or computing devices are provided for data object retention. For example, a data retention policy may specify that files of a volume are to be locked down for a lockdown retention period (e.g., locked into a read only state for 4 months) when such files are not changed within an auto commit time period (e.g., files not changed within 13 hours). Waiting for a data scanner to evaluate files for lockdown may result in files violating the data retention policy until the data scanner evaluates such files. Accordingly, a file may be considered to be in the locked down state (e.g., instantaneous lockdown), such that commands to modify or delete the file are blocked, based upon a difference between a current time of an internal compliance clock and a current value of a data object change field exceeding the auto commit time period.

Abstract: Functionality is described herein for memory-mapping an information unit (such as a file) into virtual memory by associating shared virtual memory resources with the information unit. The functionality then allows processes (or other entities) to interact with the information unit via the shared virtual memory resources, as opposed to duplicating separate private instances of the virtual memory resources for each process that requests access to the information unit. The functionality also uses a single level of address translation to convert virtual addresses to corresponding physical addresses. In one implementation, the information unit is stored on a bulk-erase type block storage device, such as a flash storage device; here, the single level of address translation incorporates any address mappings identified by wear-leveling and/or garbage collection processing, eliminating the need for the storage device to perform separate and independent address mappings.

Abstract: Systems and methods for assessing configuration profiles for a user configurable device. The configuration profile may include sets configuration parameters and an associated configuration parameter values that may be analyzed to determine a set of current states for the user configurable device. The set of current states may be used to identify a candidate state that is related to a candidate configuration profile. The candidate configuration profile may include at least one set of a candidate configuration parameter and an associated candidate configuration parameter value. One or more prompts may be rendered via the customer device to set at least one of the configuration parameters and associated configuration parameter values based on the corresponding candidate configuration parameter values. A response is received via the user interface to the prompt, and an indication of such response may be transmitted to update the identification of the subsequent candidate configuration profiles.

Abstract: A FIFO memory device has a first number of data storage units and a second number of internal FIFO memories. Each internal FIFO memory has a third number of internal data storage units. The first number is a product of the second and third numbers. A fourth number of data inputs receives input data units in order. Input multiplexer circuitry connects each one of the data inputs to any one of the internal FIFO memories, for storage of input data units, in order, in a first layer of the FIFO memory device including corresponding storage locations in respective ones of the internal FIFO memories. The first layer may be physical, or may be logical and maintained by pointers. Output multiplexer circuitry coupled to the internal FIFO memories connects each of the internal FIFO memories to any one of the data outputs to read out the stored data units in order.

Abstract: Technologies for dynamic loading of integrity protected modules into a secure enclave include a computing device having a processor with secure enclave support. The computing device divides an executable image into multiple chunks, hashes each of the chunks with corresponding attributes that affect security to generate a corresponding hash value, and generates a hash tree as a function of the hash values. The computing device generates an initial secure enclave memory image that includes the root value of the hash tree. At runtime, the computing device accesses a chunk of the executable image from within the secure enclave, which generates a page fault. In response to the page fault, the secure enclave verifies the associated chunk based on the hash tree and accepts the chunk into the secure enclave in response to successful verification. The root value of the hash tree is integrity-protected. Other embodiments are described and claimed.

Abstract: A computer system with multiple security levels, the system comprising a high-power processing device (130), a low-power processing device (110), and an interface unit (120) comprising functions for moving classified information between the high-power device (130) and the low-power device (110) according to formal rules for confidentiality and/or integrity. Additional security aspects, e.g. availability, may readily be accommodated. A method for implementing multiple levels of security along a number of independent security axes on the system is also disclosed.

Abstract: Systems, methods, and apparatuses relating to a memory fence mechanism in a configurable spatial accelerator are described. In one embodiment, a processor includes a plurality of processing elements and an interconnect network between the plurality of processing elements to receive an input of a dataflow graph comprising a plurality of nodes, wherein the dataflow graph is to be overlaid into the interconnect network and the plurality of processing elements with each node represented as a dataflow operator in the plurality of processing elements, and the plurality of processing elements are to perform a plurality of operations, each by a respective, incoming operand set arriving at each of the dataflow operators of the plurality of processing elements. The processor also includes a fence manager to manage a memory fence between a first operation and a second operation of the plurality of operations.

Abstract: A method and apparatus for implementing row hammer avoidance in a dynamic random access memory (DRAM) in a computer system. Hammer detection logic identifies a hit count of repeated activations at a specific row in the DRAM. Monitor and control logic receiving an output of the hammer detection logic compares the identified hit count with a programmable threshold value. Responsive to a specific count as determined by the programmable threshold value, the monitor and control logic captures the address where a selected row hammer avoidance action is provided.

Abstract: An unrecoverable error is determined when attempting to access data stored in a target memory unit of a storage medium of a data storage device. Access to neighboring memory units that are proximate to the target memory unit is controlled in response. The controlling of the access affects a temperature of the target memory unit over a period of time. After the period of time, access to the data is attempted from the target memory unit.

Abstract: In an example, a method of managing virtualization software installed on a host computer includes connecting to a platform management system in the host computer while a hardware platform in the host computer is in a low-power state; and accessing files of the virtualization software on a storage device in the platform management system through a distributed file system service executing on a controller of the platform management system.

Abstract: A memory device includes: a set of input pads configured to receive from a source external to the memory device one or more input signals and a chip select signal; an operation circuit electrically coupled to the input pads, operation circuit configured to perform operations corresponding to the one or more input signals when the chip select signal is enabled; and an input management circuit electrically coupled to and between the input pads and the operation circuit, the input management circuit configured to control propagation of the one or more input signals based on the chip select signal.

Abstract: An information handling system includes a device, a controller, and a license manager subsystem. The controller is configured to determine whether the device has a license assigned and to communicate with the device pursuant to a uniform protocol. The communications include issuing a command to the device to provide an identification and a command to the device to activate itself.

Abstract: An apparatus is described having instruction execution logic circuitry to execute first, second, third and fourth instruction. Both the first instruction and the second instruction insert a first group of input vector elements to one of multiple first non overlapping sections of respective first and second resultant vectors. The first group has a first bit width. Each of the multiple first non overlapping sections have a same bit width as the first group. Both the third instruction and the fourth instruction insert a second group of input vector elements to one of multiple second non overlapping sections of respective third and fourth resultant vectors. The second group has a second bit width that is larger than said first bit width. Each of the multiple second non overlapping sections have a same bit width as the second group.

Abstract: A method and apparatus for implementing row hammer avoidance in a dynamic random access memory (DRAM) in a computer system. Hammer detection logic identifies a hit count of repeated activations at a specific row in the DRAM. Monitor and control logic receiving an output of the hammer detection logic compares the identified hit count with a programmable threshold value. Responsive to a specific count as determined by the programmable threshold value, the monitor and control logic captures the address where a selected row hammer avoidance action is provided.

Abstract: A device having a controller configured to interface with a host, a storage class memory configured to interface with the controller and a flash memory configured to interface with the controller, wherein both the storage class memory and the flash memory are configured to store data, and wherein the controller is configured to separate the data according to latency critical data and non-latency critical data.

Abstract: Provided is a more versatile technique that makes it possible to input dummy information in response to an attacker seeking to collect normal information that cannot be replaced with dummy information. In the present invention, a dummy information insertion device inserts dummy information into a second location that is determined using: first location information indicating a first location that contains normal information, from among all normal information in a computer, which cannot be replaced with other information; and insertion condition information that indicates conditions for determining the second location into which dummy information is to be inserted, with such dummy information resembling the normal information that cannot be replaced and not being present in the computer or in a local network connected to the computer.

Abstract: One embodiment facilitates a high-priority read. During operation, the system receives, by a controller module of a storage device, a first request to write first data to a non-volatile memory of the storage device. The system commences a write operation to write the first data to the non-volatile memory. In response to detecting a second request to read second data from the non-volatile memory, the system: suspends the write operation; reads the second data from the non-volatile memory; and resumes the suspended write operation.

Abstract: A storage system includes a plurality of solid-state drives (SSDs) in which each SSD is an endpoint of a peer group in which one SSD is a primary SSD of the peer group, or all SSDs are treated as equal peers. Each SSD further includes a host interface port coupled to a host computing device that receives receive input/output (I/O) communications from the host computing device, a peer-interface port coupled to the peer-interface port of each other SSD in the peer group; and a controller coupled to the host interface port and the peer-interface port. The primary SSD controller is responsive to I/O communications received from the host computing device to provide data-protection computations relating to a coordinated data-protection configuration provided by the peer group and to pass the coordinated data-protection configuration information to the controllers of the other end points of the peer group through the peer-interface port.