Abstract: A fin field effect transistor (FinFET) and a method for fabricating the FinFET are provided. The method includes providing a plurality of discrete fins on a semiconductor substrate, and forming a dummy gate across a length portion of the fins and covering portions of top and sidewall surfaces of the fins. The method also includes forming an interlayer dielectric layer, covering the dummy gate and the fins, and forming an opening in the interlayer dielectric layer. In addition, the method includes forming a gate dielectric layer in the opening and on the interlayer dielectric layer, and forming a barrier layer on the gate dielectric layer. Moreover, the method includes removing the gate dielectric layer and the barrier layer from the interlayer dielectric layer, and performing an annealing treatment. Further, the method includes removing the barrier layer in the opening, and forming a metal gate in the opening.

Abstract: Semiconductor device and fabrication method are provided. The method includes: providing a base substrate; forming gate structures on the base substrate; forming source/drain doped regions in the base substrate on sides of each gate structure, where the source/drain doped regions have recessed top surfaces and are doped with source/drain ions; and doping into the recessed top surfaces of the source/drain doped regions with contact ions to form contact doped regions in top portions of the source/drain doped regions, where the contact ions have a conductivity type same as the source/drain ions.

Abstract: The method comprises fabricating a semiconductor panel comprising a plurality of semiconductor devices, fabricating a cap panel comprising a plurality of caps, bonding the cap panel onto the semiconductor panel so that each one of the caps covers one or more of the semiconductor devices, and singulating the bonded panels into a plurality of semiconductor modules.

Abstract: Provided is a FinFET including a substrate, at least one fin and at least one gate. A portion of the at least one fin is embedded in the substrate. The at least one fin includes, from bottom to top, a seed layer, a stress relaxation layer and a channel layer. The at least one gate is across the at least one fin. A method of forming a FinFET is further provided.

Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a single crystal substrate, a source/drain structure and a nanowire structure. The source/drain structure is disposed on and contacts with the substrate. The nanowire structure is connected to the source/drain structure.

Abstract: A semiconductor device includes a semiconductor substrate, first and second device fins extending from the semiconductor substrate, and a fill fin disposed on the semiconductor substrate and between the first and second device fins, wherein the fill fin has an opening. The semiconductor device further includes a first gate structure extending continuously from a channel region of the first device fin to a channel region of the second device fin through the opening.

Abstract: A method of manufacturing conductors for a semiconductor device, the method comprising: forming a structure on a base; and eliminating selected portions of members of a first set and selected portions of members of a second set from the structure. The structure includes: capped first conductors arranged parallel to a first direction; and capped second conductors arranged parallel to and interspersed with the capped first conductors. The capped first conductors are organized into at least first and second sets. Each member of the first set has a first cap with a first etch sensitivity. Each member of the second set has a second cap with a second etch sensitivity. Each of the capped second conductors has a third etch sensitivity. The first, second and third etch sensitivities are different.

Abstract: An integrated circuit includes a semiconductor substrate, a gate dielectric over the substrate, and a metal gate structure over the semiconductor substrate and the gate dielectric. The metal gate structure includes a first metal material. The integrated circuit further includes a seal formed on sidewalls of the metal gate structure. The integrated circuit further includes a dielectric film on the metal gate structure, the dielectric film including a first metal oxynitride comprising the first metal material and directly on the metal gate structure without extending over the seal formed on sidewalls of the metal gate structure.

Abstract: Techniques and structures for controlling etch-back of a finFET fin are described. One or more layers may be deposited over the fin and etched. Etch-back of a planarization layer may be used to determine a self-limited etch height of one or more layers adjacent the fin and a self-limited etch height of the fin. Strain-inducing material may be formed at regions of the etched fin to induce strain in the channel of a finFET.

Abstract: A method for forming a semiconductor device comprising forming a semiconductor fin on a substrate, forming a first sacrificial gate stack over a first channel region of the fin and forming a second sacrificial gate stack over a second channel region of the fin, forming spacers adjacent to the first sacrificial gate stack and the second sacrificial gate stack, depositing a first liner layer on the spacers, the first sacrificial gate stack and the second sacrificial gate stack, depositing a first sacrificial layer on the first liner layer, removing a portion of the first sacrificial layer over the first gate stack to expose a portion of the first liner layer on the first sacrificial gate stack, and growing a first semiconductor material on exposed portions of the fin to form a first source/drain region adjacent to the first gate sacrificial gate stack.

Abstract: A three-dimensional (3D) semiconductor memory device that includes a peripheral logic structure including peripheral logic circuits disposed on a semiconductor substrate and a first insulation layer overlapping the peripheral logic circuits, and a plurality of memory blocks spaced apart from each other on the peripheral logic structure. At least one of the memory blocks includes a well plate electrode, a semiconductor layer in contact with a first surface of the well plate electrode, a stack structure including a plurality of electrodes vertically stacked on the semiconductor layer, and a plurality of vertical structures penetrating the stack structure and connected to the semiconductor layer.

Abstract: Various embodiments of the present application are directed to a method for forming an integrated circuit (IC), and the associated integrated circuit. In some embodiments, a stack of gate dielectric precursor layers is formed on a plurality of logic sub-region and is then selectively removed from at least two logic sub-regions. Then, a gate dielectric precursor layer is formed, and a plasma treatment process and an annealing process are subsequently performed. The gate dielectric precursor layer is then selectively removed from a low-voltage logic sub-region, but not a high-voltage logic sub-region. By removing the stack of gate dielectric precursor layers from the low-voltage logic sub-region prior to performing the plasma treatment process and the annealing process, less gate dielectric precursor material is treated, annealed, and removed from the low-voltage logic sub-region. Thus, the resulting residues are reduced, and the defects introduced by the residues are also reduced or eliminated.

Abstract: A semiconductor device includes an outside-of-well n-type region, a p-type well region surrounded by the outside-of-well n-type region, an inside-of-well n-type region, and a gate electrode. The outside-of-well n-type region includes an impurity low-concentration region that is in contact with the p-type well region, and an impurity high-concentration region that is separated from the p-type well region by the impurity low-concentration region.

Abstract: A substrate having a silicon region and a silicon germanium region is provided. A first set of fins in the silicon region and a second set of fins in the silicon germanium region is etched into the substrate. A set of protective caps on upper portions of the first and second sets of fins. A lower portion of each of the first and second sets of fins is oxidized. The silicon germanium portion of the lower portion of fin in the second set of fins is completely oxidized. The lower portion of the first set of fins is partially oxidized. A punchthrough stop isolation region is formed in the lower portion of the first set of fins.

Abstract: A method includes providing a semiconductor substrate having first and second regions that are doped with first and second dopants respectively. The first and second dopants are of opposite types. The method further includes epitaxially growing a first semiconductor layer that is doped with a third dopant. The first and third dopants are of opposite types. The method further includes depositing a dielectric hard mask (HM) layer over the first semiconductor layer; patterning the dielectric HM layer to have an opening over the first region; extending the opening towards the semiconductor substrate; and epitaxially growing a second semiconductor layer in the opening. The second semiconductor layer is doped with a fourth dopant. The first and fourth dopants are of a same type. The method further includes removing the dielectric HM layer; and performing a first CMP process to planarize both the first and second semiconductor layers.

Abstract: A vertical SRAM cell includes a first (1st) inverter having a 1st pull-up (PU) transistor and a 1st pull-down (PD) transistor. The 1st PU and 1st PD transistors have a bottom source/drain (S/D) region disposed on a substrate and a channel extending upwards from a top surface of the bottom S/D region. A second (2nd) inverter has a 2nd PU transistor and a 2nd PD transistor. The 2nd PU and 2nd PD transistors have a bottom S/D region disposed on the substrate and a channel extending upwards from a top surface of the bottom S/D region. A 1st metal contact is disposed on sidewalls, and not on the top surface, of the bottom S/D regions of the 1st PU and 1st PD transistors. A 2nd metal contact is disposed on sidewalls, and not on the top surface, of the bottom S/D regions of the 2nd PU and 2nd PD transistors.

Abstract: A patterning method for fabricating a semiconductor device includes forming, for example sequentially forming, a lower buffer layer, a first channel semiconductor layer, and a capping insulating layer on a substrate, forming an opening to penetrate the capping insulating layer and the first channel semiconductor layer and expose a portion of the lower buffer layer, forming a second channel semiconductor layer to fill the opening and include a first portion protruding above the capping insulating layer, performing a first CMP process to remove at least a portion of the first portion, removing the capping insulating layer, and performing a second CMP process to remove at least a portion of a second portion of the second channel semiconductor layer protruding above the first channel semiconductor layer.

Abstract: At least one method, apparatus and system disclosed involves a semiconductor substrate on which NMOS and PMOS devices with enhanced current drives may be formed. A first substrate having an enhanced electron mobility is formed. A second substrate having an enhanced hole mobility is formed. The first substrate and the second substrate are bonded for forming a third substrate. A first channel on the third substrate characterized by the enhanced electron mobility is formed. A second channel on the third substrate characterized by the enhanced hole mobility is formed.

Abstract: A method for testing a monolithic stacked integrated circuit (IC) is provided. The method includes receiving a layer of the IC. The layer has a first surface and a second surface, and the layer includes a substrate. The method further includes attaching probe pads to the first surface, and applying a first fault testing to the IC through the probe pads. The method further includes forming another layer of the IC over the second surface, and applying a second fault testing to the IC through the probe pads.

Abstract: A well potential supply region is provided in an N-type well region of a cell array. Adjacent gates disposed in both sides of the well potential supply region in the horizontal direction and adjacent gates disposed in further both sides thereof are disposed at the same pitch. In addition, an adjacent cell array includes four gates each of which is opposed to the adjacent gates in the vertical direction. In other words, regularity in the shape of the gate patterns in the periphery of the well potential supply region is maintained.

Abstract: A method of making a semiconductor device includes forming a titanium nitride layer over a gate dielectric layer. The method further includes performing a silicon treatment on the titanium nitride layer to form at least one silicon monolayer over the titanium nitride layer. The method further includes driving silicon from the at least one silicon monolayer into the titanium nitride layer to form a TiSiON layer.

Abstract: When a MISFET is formed by using a gate last process and replacing dummy gate electrodes with metal gate electrodes, both of respective cap insulating films and an interlayer insulating film over a control gate electrode and the dummy gate electrodes are polished to prevent excessive polishing of the upper surface of the interlayer insulating film and the occurrence of dishing. In the gate last process, the interlayer insulating film is formed to cover the control gate electrode and the dummy gate electrodes as well as the cap insulating films located thereover. After the upper surface of the interlayer insulating is polished to expose the cap insulating films from the interlayer insulating films, etching is performed to selectively remove the cap insulating films. Subsequently, the upper surfaces of the interlayer insulating films are polished.

Abstract: A semiconductor structure is provided that includes a fin structure of, from bottom to top, a semiconductor punch through stop (PTS) doping fin portion, a dielectric material fin portion, and a topmost semiconductor fin portion that is present on a wider semiconductor fin base. A functional gate structure straddles the semiconductor fin structure. Portions of the wider semiconductor fin base that are not located directly beneath the fin structure of the present application and that are not covered by the functional gate structure can be used as an area for epitaxial growth of source/drain structures. The wide semiconductor fin base improves source/drain epitaxy for better dopant incorporation and strain enhancement.

Abstract: A method of fabricating a semiconductor device includes forming at least one semiconductor fin on a semiconductor substrate. A cladding layer is epitaxially grown on a portion of the at least one semiconductor fin. The cladding layer is oxidized such that r such that ions are condensed therefrom and are diffused into the at least one semiconductor fin while the cladding layer is converted to an oxide layer. The oxide layer is removed to expose the at least one semiconductor fin having a diffused fin portion that enhances electron hole mobility therethrough.

Abstract: The invention relates to ammoniacal formulations comprising a) at least one hydroxozinc compound and b) at least one compound of an element of the 3rd primary group, to the use thereof, to a method using said formulations to produce layers comprising ZnO and to electronic components produced using same.

Abstract: A fin field device structure and method for forming the same are provided. The FinFET device structure includes a substrate and a fin structure extending from the substrate. The FinFET device structure also includes an anti-punch through implant (APT) region formed in the fin structure and a barrier layer formed on the APT region. The barrier layer has a middle portion and a peripheral portion, and the middle portion is higher than the peripheral portion. The FinFET device structure further includes an epitaxial layer formed on the barrier layer.

Abstract: Methods and systems for large silicon photonic interposers by stitching are disclosed and may include, in an integrated optical communication system including CMOS electronics die coupled to a silicon photonic interposer, where the interposer includes a plurality of reticle sections: communicating an optical signal between two of the plurality of reticle sections utilizing a waveguide. The waveguide may include a taper region at a boundary between the two reticle sections, the taper region expanding an optical mode of the communicated optical signal prior to the boundary and narrowing the optical mode after the boundary. A continuous wave (CW) optical signal may be received in a first of the reticle sections from an optical source external to the interposer. The CW optical signal may be received in the interposer from an optical source assembly coupled to a grating coupler in the first of the reticle sections in the silicon photonic interposer.

Abstract: A substrate having a silicon region and a silicon germanium region is provided. A first set of fins in the silicon region and a second set of fins in the silicon germanium region is etched into the substrate. A set of protective caps on upper portions of the first and second sets of fins. A lower portion of each of the first and second sets of fins is oxidized. The silicon germanium portion of the lower portion of fin in the second set of fins is completely oxidized. The lower portion of the first set of fins is partially oxidized. A punchthrough stop isolation region is formed in the lower portion of the first set of fins. Another aspect of the invention is a device which is created by the method.

Abstract: A method of forming a spacer for a vertical transistor is provided. The method includes forming a fin structure on a substrate, depositing a first spacer on exposed surfaces of the substrate to define gaps between the first spacer and the fin structure and depositing a second spacer on the exposed surfaces of the substrate in at least the gaps.

Abstract: A semiconductor structure includes a substrate, at least one first gate structure, at least one first spacer, at least one source drain structure, at least one conductor, and at least one protection layer. The first gate structure is present on the substrate. The first spacer is present on at least one sidewall of the first gate structure. The source drain structure is present adjacent to the first spacer. The conductor is electrically connected to the source drain structure. The protection layer is present between the conductor and the first spacer and on a top surface of the first gate structure.

Abstract: Disclosed is a method of forming a semiconductor device. The method includes providing a precursor having a substrate and gate stacks over the substrate, wherein each of the gate stacks includes an electrode layer, a first hard mask (HM) layer over the electrode layer, and a second HM layer over the first HM layer. The method further includes depositing a dielectric layer over the substrate and the gate stacks and filling spaces between the gate stacks; and performing a first chemical mechanical planarization (CMP) process to partially remove the dielectric layer. The method further includes performing an etching process to remove the second HM layer and to partially remove the dielectric layer, thereby exposing the first HM layer. The method further includes performing a second CMP process to at least partially remove the first HM layer.

Abstract: A vertically integrated circuit device can include a substrate having a first region reserved for first functional circuits of the vertically integrated circuit device, where the first functional circuits has a substantially constant top surface level across the first region and having a second region reserved for second functional circuits of the vertically integrated circuit device and spaced apart from the first region. The second functional circuits can have a varied top surface level across the second region. A doped oxidation suppressing material can be included in the substrate and can extend from the first region to the second region at an interface of the substrate with the first functional circuits and the second functional circuits, respectively.

Abstract: Vertical gate all around devices are formed by initially forming a first doped region and a second doped region that are planar with each other. A channel layer is formed over the first doped region and the second doped region, and a third doped region is formed over the channel layer. A fourth doped region is formed to be planar with the third doped region, and the first doped region, the second doped region, the third doped region, the fourth doped region, and the channel layer are patterned to form a first nanowire and a second nanowire, which are then used to form the vertical gate all around devices.

Abstract: Semiconductor devices and manufacturing method of the same are disclosed. A semiconductor device includes a substrate, a p-type MOS transistor, an n-type MOS transistor and a cured flowable oxide layer. The substrate includes a first region and a second region. The p-type MOS transistor is in the first region. The n-type MOS transistor is in the second region. The cured flowable oxide layer covers the p-type MOS transistor and the n-type MOS transistor, wherein a first strain of the cured flowable oxide layer applying to the p-type MOS transistor is different from a second strain of the cured flowable oxide layer applying to the n-type MOS transistor, and the difference therebetween is greater than 0.002 Gpa.

Abstract: An imaging circuit includes a first vertical trench gate and a neighboring second vertical trench gate. The imaging circuit includes a gate control circuit. The gate control circuit operates in a first operating mode to generate a first space charge region accelerating photogenerated charge carriers of a first charge-carrier type to a first collection contact in and in a second operating mode to generate a second space charge region accelerating photogenerated charge carriers of the first charge-carrier type to the first collection contact. The imaging circuit further includes an image processing circuit which determines distance information of an object based on photogenerated charge carriers of the first charge carrier type collected at the first collection contact in the first operating mode and color information of the object based on photogenerated charge carriers of the first charge carrier type collected at the first collection contact in the second operating mode.

Abstract: A method of manufacturing a memory device includes an nMOS region and a pMOS region in a substrate. A first gate is defined within the nMOS region, and a second gate is defined in the pMOS region. Disposable spacers are simultaneously defined about the first and second gates. The nMOS and pMOS regions are selectively masked, one at a time, and LDD and Halo implants performed using the same masks as the source/drain implants for each region, by etching back spacers between source/drain implant and LDD/Halo implants. All transistor doping steps, including enhancement, gate and well doping, can be performed using a single mask for each of the nMOS and pMOS regions. Channel length can also be tailored by trimming spacers in one of the regions prior to source/drain doping.

Abstract: A method for fabricating semiconductor device is disclosed. First, a substrate having a fin-shaped structure thereon is provided, a spacer is formed adjacent to the fin-shaped structure, and the spacer is used as mask to remove part of the substrate for forming an isolation trench, in which the isolation trench includes two sidewall portions and a bottom portion. Next, a plasma doping process is conducted to implant dopants into the two sidewall portions and the bottom portion of the isolation trench.

Abstract: In a method for manufacturing a semiconductor device, a substrate is provided. A dummy gate is formed on the substrate. A first dielectric layer is formed to peripherally enclose the dummy gate over the substrate. A second dielectric layer is formed to peripherally enclose the first dielectric layer over the substrate. The second dielectric layer and the first dielectric layer are formed from different materials. An implant operation is performed on the first dielectric layer to form a first doped portion in the first dielectric layer. The dummy gate is removed to form a hole in the first dielectric layer. An operation of removing the dummy gate includes removing a portion of the first doped portion to form the hole having a bottom radial opening area and a top radial opening area which is greater than the bottom radial opening area. A metal gate is formed in the hole.

Abstract: A method of forming a FinFET with a rounded source/drain profile comprises forming a fin in a substrate, etching a source/drain recess in the fin, forming a plurality of source/drain layers in the source/drain recess; and etching at least one of the plurality of source/drain layers. The source/drain layers may be a silicon germanium compound. Etching at the source/drain layers may comprises partially etching each of the plurality of source/drain layers prior to forming subsequent layers of the plurality of source/drain layers. The source/drain layers may be formed with a thickness at a top corner of about 15 nm, and the source/drain layers may each be etched back by about 3 nm prior to forming subsequent layers of the plurality of source/drain layers. Forming the plurality of source/drain layers optionally comprises forming at least five source/drain layers.

Abstract: A method of manufacturing a semiconductor device is provided in the present invention. Multiple spacer layers are used in the invention to form spacers with different predetermined thickness on different active regions or devices, thus the spacing between the strained silicon structure and the gate structure (SiGe-to-Gate) can be properly controlled and adjusted to achieve better and more uniform performance for various devices and circuit layouts.

Abstract: A method of forming a semiconductor device includes providing a semiconductor substrate. The semiconductor substrate includes a plurality of fins formed thereon, a stress layer formed on the top surface of each of the fins, and a plurality of strip-shaped gate structures formed above the stress layers. The method further includes forming a contact hole etch stop layer. The method further includes forming a first interlayer dielectric layer to fill the gaps between adjacent fins. The first interlayer dielectric layer includes filling voids formed therein. The method further includes back etching the first interlayer dielectric layer to cause the top surface of the first interlayer dielectric layer to be just above the filling voids. The method further includes forming a barrier liner layer over the first interlayer dielectric layer, and forming a second interlayer dielectric layer over the barrier liner layer and the contact hole etch stop layer.

Abstract: The present invention provides a method of forming an integrated circuit including a substrate, a first transistor, a second transistor and a third transistor. The first transistor has a first metal gate including a first bottom barrier layer, a first work function metal layer and a first metal layer. The second transistor has a second metal gate including a second bottom barrier layer, a second work function metal layer and a second metal layer. The third transistor has a third metal gate including a third bottom barrier layer, a third work function metal layer and a third metal layer. The first transistor, the second transistor and the third transistor has the same conductive type. A nitrogen concentration of the first bottom barrier layer>a nitrogen concentration of the second bottom barrier layer>a nitrogen concentration of the third bottom barrier layer.

Abstract: Semiconductor devices include a strain-inducing layer capable of applying a strain to a channel region of a transistor included in a miniaturized electronic device, and a method of manufacturing the semiconductor device. The semiconductor device includes a substrate having a channel region; a pair of source/drain regions provided on the substrate and arranged on both sides of the channel region in a first direction; and a gate structure provided on the channel region and comprising a gate electrode pattern extending in a second direction that is different from the first direction, a gate dielectric layer disposed between the channel region and the gate electrode pattern, and a gate spacer covering respective lateral surfaces of the gate electrode pattern and the gate dielectric layer. At least one of the source/drain regions includes a first strain-inducing layer and a second strain-inducing layer.

Abstract: A method of forming a vertical FET device and a horizontal FINFET device on a common semiconductor substrate includes forming, on the semiconductor substrate, vertical device fins for the vertical FET device and the horizontal FINFET device with a sacrificial layer and a hard mask (HM) layer. The method also includes forming a vertical FET device doped source and drain (S/D) on the substrate, forming a shallow trench isolation (STI) and a bottom spacer, removing the HM layer and the sacrificial layer for horizontal FINFET device, and forming a sacrificial gate. The method further includes forming an oxide inter dielectric (ILD) layer, and opening the sacrificial gate, forming high-k vertical FET device gate and a high-k horizontal FINFET device gate, and forming contacts.

Abstract: An integrated circuit may be formed by removing source/drain spacers from offset spacers on sidewalls of MOS transistor gates, forming a contact etch stop layer (CESL) spacer layer on lateral surfaces of the MOS transistor gates, etching back the CESL spacer layer to form sloped CESL spacers on the lateral surfaces of the MOS transistor gates with heights of ¼ to ¾ of the MOS transistor gates, forming a CESL over the sloped CESL spacers, the MOS transistor gates and the intervening substrate, and forming a PMD layer over the CESL.

Abstract: A memory device and a method for fabricating the same are provided. The memory device includes a substrate and an isolation structure. The substrate has at least two memory cells, and each of the memory cells includes a first active region, a second active region, and a gate structure. The first active region and the second active region are alternately disposed in the substrate. The gate structure is disposed in the substrate and between the first active region and the second active region. The isolation structure is disposed between and protruding from the second active regions of two adjacent memory cells.

Abstract: A semiconductor device including a first gate structure is disposed on the semiconductor substrate. The first gate structure includes a gate dielectric layer, an etch stop layer, a first work function metal, a second work function metal, and a fill metal. A second gate structure is also disposed on the semiconductor substrate. The second gate structure includes the gate dielectric layer, a second work function metal, and the fill metal. In an embodiment, the second gate structure also includes an etch stop layer.

Abstract: A method for manufacturing a semiconductor device comprises forming a first diffusion stop layer on a bulk semiconductor substrate, forming a doped semiconductor layer on the first diffusion stop layer, forming a second diffusion stop layer on the doped semiconductor layer, forming a fin layer on the doped semiconductor layer, patterning the first and second diffusion stop layers, the doped semiconductor layer, the fin layer and a portion of the bulk substrate, oxidizing the doped semiconductor layer to form an oxide layer, and forming a dielectric on the bulk substrate adjacent the patterned portion of the bulk substrate, the patterned first diffusion stop layer and the oxide layer.

Abstract: A silicon carbide semiconductor device has a first-conductivity-type semiconductor layer having a lower impurity concentration and formed on a first-conductivity-type semiconductor substrate, a second-conductivity-type semiconductor layer having a higher impurity concentration and selectively formed in the first-conductivity-type semiconductor layer, a second-conductivity-type base layer having a lower impurity concentration formed on a surface of the second-conductivity-type semiconductor layer, a first-conductivity-type source region selectively formed in a surface layer of the base layer, a first-conductivity-type well region formed to penetrate the base layer from a surface to the first-conductivity-type semiconductor layer, and a gate electrode formed via a gate insulation film on a surface of the base layer interposed between the source region and the well region.

Abstract: A semiconductor device a first epitaxially grown source/drain region comprising a first material arranged on a first fin, a second epitaxially grown source/drain region comprising the first material arranged on the second fin, the second epitaxially grown source/drain region arranged above the first epitaxially grown source/drain region, a third epitaxially grown source/drain region comprising the first material arranged on a second fin, a fourth epitaxially grown source/drain region comprising a second material arranged on the second fin, the fourth epitaxially grown source/drain region arranged above the third epitaxially grown source/drain region, and a gate stack arranged over a channel region of the first fin and a channel region of the second fin.