Complementary Insulated Gate Field Effect Transistors (i.e., Cmos) Patents (Class 438/199)
  • Patent number: 8673710
    Abstract: When forming sophisticated high-k metal gate electrode structures, the uniformity of the device characteristics may be enhanced by growing a threshold adjusting semiconductor alloy on the basis of a hard mask regime, which may result in a less pronounced surface topography, in particular in densely packed device areas. To this end, in some illustrative embodiments, a deposited hard mask material may be used for selectively providing an oxide mask of reduced thickness and superior uniformity.
    Type: Grant
    Filed: August 3, 2011
    Date of Patent: March 18, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Stephan Kronholz, Rohit Pal
  • Patent number: 8674451
    Abstract: The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate having a first region and a second region; a first gate stack of an n-type field-effect transistor (FET) in the first region; and a second gate stack of a p-type FET in the second region. The first gate stack includes a high k dielectric layer on the semiconductor substrate, a first crystalline metal layer in a first orientation on the high k dielectric layer, and a conductive material layer on the first crystalline metal layer. The second gate stack includes the high k dielectric layer on the semiconductor substrate, a second crystalline metal layer in a second orientation on the high k dielectric layer, and the conductive material layer on the second crystalline metal layer.
    Type: Grant
    Filed: December 10, 2008
    Date of Patent: March 18, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Simon Su-Horng Lin, Chi-Ming Yang, Chyi-Shyuan Chern, Chin-Hsiang Lin
  • Patent number: 8673720
    Abstract: An insulated-gate field-effect transistor (110, 114, or 122) is fabricated so that its gate dielectric layer (500, 566, or 700) contains nitrogen having a vertical concentration profile specially tailored to prevent boron in the overlying gate electrode (502, 568, or 702) from significantly penetrating through the gate dielectric layer into the underlying channel zone (484, 554, or 684) while simultaneously avoiding the movement of nitrogen from the gate dielectric layer into the underlying semiconductor body. Damage which could otherwise result from undesired boron in the channel zone and from undesired nitrogen in the semiconductor body is substantially avoided.
    Type: Grant
    Filed: March 27, 2009
    Date of Patent: March 18, 2014
    Assignee: National Semiconductor Corporation
    Inventors: Prasad Chaparala, D. Courtney Parker
  • Patent number: 8673724
    Abstract: Provided are methods of fabricating a semiconductor device that include providing a substrate that includes a first region having a gate pattern and a second region having a first trench and an insulating layer that fills the first trench. A portion of a sidewall of the first trench is exposed by etching part of the insulating layer and a first spacer is formed on a sidewall of the gate pattern. A second spacer is formed on the exposed sidewall of the first trench, wherein the first spacer and the second spacer are formed simultaneously.
    Type: Grant
    Filed: July 30, 2012
    Date of Patent: March 18, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Jine Park, Kee-Sang Kwon, Doo-Sung Yun, Bo-Un Yoon, Jeong-Nam Han
  • Patent number: 8674450
    Abstract: A method is provided for fabricating a semiconductor structure. The method includes providing a semiconductor substrate, and forming a shallow trench isolation structure in the semiconductor substrate. The method also includes forming a plurality of parallel gate structures on the semiconductor substrate surrounded by the shallow trench isolation structure. Further, the method includes forming a plurality of first trenches in the semiconductor substrate at least one side of the gate structures proximity to the shallow trench isolation structure, and forming a first silicon germanium layer with a first germanium concentration in each of the first trenches. Further the method also includes forming a plurality second trenches in semiconductor substrate at least one side of the gate structures farther from the shallow trench isolation structure, and forming a second silicon germanium layer with a second germanium concentration greater than the first germanium concentration in each of the second trenches.
    Type: Grant
    Filed: January 3, 2013
    Date of Patent: March 18, 2014
    Assignee: Semiconductor Manufacturing International Corp.
    Inventors: Hao Deng, Bin Zhang
  • Patent number: 8669153
    Abstract: A method is provided that includes providing a substrate; forming a transistor in the substrate, the transistor having a dummy gate; forming a dielectric layer over the substrate and transistor; forming a contact feature in the dielectric layer; and after forming the contact feature, replacing the dummy gate of the transistor with a metal gate. An exemplary contact feature is a dual contact.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: March 11, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chiung-Han Yeh, Ming-Yuan Wu, Kong-Beng Thei, Harry Chuang, Mong-Song Liang
  • Patent number: 8669590
    Abstract: Methods and apparatus for forming semiconductor structures are disclosed herein. In some embodiments, a semiconductor structure may include a first germanium carbon layer having a first side and an opposing second side; a germanium-containing layer directly contacting the first side of the first germanium carbon layer; and a first silicon layer directly contacting the opposing second side of the first germanium carbon layer. In some embodiments, a method of forming a semiconductor structure may include forming a first germanium carbon layer atop a first silicon layer; and forming a germanium-containing layer atop the first germanium carbon layer.
    Type: Grant
    Filed: August 26, 2011
    Date of Patent: March 11, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Errol Antonio C. Sanchez, Yi-Chiau Huang
  • Patent number: 8669154
    Abstract: A CMOS device includes high k gate dielectric materials. A PMOS device includes a gate that is implanted with an n-type dopant. The NMOS device may be doped with either an n-type or a p-type dopant. The work function of the CMOS device is set by the material selection of the gate dielectric materials. A polysilicon depletion effect is reduced or avoided.
    Type: Grant
    Filed: May 17, 2011
    Date of Patent: March 11, 2014
    Assignee: Infineon Technologies AG
    Inventor: Hong-Jyh Li
  • Patent number: 8669618
    Abstract: A manufacturing method for semiconductor device having metal gate includes providing a substrate having a first semiconductor device and a second semiconductor device formed thereon, the first semiconductor device having a first gate trench and the second semiconductor device having a second gate trench; sequentially forming a high dielectric constant (high-k) gate dielectric layer and a multiple metal layer on the substrate; forming a first work function metal layer in the first gate trench; performing a first pull back step to remove a portion of the first work function metal layer from the first gate trench; forming a second work function metal layer in the first gate trench and the second gate trench; and performing a second pull back step to remove a portion of the second work function metal layer from the first gate trench and the second gate trench.
    Type: Grant
    Filed: December 15, 2011
    Date of Patent: March 11, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Ssu-I Fu, Wen-Tai Chiang, Ying-Tsung Chen, Shih-Hung Tsai, Chien-Ting Lin, Chi-Mao Hsu, Chin-Fu Lin
  • Patent number: 8664057
    Abstract: When forming high-k metal gate electrode structures in transistors of different conductivity type while also incorporating an embedded strain-inducing semiconductor alloy selectively in one type of transistor, superior process uniformity may be accomplished by selectively reducing the thickness of a dielectric cap material of a gate layer stack above the active region of transistors which do not receive the strain-inducing semiconductor alloy. In this case, superior confinement and thus integrity of sensitive gate materials may be accomplished in process strategies in which the sophisticated high-k metal gate electrode structures are formed in an early manufacturing stage, while, in a replacement gate approach, superior process uniformity is achieved upon exposing the surface of a placeholder electrode material.
    Type: Grant
    Filed: August 3, 2012
    Date of Patent: March 4, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Rohit Pal, Sven Beyer, Andy Wei, Richard Carter
  • Patent number: 8664058
    Abstract: A method of fabricating an integrated circuit and an integrated circuit having silicon on a stress liner are disclosed. In one embodiment, the method comprises providing a semiconductor substrate comprising an embedded disposable layer, and removing at least a portion of the disposable layer to form a void within the substrate. This method further comprises depositing a material in that void to form a stress liner, and forming a transistor on an outside semiconductor layer of the substrate. This semiconductor layer separates the transistor from the stress liner. In one embodiment, the substrate includes isolation regions; and the removing includes forming recesses in the isolation regions, and removing at least a portion of the disposable layer via these recesses. In one embodiment, the depositing includes depositing a material in the void via the recesses. End caps may be formed in the recesses at ends of the stress liner.
    Type: Grant
    Filed: February 13, 2013
    Date of Patent: March 4, 2014
    Assignee: International Business Machines Corporation
    Inventors: Stephen W. Bedell, Josephine B. Chang, Chung-Hsun Lin
  • Patent number: 8664055
    Abstract: A fin field-effect transistor structure includes a substrate, a fin channel and a high-k metal gate. The high-k metal gate is formed on the substrate and the fin channel. A process of manufacturing the fin field-effect transistor structure includes the following steps. Firstly, a polysilicon pseudo gate structure is formed on the substrate and a surface of the fin channel. By using the polysilicon pseudo gate structure as a mask, a source/drain region is formed in the fin channel. After the polysilicon pseudo gate structure is removed, a high-k dielectric layer and a metal gate layer are successively formed. Afterwards, a planarization process is performed on the substrate having the metal gate layer until the first dielectric layer is exposed, so that a high-k metal gate is produced.
    Type: Grant
    Filed: December 3, 2012
    Date of Patent: March 4, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Teng-Chun Tsai, Chun-Yuan Wu, Chin-Fu Lin, Chih-Chien Liu, Chin-Cheng Chien
  • Patent number: 8658488
    Abstract: A graphene layer is provided onto at least an upper surface of a first dielectric material which includes at least one first conductive region contained therein. At least one semiconductor device is formed using the graphene layer as an element of the at least one semiconductor device. After forming the at least one semiconductor device, a second dielectric material is formed covering the graphene layer, the at least one semiconductor device, and portions of the first dielectric material. The second dielectric that is formed includes at least one second conductive region contained therein, and the at least one second conductive region is in contact with a conductive element of the at least one semiconductor device.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: February 25, 2014
    Assignee: International Business Machines Corporation
    Inventors: Christos D. Dimitrakopoulos, Guy Cohen, Stephen M. Gates, Alfred Grill, Timothy J. McArdle, Chun-yung Sung
  • Patent number: 8658487
    Abstract: A method for fabricating a semiconductor device comprises steps as follows: A first dummy gate having a first high-k gate insulator layer, a first composite sacrificial layer, and a first dummy gate electrode sequentially stacked on a substrate is firstly provided. The first dummy gate electrode is subsequently removed to expose the first composite sacrificial layer. The first composite sacrificial layer is then removed. Thereafter, a first work function layer is formed on the first high-k gate insulator layer, and a first metal gate electrode is formed on the first work function layer.
    Type: Grant
    Filed: November 17, 2011
    Date of Patent: February 25, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Duan-Quan Liao, Shih-Chieh Hsu, Yi-Kun Chen, Ching-Hwa Tey
  • Patent number: 8658489
    Abstract: A CMOS device having an NMOS transistor with a metal gate electrode comprising a mid-gap metal with a low work function/high oxygen affinity cap and a PMOS transistor with a metal gate electrode comprising a mid gap metal with a high work function/low oxygen affinity cap and method of forming.
    Type: Grant
    Filed: August 15, 2013
    Date of Patent: February 25, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: James Joseph Chambers, Hiroaki Niimi
  • Patent number: 8658491
    Abstract: A semiconductor device and a method for manufacturing the same are disclosed. The disclosed semiconductor device includes a semiconductor substrate having a device isolation structure for delimiting an active region, the active region being recessed and grooves being defined in channel forming areas of the active region; gates formed in and over the grooves; gate spacers formed on both sidewalls of the gates over portions of the recessed active region which are positioned on both sides of the gates; an LDD region formed in the active region under the gate spacers; junction areas formed in the active region on both sides of the gates including the gate spacers; and landing plugs formed on the junction areas.
    Type: Grant
    Filed: September 27, 2010
    Date of Patent: February 25, 2014
    Assignee: Hynix Semiconductor Inc.
    Inventor: Gyu Seog Cho
  • Publication number: 20140048887
    Abstract: An integrated circuit having improved radiation immunity is described. The integrated circuit comprises a substrate; an n-well formed on the substrate; a p-well formed on the substrate; and a p-tap formed in the p-well adjacent to the n-well, wherein the p-tap extends between circuit elements formed in the n-well and circuit elements formed in the p-well, and is coupled to a ground potential. A method of forming an integrated circuit having improved radiation immunity is also described.
    Type: Application
    Filed: August 16, 2012
    Publication date: February 20, 2014
    Applicant: XILINX, INC.
    Inventors: Michael J. Hart, James Karp
  • Patent number: 8653602
    Abstract: A transistor is fabricated by removing a polysilicon gate over a doped region of a substrate and forming a mask layer over the substrate such that the doped region is exposed through a hole within the mask layer. An interfacial layer is deposited on top and side surfaces of the mask layer and on a top surface of the doped region. A layer adapted to reduce a threshold voltage of the transistor and/or reduce a thickness of an inversion layer of the transistor is deposited on the interfacial layer. The layer includes metal, such as aluminum or lanthanum, which diffuses into the interfacial layer, and also includes oxide, such as hafnium oxide. A conductive plug, such as a metal plug, is formed within the hole of the mask layer. The interfacial layer, the layer on the interfacial layer, and the conductive plug are a replacement gate of the transistor.
    Type: Grant
    Filed: September 11, 2010
    Date of Patent: February 18, 2014
    Assignee: International Business Machines Corporation
    Inventors: Dechao Guo, Keith Kwong Hon Wong
  • Patent number: 8653604
    Abstract: Multiple transistor types are formed in a common epitaxial layer by differential out-diffusion from a doped underlayer. Differential out-diffusion affects the thickness of a FET channel, the doping concentration in the FET channel, and distance between the gate dielectric layer and the doped underlayer. Differential out-diffusion may be achieved by differentially applying a dopant migration suppressor such as carbon; differentially doping the underlayer with two or more dopants having the same conductivity type but different diffusivities; and/or differentially applying thermal energy.
    Type: Grant
    Filed: September 21, 2012
    Date of Patent: February 18, 2014
    Assignee: SuVolta, Inc.
    Inventors: Thomas Hoffmann, Pushkar Ranade, Lucian Shifren, Scott E. Thompson
  • Patent number: 8652895
    Abstract: A memory cell of an SRAM has two drive MISFETs and two vertical MISFETs. The p channel vertical MISFETs are formed above the n channel drive MISFETs. The vertical MISFETs respectively mainly include a laminate formed of a lower semiconductor layer, intermediate semiconductor layer and upper semiconductor layer laminated in this sequence, a gate insulating film of silicon oxide formed on the surface of the side wall of the laminate, and a gate electrode formed so as to cover the side wall of the laminate. The vertical MISFETs are perfect depletion type MISFETs.
    Type: Grant
    Filed: July 5, 2011
    Date of Patent: February 18, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Masahiro Moniwa, Hiraku Chakihara, Kousuke Okuyama, Yasuhiko Takahashi
  • Patent number: 8652887
    Abstract: The present invention relates to a method for providing a Silicon-On-Insulator (SOI) stack that includes a substrate layer, a first oxide layer on the substrate layer and a silicon layer on the first oxide layer (BOX layer). The method includes providing at least one first region of the SOI stack wherein the silicon layer is thinned by thermally oxidizing a part of the silicon layer and providing at least one second region of the SOI stack wherein the first oxide layer (BOX layer) is thinned by annealing.
    Type: Grant
    Filed: March 9, 2012
    Date of Patent: February 18, 2014
    Assignee: Soitec
    Inventors: Bich-Yen Nguyen, Carlos Mazure, Richard Ferrant
  • Patent number: 8652896
    Abstract: A SRAM includes a first CMOS inverter of first and second MOS transistors connected in series, a second CMOS inverter of third and fourth MOS transistors connected in series and forming a flip-flop circuit together with the first CMOS inverter, and a polysilicon resistance element formed on a device isolation region, each of the first and third MOS transistors is formed in a device region of a first conductivity type and includes a second conductivity type drain region at an outer side of a sidewall insulation film of the gate electrode with a larger depth than a drain extension region thereof, wherein a source region is formed deeper than a drain extension region, the polysilicon gate electrode has a film thickness identical to a film thickness of the polysilicon resistance element, the source region and the polysilicon resistance element are doped with the same dopant element.
    Type: Grant
    Filed: December 26, 2012
    Date of Patent: February 18, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Makoto Yasuda
  • Patent number: 8647939
    Abstract: A method of forming a field effect transistor (FET) device includes forming a patterned gate structure over a substrate; forming a solid source dopant material on the substrate, adjacent sidewall spacers of the gate structure; performing an anneal process at a temperature sufficient to cause dopants from the solid source dopant material to diffuse within the substrate beneath the gate structure and form source/drain extension regions; following formation of the source/drain extension regions, forming trenches in the substrate adjacent the sidewall spacers, corresponding to source/drain regions; and forming an embedded semiconductor material in the trenches so as to provide a stress on a channel region of the substrate defined beneath the gate structure.
    Type: Grant
    Filed: August 20, 2013
    Date of Patent: February 11, 2014
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Bruce B. Doris, Pranita Kerber, Ali Khakifirooz, Douglas C. La Tulipe, Jr.
  • Publication number: 20140035059
    Abstract: Semiconductor devices having metallic source and drain regions are described. For example, a semiconductor device includes a gate electrode stack disposed above a semiconducting channel region of a substrate. Metallic source and drain regions are disposed above the substrate, on either side of the semiconducting channel region. Each of the metallic source and drain regions has a profile. A first semiconducting out-diffusion region is disposed in the substrate, between the semiconducting channel region and the metallic source region, and conformal with the profile of the metallic source region. A second semiconducting out-diffusion region is disposed in the substrate, between the semiconducting channel region and the metallic drain region, and conformal with the profile of the metallic drain region.
    Type: Application
    Filed: December 19, 2011
    Publication date: February 6, 2014
    Inventors: Martin D. Giles, Annalisa Cappellani, Sanaz Kabehie, Rafael Rios, Cory E. Weber, Aaron A. Budrevich
  • Publication number: 20140035062
    Abstract: A transistor device is provided that includes a substrate, a first channel region formed in a first portion of the substrate and being doped with a dopant of a first type of conductivity, a second channel region formed in a second portion of the substrate and being doped with a dopant of a second type of conductivity, a gate insulating layer formed on the first channel region and on the second channel region, a dielectric capping layer formed on the gate insulating layer, a first gate region formed on the dielectric capping layer over the first channel region, and a second gate region formed on the dielectric capping layer over the second channel region, wherein the first gate region and the second gate region are made of the same material, and wherein one of the first gate region and the second gate region comprises an ion implantation.
    Type: Application
    Filed: October 23, 2013
    Publication date: February 6, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jacob C. Hooker, Markus Mueller
  • Patent number: 8642417
    Abstract: A method includes forming a gate structure over a semiconductor substrate. The gate structure defines a channel region in the semiconductor substrate. Trenches are formed in the semiconductor substrate, and the trenches are interposed by the channel region. A first semiconductor layer is epitaxially grown in the trenches, and the first semiconductor layer has a first dopant with a first dopant concentration. A second semiconductor layer is epitaxially grown over the first semiconductor layer, and the second semiconductor layer has a second dopant with a second dopant concentration. The second dopant has an electrical carrier type opposite to an electrical carrier type of the first dopant.
    Type: Grant
    Filed: June 18, 2013
    Date of Patent: February 4, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Fai Cheng, Li-Ping Huang, Ka-Hing Fung
  • Patent number: 8642418
    Abstract: A method of manufacturing a semiconductor device with NMOS and PMOS transistors is provided. The semiconductor device can lessen a short channel effect, can reduce gate-drain current leakage, and can reduce parasitic capacitance due to gate overlaps, thereby inhibiting a reduction in the operating speed of circuits. An N-type impurity such as arsenic is ion implanted to a relatively low concentration in the surface of a silicon substrate (1) in a low-voltage NMOS region (LNR) thereby to form extension layers (61). Then, a silicon oxide film (OX2) is formed to cover the whole surface of the silicon substrate (1). The silicon oxide film (OX2) on the side surfaces of gate electrodes (51-54) is used as an offset sidewall. Then, boron is ion implanted to a relatively low concentration in the surface of the silicon substrate (1) in a low-voltage PMOS region (LPR) thereby to form P-type impurity layers (621) later to be extension layers (62).
    Type: Grant
    Filed: August 12, 2013
    Date of Patent: February 4, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Kazunobu Ota, Hirokazu Sayama, Hidekazu Oda
  • Patent number: 8642415
    Abstract: A method of creating a semiconductor integrated circuit is disclosed. The method includes forming a first field effect transistor (FET) device and a second FET device on a semiconductor substrate. The method includes epitaxially growing raised source/drain (RSD) structures for the first FET device at a first height. The method includes epitaxially growing raised source/drain (RSD) structures for the second FET device at a second height. The second height is greater than the first height such that a threshold voltage of the second FET device is greater than a threshold voltage of the first FET device.
    Type: Grant
    Filed: June 4, 2012
    Date of Patent: February 4, 2014
    Assignee: International Business Machines Corporation
    Inventors: Thomas N. Adam, Kangguo Cheng, Bruce B. Doris, Balasubramanian S. Haran, Pranita Kulkarni, Alexander Reznicek
  • Patent number: 8642426
    Abstract: It is an object to allow an inverter to be made up using a single island-shaped semiconductor, so as to provide a semiconductor device comprising a highly-integrated SGT-based CMOS inverter circuit.
    Type: Grant
    Filed: June 27, 2012
    Date of Patent: February 4, 2014
    Assignee: Unisantis Electronics Singapore Pte Ltd.
    Inventors: Fujio Masuoka, Hiroki Nakamura
  • Patent number: 8642416
    Abstract: A method for formation of a semiconductor device including a first wafer including a first single crystal layer comprising first transistors and first alignment mark, the method including: implanting to form a doped layer within a second wafer; forming a second mono-crystalline layer on top of the first wafer by transferring at least a portion of the doped layer using layer transfer step, and completing the formation of second transistors on the second mono-crystalline layer including a step of forming a gate dielectric followed by second transistors gate formation step, wherein the second transistors are horizontally oriented.
    Type: Grant
    Filed: June 28, 2011
    Date of Patent: February 4, 2014
    Assignee: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Deepak Sekar, Brian Cronquist, Ze'ev Wurman
  • Patent number: 8642435
    Abstract: A method includes forming a gate stack over a semiconductor substrate, wherein the gate stack includes a gate dielectric and a gate electrode over the gate dielectric. A portion of the semiconductor substrate adjacent to the gate stack is recessed to form a recess. A semiconductor region is epitaxially grown in the recess. The semiconductor region is implanted with a p-type impurity or an n-type impurity. A dry treatment is performed on the semiconductor region.
    Type: Grant
    Filed: January 13, 2012
    Date of Patent: February 4, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Che-Cheng Chang, Po-Chi Wu, Chang-Yin Chen, Zhe-Hao Zhang, Yi-Chen Huang
  • Patent number: 8643113
    Abstract: A process is disclosed of forming metal replacement gates for NMOS and PMOS transistors with oxygen in the PMOS metal gates and metal atom enrichment in the NMOS gates such that the PMOS gates have effective work functions above 4.85 eV and the NMOS gates have effective work functions below 4.25 eV. Metal work function layers in both the NMOS and PMOS gates are oxidized to increase their effective work functions to the desired PMOS range. An oxygen diffusion blocking layer is formed over the PMOS gate and an oxygen getter is formed over the NMOS gates. A getter anneal extracts the oxygen from the NMOS work function layers and adds metal atom enrichment to the NMOS work function layers, reducing their effective work functions to the desired NMOS range. Processes and materials for the metal work function layers, the oxidation process and oxygen gettering are disclosed.
    Type: Grant
    Filed: November 21, 2008
    Date of Patent: February 4, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: James Joseph Chambers, Hiroaki Niimi
  • Publication number: 20140030859
    Abstract: In some embodiments, a method for manufacturing forms a semiconductor device, such as a transistor. A dielectric stack is formed on a semiconductor substrate. The stack comprises a plurality of dielectric layers separated by one of a plurality of spacer layers. Each of the plurality of spacer layers is formed of a different material than immediately neighboring layers of the plurality of dielectric layers. A vertically-extending hole is formed through the plurality of dielectric layers and the plurality of spacer layers. The hole is filled by performing an epitaxial deposition, with the material filling the hole forming a wire. The wire is doped and three of the dielectric layers are sequentially removed and replaced with conductive material, thereby forming upper and lower contacts to the wire and a gate between the upper and lower contacts. The wire may function as a channel region for a transistor.
    Type: Application
    Filed: October 3, 2013
    Publication date: January 30, 2014
    Applicant: ASM IP Holding B.V.
    Inventors: Qi Xie, Vladimir Machkaoutsan, Jan Willem Maes
  • Patent number: 8637357
    Abstract: A CMOS device with transistors having different gate dielectric materials and a method of manufacture thereof. A CMOS device is formed on a workpiece having a first region and a second region. A first gate dielectric material is deposited over the second region. A first gate material is deposited over the first gate dielectric material. A second gate dielectric material comprising a different material than the first gate dielectric material is deposited over the first region of the workpiece. A second gate material is deposited over the second gate dielectric material. The first gate material, the first gate dielectric material, the second gate material, and the second gate dielectric material are then patterned to form a CMOS device having a symmetric Vt for the PMOS and NMOS FETs.
    Type: Grant
    Filed: April 11, 2012
    Date of Patent: January 28, 2014
    Assignee: Infineon Technologies AG
    Inventor: Hong-Jyh Li
  • Publication number: 20140021556
    Abstract: An integrated circuit may be formed by removing source/drain spacers from offset spacers on sidewalls of MOS transistor gates, forming a contact etch stop layer (CESL) spacer layer on lateral surfaces of the MOS transistor gates, etching back the CESL spacer layer to form sloped CESL spacers on the lateral surfaces of the MOS transistor gates with heights of ¼ to ¾ of the MOS transistor gates, forming a CESL over the sloped CESL spacers, the MOS transistor gates and the intervening substrate, and forming a PMD layer over the CESL.
    Type: Application
    Filed: May 31, 2013
    Publication date: January 23, 2014
    Inventor: Tom Lii
  • Publication number: 20140021558
    Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a first doped region and a second doped region both formed in a substrate. The first and second doped regions are oppositely doped. The semiconductor device includes a first gate formed over the substrate. The first gate overlies a portion of the first doped region and a portion of the second doped region. The semiconductor device includes a second gate formed over the substrate. The second gate overlies a different portion of the second doped region. The semiconductor device includes a first voltage source that provides a first voltage to the second gate. The semiconductor device includes a second voltage source that provides a second voltage to the second doped region. The first and second voltages are different from each other.
    Type: Application
    Filed: September 25, 2013
    Publication date: January 23, 2014
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yung-Chih Tsai, Han-Chung Lin
  • Patent number: 8633480
    Abstract: An object of an embodiment of the present invention is to manufacture a semiconductor device with high display quality and high reliability, which includes a pixel portion and a driver circuit portion capable of high-speed operation over one substrate, using transistors having favorable electric characteristics and high reliability as switching elements. Two kinds of transistors, in each of which an oxide semiconductor layer including a crystalline region on one surface side is used as an active layer, are formed in a driver circuit portion and a pixel portion. Electric characteristics of the transistors can be selected by choosing the position of the gate electrode layer which determines the position of the channel. Thus, a semiconductor device including a driver circuit portion capable of high-speed operation and a pixel portion over one substrate can be manufactured.
    Type: Grant
    Filed: November 3, 2010
    Date of Patent: January 21, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama, Hiroyuki Miyake
  • Publication number: 20140015064
    Abstract: A method is provided for fabricating a CMOS device. The method includes providing a semiconductor substrate having a first active region and a second active region. The method also includes forming a first trench on the first active region using a first barrier layer and a second substitute gate electrode layer to protect a gate region on the second active region, followed by forming a first work function layer and a first metal gate in the first trench. Further, the method includes forming a second trench on the second active region using a second barrier layer to protect the first metal gate structure, followed by forming a second work function layer and a second metal gate in the second trench.
    Type: Application
    Filed: December 14, 2012
    Publication date: January 16, 2014
    Applicant: Semiconductor Manufacturing International Corp.
    Inventors: WEIHAI BU, WENBO WANG, SHAOFENG YU, HANMING WU
  • Patent number: 8629016
    Abstract: Multiple transistor types are formed in a common epitaxial layer by differential out-diffusion from a doped underlayer. Differential out-diffusion affects the thickness of a FET channel, the doping concentration in the FET channel, and distance between the gate dielectric layer and the doped underlayer. Differential out-diffusion may be achieved by differentially applying a dopant migration suppressor such as carbon; differentially doping the underlayer with two or more dopants having the same conductivity type but different diffusivities; and/or differentially applying thermal energy.
    Type: Grant
    Filed: April 30, 2012
    Date of Patent: January 14, 2014
    Assignee: SuVolta, Inc.
    Inventors: Thomas Hoffmann, Pushkar Ranade, Lucian Shifren, Scott E. Thompson
  • Patent number: 8629015
    Abstract: According to an aspect of the invention, a method is provided for manufacturing electronic components. A conducting element comprising a first portion, a second portion and a third portion between the first portion and the second portion is provided. Thermally responsive dielectric material is added at least onto the third portion of the conducting element. Electric current is supplied between the first portion and the second portion of the conducting element causing ohmic heating to affix dielectric material located on the third portion to the third portion. Non-thermally-affixed dielectric material is removed.
    Type: Grant
    Filed: July 3, 2009
    Date of Patent: January 14, 2014
    Assignee: Smartrac IP B.V.
    Inventors: Tomas Bäcklund, Kaisa Lilja, Timo Joutsenoja
  • Patent number: 8629021
    Abstract: A method for making an NMOS transistor on a semiconductor substrate includes reducing the thickness of the PMD layer to expose the polysilicon gate electrode of the NMOS transistor and the polysilicon gate electrode of the PMOS transistor, and then removing the gate electrode of the NMOS transistor. The method also includes depositing a NMOS-metal layer over the semiconductor substrate, depositing a fill-metal layer over the NMOS-metal layer, and then reducing the thickness of the NMOS metal layer and the fill metal layer to expose the gate electrodes of the NMOS transistor and the PMOS transistor.
    Type: Grant
    Filed: November 2, 2007
    Date of Patent: January 14, 2014
    Assignee: Texas Instruments Incorporated
    Inventor: Michael Francis Pas
  • Patent number: 8629014
    Abstract: A stack of a barrier metal layer and a first-type work function metal layer is deposited in replacement metal gate schemes. The barrier metal layer can be deposited directly on the gate dielectric layer. The first-type work function metal layer is patterned to be present only in regions of a first type field effect transistor. A second-type work function metal layer is deposited directly on the barrier metal layer in the regions of a second type field effect transistor. Alternately, the first-type work function layer can be deposited directly on the gate dielectric layer. The barrier metal layer is patterned to be present only in regions of a first type field effect transistor. A second-type work function metal layer is deposited directly on the gate dielectric layer in the regions of the second type field effect transistor. A conductive material fill and planarization form dual work function replacement gate structures.
    Type: Grant
    Filed: September 20, 2010
    Date of Patent: January 14, 2014
    Assignee: International Business Machines Corporation
    Inventors: Unoh Kwon, Michael P. Chudzik, Ravikumar Ramachandran
  • Patent number: 8629027
    Abstract: An asymmetric insulated-gate field-effect transistor (100 or 102) has a source (240 or 280) and a drain (242 or 282) laterally separated by a channel zone (244 or 284) of body material (180 or 182) of a semiconductor body. A gate electrode (262 or 302) overlies a gate dielectric layer (260 or 300) above the channel zone. A more heavily doped pocket portion (250 or 290) of the body material extends largely along only the source. The source has a main source portion (240M or 280M) and a more lightly doped lateral source extension (240E or 280E). The drain has a main portion (242M or 282M) and a more lightly doped lateral drain extension (242E or 282E). The drain extension is more lightly doped than the source extension. The maximum concentration of the semiconductor dopant defining the two extensions occurs deeper in the drain extension than in the source extension. Additionally or alternatively, the drain extension extends further laterally below the gate electrode than the source extension.
    Type: Grant
    Filed: April 4, 2011
    Date of Patent: January 14, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Constantin Bulucea, William D. French, Sandeep R. Bahl, Jeng-Jiun Yang, D. Courtney Parker, Peter B. Johnson, Donald M. Archer
  • Publication number: 20140008730
    Abstract: Disclosed are complementary metal-oxide-semiconductor (CMOS) devices and methods of manufacturing such CMOS devices. In some embodiments, an example CMOS device may include a substrate, and a buffer layer formed on the substrate, where the buffer layer comprises Si1-xGex, where x is less than 0.5. The example CMOS device may further include one or more pMOS channel layer elements, where each pMOS channel layer element comprises Si1-yGey, and where y is greater than x. The example CMOS device may still further include one or more nMOS channel layer elements, where each nMOS channel layer element comprises Si1-zGez, and where z is less than x. In some embodiments, the example CMOS device may be a fin field-effect transistor (FinFET) CMOS device and may further include a first fin structure including the pMOS channel layer element(s) and a second fin structure including the nMOS channel layer element(s).
    Type: Application
    Filed: July 3, 2013
    Publication date: January 9, 2014
    Applicant: IMEC
    Inventors: Jerome Mitard, Liesbeth Witters
  • Publication number: 20140001474
    Abstract: Various embodiments provide complementary metal-oxide-semiconductor (CMOS) devices and fabrication methods. An exemplary CMOS device can be formed by providing a first dummy gate over a semiconductor substrate in a first region, providing a second dummy gate over the semiconductor substrate in a second region, and amorphizing a surface portion of the first dummy gate to form a first amorphous silicon layer. The first amorphous silicon layer can be used to protect the first dummy gate in the first region, when a second opening is formed in the second region by wet etching at least the second dummy gate. A second metal gate can then be formed in the second opening, followed by removing the first amorphous silicon layer and at least the first dummy gate to form a first opening in the first region. A first metal gate can be formed in the first opening.
    Type: Application
    Filed: November 13, 2012
    Publication date: January 2, 2014
    Inventor: ZHONGSHAN HONG
  • Publication number: 20140003133
    Abstract: Roughly described, the cell layout in an SRAM array is re-arranged such that the gate electrodes for transistors for which flexibility to use one channel length is desired, are formed along a different track from those for transistors for which flexibility to use a different channel length is desired. Not only does such a re-arrangement permit optimization of device ratios, but also in certain implementations can also reduce, rather than increase, cell area. Specific example layouts are described. The invention also involves layout files, macrocells, lithographic masks and integrated circuit devices incorporating these principles, as well as fabrication methods.
    Type: Application
    Filed: June 27, 2013
    Publication date: January 2, 2014
    Applicant: Synopsys, Inc.
    Inventors: Xi-Wei Lin, Victor Moroz
  • Patent number: 8617968
    Abstract: A method of forming a semiconductor device that includes providing a first strained layer of a first composition semiconductor material over a dielectric layer. A first portion of the layer of the first composition semiconductor material is etched or implanted to form relaxed islands of the first composition semiconductor material. A second composition semiconductor material is epitaxially formed over the relaxed island of the first composition semiconductor material. The second composition semiconductor material is intermixed with the relaxed islands of the first composition semiconductor material to provide a second strained layer having a different strain than the first strained layer.
    Type: Grant
    Filed: June 18, 2012
    Date of Patent: December 31, 2013
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Bruce B. Doris, Pouya Hashemi, Ali Khakifirooz
  • Patent number: 8617991
    Abstract: A method of manufacturing a semiconductor device includes forming an interlayer dielectric film that has first and second trenches on first and second regions of a substrate, respectively, forming a first metal layer along a sidewall and a bottom surface of the first trench and along a top surface of the interlayer dielectric film in the first region, forming a second metal layer along a sidewall and a bottom surface of the second trench and along a top surface of the interlayer dielectric film in the second region, forming a first sacrificial layer pattern on the first metal layer such that the first sacrificial layer fills a portion of the first trench, forming a first electrode layer by etching the first metal layer and the second metal layer using the first sacrificial layer pattern, and removing the first sacrificial layer pattern.
    Type: Grant
    Filed: June 19, 2012
    Date of Patent: December 31, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-Chan Lee, Yoo-Jung Lee, Ki-Hyung Ko, Dae-Young Kwak, Seung-Jae Lee, Jae-Sung Hur, Sang-Bom Kang, Cheol Kim, Bo-Un Yoon
  • Patent number: 8617946
    Abstract: A method of forming an integrated circuit is provided. The method includes forming a gate electrode of an NMOS transistor over a substrate by a gate-first process. A gate electrode of a PMOS transistor is formed over the substrate by a gate-last process.
    Type: Grant
    Filed: July 29, 2010
    Date of Patent: December 31, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Shi Liu, Chen-Hua Yu
  • Patent number: 8617947
    Abstract: A method of manufacturing a semiconductor device includes forming a channel region, forming a buffer layer on the channel region, and heat-treating the channel region by using a gas containing halogen atoms.
    Type: Grant
    Filed: April 26, 2012
    Date of Patent: December 31, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jun-kyu Yang, Phil-ouk Nam, Ki-hyun Hwang, Jae-young Ahn, Han-mei Choi, Bi-o Kim