Abstract: The method of manufacturing a semiconductor device has the steps of: etching a semiconductor substrate to form an isolation trench by using as a mask a pattern including a first silicon nitride film and having a window; depositing a second silicon nitride film covering an inner surface of the isolation trench; forming a first silicon oxide film burying the isolation trench; etching and removing the first silicon oxide film in an upper region of the isolation trench; etching and removing the exposed second silicon nitride film; chemical-mechanical-polishing the second silicon oxide film; and etching and removing the exposed first silicon nitride film.

Abstract: A method of treating a dielectric surface portion of a semiconductor substrate, comprising the steps of: (a) providing a semiconductor substrate having a dielectric surface portion; and then (b) treating said dielectric surface portion with a coating reagent, the coating reagent comprising a reactive group coupled to a coordinating group, with the coordinating group having a metal bound thereto, so that the metal is deposited on the dielectric surface portion to produce a surface portion treated with a metal.

Abstract: Methods of fabricating semiconductor devices are disclosed. One example method includes forming a gate oxide and a gate electrode on a semiconductor substrate; performing a first ion implantation process for the formation of an LDD (lightly doped drain) region in the substrate; forming spacers on the sidewalls of the gate electrode; performing a second ion implantation process for the formation of a junction region in the substrate using the spacers as mask; forming a trench for device isolation by removing selectively the top portion of the substrate between the spacers; forming a sidewall oxide layer on the resulting substrate; forming a diffusion barrier on the sidewall oxide layer; depositing a gap filling insulation layer over the diffusion barrier; planarizing the gap filling insulating layer; and removing selectively some part of the gap filling insulation layer to form contact holes.

Abstract: A transistor, memory cell array and method of manufacturing a transistor are disclosed.

Abstract: A static random access memory (SRAM) cell structure is created in a three-dimensional format as a vertical stack of wired transistors. These transistors are fabricated from crystalline silicon, and supplemental wiring structure features are fabricated to comprise a circuit along the walls of a vertical pillar. The three-dimensional cell integrated circuit can be created by a single mask step. Various structural features and methods of fabrication are described in detail. Peripheral interface, a two pillar version and other supplemental techniques are also described.

Abstract: A method of depositing dielectric material into sub-micron spaces and resultant structures is provided. After a trench is etched in the surface of a wafer, an oxygen barrier is deposited into the trench. An expandable, oxidizable liner, preferably amorphous silicon, is then deposited. The trench is then filled with a spin-on dielectric (SOD) material. A densification process is then applied, whereby the SOD material contracts and the oxidizable liner expands. Preferably, the temperature is ramped up while oxidizing during at least part of the densification process. The resulting trench has a negligible vertical wet etch rate gradient and a negligible recess at the top of the trench.