Abstract: Methods of forming an improved shallow trench isolation (STI) region are disclosed. Several exemplary techniques are proposed for treating STI sidewalls to improve the silicon (Si) surface at the atomic level. Each of the exemplary methods creates a smooth STI sidewall surface, prior to performing oxidation, by reconstructing silicon atoms at the surface. The suggested STI region can be used in imager pixel cells or memory device applications.

Abstract: Methods of forming buried bit lines in a non-volatile memory device can include forming impurity regions in a substrate of a non-volatile memory device to provide immediately neighboring buried bit lines for the device and then forming a shallow trench isolation region in the substrate between the immediately neighboring buried bit lines to substantially equalize lengths of the immediately neighboring buried bit lines.

Abstract: A semiconductor device with a field ring in an edge pattern of a semiconductor body with a central cell area and with field plate discharge pattern. The edge pattern exhibits at least one horizontal field plate which is arranged with one end over the field ring and with its other end on insulating layers towards the edge of the semiconductor body. A first ring-shaped area of a type of conduction doped complementary to a drift section material exhibits a field ring effect. A second highly doped ring-shaped area which contacts the one end of the horizontal field plate and forms a pn junction with the first ring-shaped area and which is arranged within the first area exhibits a locally limited punch-through effect or a resistive contact to the drift section material.

Abstract: A memory structure including a substrate, a first dielectric layer, a first conducting layer, a second conducting layer, a second dielectric layer, a spacer and a doped region is provided. The substrate has a trench wherein. The first dielectric layer is disposed on the interior surface of the trench. The first conducting layer is disposed on the first dielectric layer of the lower portion of the trench. The second conducting layer is disposed above the first conducting layer and filling the trench. The second dielectric layer is disposed between the first conducting layer and the second conducting layer. The spacer is disposed between the first dielectric layer and the second conducting layer. The doped region is disposed in the substrate of a side of the trench.

Abstract: A method of manufacturing a transistor. In one embodiment, the method includes forming a gate electrode by defining a gate groove in the substrate. A plate-like portion is defined in each of the trenches at a position adjacent to the groove so that the two plate-like portions will be connected with the groove and the groove is disposed between two plate-like portions. In one embodiment, the two plate-like portions are defined by an etching process which selectively etches the isolating material of the isolation trenches with respect to the semiconductor substrate material. A gate insulating material is provided at an interface between the active area and the groove and the interface between the active area and the plate-like portions, and a gate electrode material is deposited so as to fill the groove and the two plate-like portions.

Abstract: A process for realizing an integrated electronic circuit makes it possible to obtain transistors with p-type conduction and transistors with n-type conduction, in respective active zones having crystal orientations adapted to each conduction type. In addition, each active zone is electrically insulated from a primary substrate of the circuit, so that the entire circuit is compatible with SOI technology.

Abstract: A method of fabricating an isolation layer in a semiconductor device includes forming a trench in a semiconductor substrate, depositing a high-density plasma (HDP) oxide layer partially filling the trench by supplying an HDP deposition source, etching an overhang generated while the HDP oxide layer is deposited using a fluorine-containing etching gas, depositing a liner HDP oxide layer on the HDP oxide layer by supplying an inert gas and an HDP deposition source such that fluorine (F) is trapped in the liner HDP oxide layer, performing an isotropic etching on an overhang portion of a side surface of the HDP oxide layer using the fluorine (F) trapped in the liner HDP oxide layer, and forming an HDP capping layer on the liner HDP oxide layer to fill a remaining portion of the trench.

Abstract: A semiconductor device includes a first insulating isolation film provided on a main surface of a semiconductor substrate, an active region surrounded by the first insulating isolation film, and a second insulating isolation film provided on the main surface of the semiconductor substrate, having a thickness smaller than that of the first insulating isolation film and separating the active region into a first active region and a second active region.

Abstract: A method of forming an integrated deep and shallow trench isolation structure comprises depositing a hard mask on a film stack having a plurality of layers formed on a substrate such that the hard mask is deposited on a furthermost layer from the substrate, imprinting a first pattern into the hard mask to define an open end of a first trench, imprinting a second pattern into the hard mask to define an open end of a second trench, and etching into the film stack the first trench to a first depth and the second trench to a second depth such that the first trench and the second trench each define a blind aperture in the surface of the film stack.

Abstract: A method of manufacturing a semiconductor device includes the steps of forming a trench on a semiconductor substrate to define a first and a second element regions; burying a first oxide film in the trench; forming a second oxide film on surfaces of the first and second element regions; performing a first ion doping using a first mask which is exposing a first region containing the first element region and a part of the first oxide; performing a second ion doping using a second mask which is exposing a second region containing the second element region and a part of the first oxide film; and removing the second oxide film formed in the first element region and the second element region by etching, and the first oxide film is selectively thinned using the first or second mask after performing the first or second ion doping.

Abstract: A shallow trench isolation well is formed to be very thin in a highly integrated semiconductor device. When critical dimension (CD) is small, it is difficult to reduce the width of the photosensitive layer pattern for forming a trench to no more than a predetermined value due to limitations on the photolithography process.

Abstract: A method for forming isolation structure for MOS transistor is disclosed, which includes forming a first photoresist layer over a sacrificed oxide layer of a semiconductor substrate, patterning the first photoresist layer to define a PMOS active region and a PMOS isolation region; implanting nitrogen ions into the PMOS isolation region through the sacrificed oxide layer by using the first photoresist layer as a mask; removing the first photoresist layer; forming a second photoresist layer over the sacrificed oxide layer, patterning the second photoresist layer to define a NMOS active region and a NMOS isolation region; implanting oxygen ions into the NMOS isolation region through the sacrificed oxide layer by using the second photoresist layer as a mask; removing the second photoresist layer and the sacrificed oxide layer; and annealing the semiconductor substrate to form isolation structures of PMOS and NMOS, respectively.

Abstract: Vertical device structures incorporating at least one nanotube and methods for fabricating such device structures by chemical vapor deposition. Each nanotube is grown by chemical vapor deposition catalyzed by a catalyst pad and encased in a coating of a dielectric material. Vertical field effect transistors may be fashioned by forming a gate electrode about the encased nanotubes such that the encased nanotubes extend vertically through the thickness of the gate electrode. Capacitors may be fashioned in which the encased nanotubes and the corresponding catalyst pad bearing the encased nanotubes forms one capacitor plate.

Abstract: Methods, methods of making, devices, and systems for image sensors that include isolation regions are disclosed. A semiconductor imager includes a pixel array and peripheral circuitry arranged on at least one side of the pixel array. Array devices are formed as part of the pixel array and periphery devices are formed in the periphery. Array isolation regions are disposed around at least a portion of at least some of the array devices and periphery isolation regions are disposed around at least a portion of at least some of the periphery devices. Within the semiconductor imager, the periphery isolation regions are configured differently from the array isolation regions. The semiconductor image sensor may be included in as part of an imaging system that includes a processor.

Abstract: The present disclosure provides an image sensor semiconductor device. A semiconductor substrate having a first-type conductivity is provided. A plurality of sensor elements is formed in the semiconductor substrate. An isolation feature is formed between the plurality of sensor elements. An ion implantation process is performed to form a doped region having the first-type conductivity substantially underlying the isolation feature using at least two different implant energy.

Abstract: Disclosed herein are embodiments of a semiconductor structure and an associated method of forming the semiconductor structure with shallow trench isolation structures having selectively adjusted reflectance and absorption characteristics in order to ensure uniform temperature changes across a wafer during a rapid thermal anneal and, thereby, limit variations in device performance. Also disclosed are embodiments of another semiconductor structure and an associated method of forming the semiconductor structure with devices having selectively adjusted reflectance and absorption characteristics in order to either selectively vary the performance of individual devices (e.g., to form devices with different threshold voltages (Vt) on the same wafer) and/or to selectively optimize the anneal temperature of individual devices (e.g., to ensure optimal activation temperatures for n-type and p-type dopants during anneals).

Abstract: A method of forming a monitor mark includes forming an insulating film on a semiconductor substrate, and forming a first repetitive line pattern group and a second repetitive line pattern group by patterning the insulating film on the semiconductor substrate, such that the first repetitive line pattern group and the second repetitive line pattern group face each other with a predetermined space therebetween.

Abstract: In a thin film forming step S1, a thin film, having carbon as a main component, is formed on at least one principal surface of a silicon substrate. In a thin film partial removal step S2, of the thin film, a thin film portion at a partial region on the one principal surface is removed. In a porous region forming step S3, the portion of the carbon thin film remaining after the removal of the thin film portion at the partial region in the previous thin film partial removal step S2 is used as a mask and the silicon substrate is anodized in an electrolytic solution containing hydrofluoric acid to selectively form a porous silicon region in a surrounding region including the partial region from which the thin film has been removed. In a remaining thin film portion removal step S4, the remaining portion of the thin film on the one principal surface of the silicon substrate is removed under the oxidizing atmosphere, and at the same time, at least a portion of the porous silicon region is oxidized.

Abstract: Disclosed are embodiments of a semiconductor structure and method of forming the structure with selectively adjusted reflectance and absorption characteristics in order to selectively control temperature changes during a rapid thermal anneal and, thereby, to selectively control variations in device performance and/or to selectively optimize the anneal temperature of such devices. Selectively controlling the temperature changes in different devices during a rapid thermal anneal is accomplished by selectively varying the isolation material thickness in different sections of a shallow trench isolation structures. Alternatively, it is accomplished by selectively varying the pattern of fill structures in different sections of a semiconductor wafer so that predetermined amounts of shallow trench isolation regions in the different sections are exposed.

Abstract: Formation of an electrostatic discharge (ESD) protection device having a desired breakdown voltage (BV) is disclosed. The breakdown voltage (BV) of the device can be set, at least in part, by varying the degree to which a surface junction between two doped areas is covered. This junction can be covered in one embodiment by a dielectric material and/or a semiconductor material. Moreover, a variable breakdown voltage can be established by concurrently forming, in a single process flow, multiple diodes that have different breakdown voltages, where the diodes are also formed concurrently with circuitry that is to be protected. To generate the variable or different breakdown voltages, respective edges of isolation regions can be extended to cover more of the surface junctions of different diodes. In this manner, a first diode can have a first breakdown voltage (BV1), a second diode can have a second breakdown voltage (BV2), a third diode can have a third breakdown voltage (BV3), etc.

Abstract: In a method of fabricating a semiconductor optical device, insulating structures for an alignment mark for use in electron beam exposure is formed on a primary surface of a first III-V semiconductor region. After forming the insulating structures, a second III-V semiconductor region is grown on the first III-V semiconductor region to form an epitaxial wafer. The height of the insulating structures is larger than thickness of the second III-V semiconductor region. After forming the second III-V semiconductor region, alignment for the electron beam exposure is performed. After the alignment, a resist is exposed to electron beam to form a resist mask. The resist mask has a pattern for a diffraction grating, and the resist is on the epitaxial wafer.

Abstract: An electronic device is formed by epitaxially growing a Si substrate on a Si layer of an SOI substrate in which the Si layer is deposited on a front surface of a substrate with an insulating layer interposed therebetween; forming an element on a front-surface side of the Si substrate; and forming a back-surface element aligned with respect to the element, on a back-surface side of the Si substrate after the substrate is etched. A mark is formed by etching and removing the Si layer and the insulating layer in a predetermined position of the SOI substrate. The element is formed using a concave part as a reference position. The concave part appears on the front surface of the Si substrate epitaxially grown on the mark. The back-surface element is formed using the mark as a reference position. The mark appears after the substrate is etched.

Abstract: A method for forming a shallow trench isolation (STI) of a semiconductor device comprises forming a nitride film pattern over a semiconductor substrate having a defined lower structure, etching a predetermined thickness of the semiconductor substrate using the nitride film pattern as a mask to form a trench having a vertical sidewall in a portion of the substrate predetermined to be a device isolation region, performing a plasma treatment process on the sidewall of the trench to form a plasma oxide film, forming an oxide film over the resulting structure to fill the trench, and performing a planarization process over the resulting structure.

Abstract: The present invention discloses a process of manufacturing an STI for avoiding bubble defects, in which, after the shallow trench is formed by etching, substance containing carbon or oxygen on the bottom of the shallow trench is removed, and then the process is continued to accomplish the STI. Alternatively, the removal of substance containing carbon or oxygen may be performed after the oxide liner and the silicon nitride liner are formed on the bottom surface of the shallow trench. The present invention also discloses a process of treating bottom surface of the shallow trench. After the bottom surface of the shallow trench is treated, the bubble defects due to the use of the silicon nitride liner can be avoided.

Abstract: A solid-state image pickup device includes an element isolation insulating film electrically isolating pixels on the surface of a well region; a first isolation diffusion layer electrically isolating the pixels under the element isolation insulating film; and a second isolation diffusion layer electrically isolating the pixels under the first isolation diffusion layer, wherein a charge accumulation region is disposed in the well region surrounded by the first and second isolation diffusion layers, the inner peripheral part of the first isolation diffusion layer forms a projecting region, an impurity having a conductivity type of the first isolation diffusion layer and an impurity having a conductivity type of the charge accumulation region are mixed in the projecting region, and a part of the charge accumulation region between the charge accumulation region and the second isolation diffusion layer is abutted or close to the second isolation diffusion layer under the projecting region.

Abstract: A method for forming a STI of a semiconductor device includes steps of sequentially forming a pad oxide film and a pad nitride film on the semiconductor device and carrying out a pattern process PR; etching the pad oxide film and the nitride film and carrying out a cleaning process; selectively growing epitaxial silicon; and carrying out liner oxidation on the epitaxial silicon and carrying out CMP so as to form an oxidation fill and STI.

Abstract: According to one embodiment of the disclosure, a method for passivating a circuit device generally includes providing a substrate having a substrate surface, forming an electrical component on the substrate surface, and coating the substrate surface and the electrical component with a first protective dielectric layer. The first protective dielectric layer is made of a generally moisture insoluble material having a moisture permeability less than 0.01 gram/meter2/day, a moisture absorption less than 0.04 percent, a dielectric constant less than 10, a dielectric loss less than 0.005, a breakdown voltage strength greater than 8 million volts/centimeter, a sheet resistivity greater than 1015 ohm-centimeter, and a defect density less than 0.5/centimeter2.

Abstract: A method of manufacturing a semiconductor wafer for dicing includes providing a semiconductor wafer including a substrate and a plurality of upper layers on the substrate that form a formation of die areas. The formation is arranged so that adjacent die areas are separated by a path for a dicing tool within each path, a pair of spaced apart lines is fabricated. Each line defines a dicing edge of a respective path and has at least one trench extending between a top surface of the wafer and the substrate. Each trench is filled with a stress absorbing material for reducing die tool induced stress on the die areas during dicing.

Abstract: A method for providing an isolation material, for example trench isolation for a semiconductor device, comprises forming a first dielectric such as silicon dioxide using an atomic layer deposition (ALD) process within a trench, partially etching the first dielectric, then forming a second dielectric such as a silicon dioxide using a high density plasma (HDP) deposition within the trench. The second dielectric provides desirable properties such as resistance to specific etches than the first dielectric, while the first dielectric fills high aspect ratio openings more easily than the second dielectric. Depositing the first dielectric results in a decreased trench aspect ratio which must be filled by the second dielectric.

Abstract: A semiconducting material that has all the advantages of prior art SOI substrates including, for example, low parasitic capacitance and leakage, without having floating body effects is provided. More specifically, the present invention provides a Semiconductor-on-Pores (SOP) material that includes a top semiconductor layer and a bottom semiconductor layer, wherein the semiconductor layers are separated in at least one region by a porous semiconductor material. Semiconductor structures including the SOP material as a substrate as well as a method of fabricating the SOP material are also provided. The method includes forming a p-type region with a first semiconductor layer, converting the p-type region to a porous semiconductor material, sealing the upper surface of the porous semiconductor material by annealing, and forming a second semiconductor layer atop the porous semiconductor material.

Abstract: A semiconductor device includes: a silicon substrate; a first trench formed on a surface portion of the silicon substrate to isolate a plurality of active regions from one another; a first element isolation layer embedded in the first trench; a plurality of selectively-grown silicon layers formed on the respective active regions; and a second element isolation layer embedded in a second trench defined by the top surface of the first element isolation layer and opposing side surfaces of adjacent two of the selectively-grown silicon layers.

Abstract: To improve the mechanical strength of a wafer comprising a low-k dielectric layer, the low-k dielectric layer is formed so as to have certain regions of low dielectric constant and the remainder having a higher mechanical strength. The higher-strength regions may have a relatively-higher value of dielectric constant. Selective ultraviolet curing of a dielectric material can be performed so as to expel a porogen from the region(s) desired to have low dielectric constant. A photomask, hardmask, or opaque resist, patterned so as to define the region(s) to have lower dielectric constant, is used to shield the remainder of the dielectric material from the ultraviolet radiation. Alternatively, a layer of dielectric material can be blanket cured to lower its dielectric constant, then non-critical regions thereof can be selectively over-cured whereby to produce regions of increased mechanical strength.

Abstract: A semiconductor device with a substrate includes a structure. The structure has a first part and a second part. At least one section of the edge of the first part of the structure is at an essential constant distance measured parallel to the substrate to a first section of an edge of a second structure. At least one section of the edge of the second part of the structure is lined with an edge of a second section of the same second section. The first section of the edge of the second structure and a second section of the edge of the second structure merge at least at one point, whereby the angle between the tangents of the edges of the first and second section of the second structure is less than 90°. The structure and the second structure are distanced by a spacer structure.

Abstract: In a method for forming a semiconductor device, a device isolation layer is formed in a capacitor region of a silicon substrate, and a bottom electrode and a dielectric layer are formed on the device isolation layer. Insulation sidewalls are formed on both sides of the bottom electrode. A top electrode is formed on the dielectric layer, and simultaneously a gate electrode is formed in a transistor region of the silicon substrate. Source/drain impurity regions are formed in the silicon substrate at both sides of the gate electrode.

Abstract: One or more local oxidation of silicon (LOCOS) regions may be formed that apply compressive strain to a channel of a field-effect transistor such as a P-type field-effect transistor (PFET) or other circuit element of a semiconductor device. For instance, a pair of LOCOS regions may be formed on opposite sides of a PFET gate and its corresponding channel, or one or more LOCOS regions may more fully surround, or even completely surround, the PFET channel. In addition, one or more slits may be formed in the LOCOS regions as appropriate to reduce or even completely neutralize the compressive strain in certain directions that would otherwise be applied without the slits. These techniques may be used in silicon-on-insulator (SOI) wafers with or without hybrid orientation technology (HOT) regions.

Abstract: A method for forming a substrate contact on a silicon-on-insulator (SOI) wafer is provided that can be integrated with a process for fabricating SOI devices without additional processing after wafer dicing. The method is applicable in many of the more advanced packaging technologies, e.g., such as flip chip and die stacking, directly creating a contact to silicon substrate via the front of the diced SOI wafer.

Abstract: This invention provides a hybrid orientation (HOT) semiconductor-on-insulator (SOI) structure having an isolation region, e.g. a shallow trench isolation region (STI), and a method for forming the STI structure that is easy to control. The method of forming the isolation region includes an etch of the insulating material, selective to the semiconductor material, followed by an etch of the semiconductor material, selective to the insulating material, and then filling any high aspect ratio gaps with a CVD oxide, and filling the remainder of the STI with an HDP oxide.

Abstract: The invention includes methods of forming recessed access devices. A substrate is provided to have recessed access device trenches therein. A pair of the recessed access device trenches are adjacent one another. Electrically conductive material is formed within the recessed access device trenches, and source/drain regions are formed proximate the electrically conductive material. The electrically conductive material and source/drain regions together are incorporated into a pair of adjacent recessed access devices. After the recessed access device trenches are formed within the substrate, an isolation region trench is formed between the adjacent recessed access devices and filled with electrically insulative material to form a trenched isolation region.

Abstract: Disclosed is a method for manufacturing a semiconductor device. The method includes the steps of forming an insulating layer on a substrate, partially exposing the substrate by selectively etching the insulating layer, implanting ions into the exposed substrate using the etched insulating layer as an ion implantation mask, and removing the etched insulating layer from the ion-implanted substrate.

Abstract: One embodiment of the present invention relates to a method of forming an isolation structure. During this method, an isolation trench is formed within a semiconductor body. After this trench is formed, it is filled by performing multiple high-frequency plasma depositions to deposit multiple dielectric layers over the semiconductor body. A first of the multiple layers is deposited at a high-frequency power of between approximately 100 watts and approximately 900 watts.

Abstract: A method for forming a trench isolation in a semiconductor device is provided. This is a novel method for rounding the top corners of trench isolations. The method ensures that rounded corner portions with a uniform shape are consistently formed regardless of the pattern densities of active areas. The method increases the reliability of semiconductor integrated circuit devices, without degrading electrical characteristics, and making it easier to achieve high integration and performance in semiconductor integrated circuit devices.

Abstract: A method of forming a semiconductor device can include forming a trench in a semiconductor substrate to define an active region. The trench is filled with a first device isolation layer. A portion of the first device isolation layer is etched to recess a top surface of the first device isolation layer below an adjacent top surface of the active region of the semiconductor substrate and to partially expose a sidewall of the active region. The exposed sidewall of the active region is epitaxially grown to form an extension portion of the active region that extends partially across the top surface of the first device isolation layer in the trench. A second device isolation layer is formed on the recessed first device isolation layer in the trench. The second device isolation layer is etched to expose a top surface of the extension portion of the active region and leave a portion of the second device isolation layer between extension portions of active regions on opposite sides of the trench.

Abstract: A method for aligning a first set of features of a fabrication level of an integrated circuit chip to an electron beam alignment target including a high atomic weight layer formed in a substrate and forming the first set of features using electron beam lithography and for aligning a second set of features of the same fabrication level of the integrated circuit chip to an optical alignment target formed in the substrate and forming the second set of features using photolithography, the optical alignment target itself is aligned to the electron beam alignment target. Also a method of forming and a structure of the electron beam alignment target.

Abstract: A method of forming a device isolation film for a semiconductor device comprising forming a trench on a silicon semiconductor substrate, rounding an upper corner of the trench using an in-situ plasma method, filling the trench by forming an insulating layer over the silicon semiconductor substrate, and forming a shallow trench isolation area by performing a planarization process on the insulating layer so as to expose the silicon semiconductor substrate.

Abstract: A method of forming a device isolation film of a semiconductor device is provided. The method of forming a device isolation film of a semiconductor device according to an embodiment includes forming the device isolation film by ion-implanting insulation materials inside of a trench formed on a semiconductor substrate.

Abstract: In a method of producing a semiconductor device, semiconductor burrs (74) are removed by dry etching using an etching gas in which a lateral-direction etch rate (R2) is greater than a depth-direction etch rate (R1) (that is, R1/R2 is smaller than 1) in a section of a groove (72) in a direction parallel to word lines.

Abstract: The invention provides methods for forming isolation structures and STI trenches in a semiconductor device, which may be carried out in a variety of semiconductor manufacturing processes. One embodiment of the invention relates to a method of forming a semiconductor device having isolation structures. In this method, trench regions are formed within a semiconductor body, and then surfaces of the trench regions are nitrided. Then the nitrided surfaces are subjected to a condition that limits nitrogen desorption from the nitrided surfaces. The nitrided surfaces of the trench regions are then oxidized to form nitrogen containing liners, after which the isolation trench is filled with a dielectric material. Other methods and systems are also disclosed.

Abstract: A method of indexing a plurality of dice obtained from a material wafer comprising a plurality of stacked material layers, each die being obtained in a respective die position in the wafer, the method including providing a visible index on each die indicative of the respective die position, wherein providing the visible index on each die includes: forming in a first material layer of the die a reference structure adapted to defining a mapping of the wafer; and forming in a second material layer of the die a marker associated with the reference structure, a position of the marker with respect to the reference structure being adapted to provide an indication of the die position in the wafer.

Abstract: A first example embodiment comprises the following steps and the structure formed therefrom. A trench having opposing sidewalls is formed within a substrate. A stress layer having an inherent stress is formed over the opposing trench sidewalls. The stress layer having stress layer sidewalls over the trench sidewalls. Ions are implanted into one or more portions of the stress layer to form ion-implanted relaxed portions with the portions of the stress layer that are not implanted are un-implanted portions, whereby the inherent stress of the one or more ion-implanted relaxed portions of stress layer portions is relaxed.

Abstract: A method of a semiconductor device comprises: a) depositing a first semiconductor layer and a second semiconductor layer in a semiconductor substrate in series; b) forming a first groove penetrating the first and second semiconductor layers and placed adjacent to an element region by partly etching the first and second semiconductor layers; c) forming a supporting member that supports the second semiconductor layer and covers over the second semiconductor layer and is embedded into the first groove; d) forming a second groove that exposes the first semiconductor layer from the bottom of the second semiconductor layer supported by the supporting member and is placed near the element region; and e) forming a cavity between the semiconductor substrate and the second semiconductor layer in the element region by etching the first semiconductor layer via the second groove under a specific condition in which the first semiconductor layer is easily etched, compared to the second semiconductor layer.