Abstract: A method for making STI structure includes etching a STI trench through a nitride layer, through an oxide layer, and into a silicon layer. The method also includes forming a sacrificial liner, pulling-back the nitride layer, and removing a remaining portion of the sacrificial liner. Furthermore, the method includes forming a STI liner and forming a STI fill coupled to the STI liner.

Abstract: A method of forming an isolation structure, comprising: (a) providing a base having a recess; (b) forming a stop layer on the base and in the recess; (c) forming a dielectric material on the stop layer so as to allow the rest of the recess to be filled with the dielectric material; (d) removing the dielectric material over the base by performing a chemical mechanical polishing (CMP) process until a part of the stop layer is exposed so as to form a dielectric layer in the recess; and (e) removing a part of the stop layer, wherein the another part of the stop layer and the dielectric layer filled in the recess constitute the isolation structure.

Abstract: A method of preparing active silicon regions for CMOS devices includes providing a structure including a silicon substrate (210, 410) having formed thereon first and second silicon diffusion lines (110, 420), both of which include first and second silicon layers (211, 213, 421, 423), a silicon germanium layer (212, 422), and an electrically insulating layer (214, 424). The method further includes forming an oxide layer (430) in first and second regions of the structure, forming a polysilicon layer (510) over the oxide layer, removing the polysilicon layer from the first region and depositing oxide (610) therein in order to form an oxide anchor, removing the polysilicon layer from the second region, removing the silicon germanium layer, filling the first and second gaps with an electrically insulating material (910), and depositing oxide in the second region.

Abstract: A method of forming isolation layer in a semiconductor device, comprising forming a trench on an isolation region of a semiconductor substrate by etching utilizing an isolation mask; forming a first insulating layer on a lower portion of the trench; forming a second insulating layer on the semiconductor substrate including the first insulating layer; etching the second insulating layer to increase an aspect ratio on the isolation region; and forming a third insulating layer on a peripheral region of the second insulating layer to fill moats formed on the second insulating layer with the third insulating layer.

Abstract: A method of manufacturing a test pattern for a semiconductor device includes the steps of forming, on a semiconductor substrate, a moat mask pattern including plural moat lines patterned in a comb-shape and etching a portion of the semiconductor substrate exposed by the moat mask pattern, to form a trench. The method further includes gap-filling the trench with an insulation material to form a field separator, planarizing the semiconductor substrate having the field separator formed thereon, and forming a poly comb pattern on the planarized semiconductor substrate. The poly comb pattern is formed such that the moat lines are arranged between lines of the poly comb pattern.

Abstract: A method for manufacturing a semiconductor device that can prevent the loss of an isolation structure and that can also stably form epi-silicon layers is described. The method for manufacturing a semiconductor device includes defining trenches in a semiconductor substrate having active regions and isolation regions. The trenches are partially filled with a first insulation layer. An etch protection layer is formed on the surfaces of the trenches that are filled with the first insulation layer. A second insulation layer is filled in the trenches formed with the etch protection layer to form an isolation structure in the isolation regions of the semiconductor substrate. Finally, portions of the active regions of the semiconductor substrate are recessed such that the isolation structure has a height higher than the active regions of the semiconductor substrate.

Abstract: Provided is a method that includes forming a first semiconductor layer on a semiconductor substrate, growing a second semiconductor layer on the first semiconductor layer, forming composite shapes on the first semiconductor layer, each composite shape comprising of an overlying oxide-resistant shape and an underlying second semiconductor shape, with portions of the first semiconductor layer exposed between the composite shapes, forming spacers on sides of the composite shapes, forming buried silicon oxide regions in exposed top portions of the first semiconductor layer, and in portions of the first semiconductor layer located underlying second semiconductor shapes, selectively removing the oxide-resistant shapes and spacers resulting in the second semiconductor shapes, and forming a semiconductor device in a second semiconductor shape wherein a first portion of the semiconductor device overlays the first semiconductor layer and wherein second portions of the semiconductor device overlays a buried silicon oxid

Abstract: A method of forming trench isolation includes etching first trench lines into semiconductive material of a semiconductor substrate. First isolation material is formed within the first trench lines within the semiconductive material. After forming the first isolation material within the first trench lines, second trench lines are etched into semiconductive material of the substrate between the first trench lines such that the first trench lines and second trench lines alternate. Second isolation material is formed within the second trench lines within the semiconductive material. Alternate and additional aspects are contemplated.

Abstract: A substrate comprising a trench lateral epitaxial overgrowth structure including a trench cavity, wherein the trench cavity includes a growth-blocking layer or patterned material supportive of a coalescent Pendeo layer thereon, on at least a portion of an inside surface of the trench. Such substrate is suitable for carrying out lateral epitaxial overgrowth to form a bridged lateral overgrowth formation overlying the trench cavity. The bridged lateral overgrowth formation provides a substrate surface on which epitaxial layers can be grown in the fabrication of microelectronic devices such as laser diodes, high electron mobility transistors, ultraviolet light emitting diodes, and other devices in which low dislocation density is critical. The epitaxial substrate structures of the invention can be formed without the necessity for deep trenches, such as are required in conventional Pendeo epitaxial overgrowth structures.

Abstract: In various embodiments, semiconductor structures and methods to manufacture these structures are disclosed. In one embodiment, a method to form a semiconductor structure includes removing a portion of a semiconductor material to form one or more suspended structures and a cavity, the cavity having a boundary that is below a surface of the semiconductor material and wherein the one or more suspended structures extend from the surface into the cavity. The method further includes altering the one or more suspended structures to form one or more altered suspended structures and forming a material over the one or more altered suspended structures and in a region between the one or more altered suspended structures. Other embodiments are described and claimed.

Abstract: A method of forming a semiconductor device includes forming line patterns on a substrate, the line patterns defining narrow and wide gap regions, forming spacer patterns in the narrow and wide gap regions on sidewalls of the line patterns, spacer patterns in the wide gap regions exposing an upper surface of the substrate, and spacer patterns in the narrow gap regions contacting each other to fill the narrow gap regions, forming an insulating interlayer to cover the spacer patterns and the line patterns, forming at least one opening through the insulating interlayer, the opening including at least one contact hole selectively exposing the upper surface of the substrate in the wide gap region, the contact hole being formed by using the spacer patterns in the narrow gap region as an etching mask, and forming a conductive pattern to fill the opening.

Abstract: In various embodiments, semiconductor structures and methods to manufacture these structures are disclosed. In one embodiment, a method includes removing a portion of a semiconductor material to form a first protrusion and a cavity having a boundary that is below a surface of the semiconductor material, wherein the first protrusion extends from the boundary of the cavity. The method further includes forming a non-conformal material over a first portion of the first protrusion using an angled deposition of the non-conformal material, wherein the angle of deposition of the non-conformal material is non-perpendicular to the surface of the semiconductor material. Other embodiments are described and claimed.

Abstract: A nitride-based FET device that provides reduced electron trapping and gate current leakage. The device includes a relatively thick passivation layer to reduce traps caused by device processing and a thin passivation layer below the gate terminal to reduce gate current leakage. The device includes semiconductor device layers deposited on a substrate. A plurality of passivation layers are deposited on the semiconductor device layers, where at least two of the layers are made of a different dielectric material to provide an etch stop. One or more of the passivation layers can be removed using the interfaces between the layers as an etch stop so that the distance between the gate terminal and the semiconductor device layers can be tightly controlled, where the distance can be made very thin to increase device performance and reduce gate current leakage.

Abstract: Non-volatile memory cell structures are described that are formed by a method including forming a first oxide layer on a horizontal strained substrate, forming at least one first recess through the first oxide layer to the strained substrate, and forming at least one vertical epitaxial structure in the recess. A crystal lattice of the vertical epitaxial structure is aligned with a crystal lattice of the strained substrate.

Abstract: A method for forming a device isolation layer in a semiconductor substrate by destroying a lattice structure of the semiconductor substrate through a high-energy ion implantation process.

Abstract: A semiconductor device which has higher integration and is further reduced in thickness and size. A semiconductor device with high performance and low power consumption. A semiconductor element layer separated from a substrate by using a separation layer is stacked over a semiconductor element layer formed by using another substrate and covered with a flattened inorganic insulating layer. After separation of the semiconductor element layer in a top layer from the substrate, the separation layer is removed so that an inorganic insulating film formed under the semiconductor element layer is exposed. The flattened inorganic insulating layer and the inorganic insulating film are made to be in close contact and bonded to each other. In addition, a semiconductor layer included in the semiconductor element layer is a single crystal semiconductor layer which is separated from a semiconductor substrate and transferred to a formation substrate.

Abstract: A wafer comprises a multi-layer structure. The multi-layer structure includes a first device structure neighbouring an area for receiving alignment markers. A plurality of alignment markers extend into the multi-layer structure and are located within the area for receiving alignment markers. The plurality of alignment markers is arranged to prevent propagation of a crack, when occurring, beyond a material-dependent critical length in a part of the multi-layer structure corresponding to the area for receiving the alignment structure. The material-dependent critical length is associated with the part of the multi-layer structure.

Abstract: A method of manufacturing a metal-oxide-semiconductor (MOS) transistor device is disclosed. A gate dielectric layer is formed on an active area of a substrate. A gate electrode is patterned on the gate dielectric layer. The gate electrode has vertical sidewalls and a top surface. A liner is formed on the vertical sidewalls of the gate electrode. A nitride spacer is formed on the liner. An ion implanted is performed to form a source/drain region. After salicide process, an STI region that isolates the active area is recessed, thereby forming a step height at interface between the active area and the STI region. The nitride spacer is removed. A nitride cap layer that borders the liner is deposited. The nitride cap layer has a specific stress status.

Abstract: A semiconductor device includes: a semiconductor substrate; and an insulating layer formed on at least a main surface of the semiconductor substrate; wherein a contact hole is formed at the insulating layer so as to expose the main surface of the semiconductor substrate through the insulating layer so that a cross section of the contact hole parallel to the main surface of the semiconductor substrate is shaped rectangularly.

Abstract: An integrated circuit having memory cells and a method of manufacture is disclosed. One embodiment provides a switching active volume and a selection transistor coupled in series between a first electrode and a second electrode. The selection transistor is a vertical transistor for at least partially guiding a substantially vertical current flow. The second electrode includes a buried diffused ground plate formed in a substrate. A metal-containing region at least partially contacting the buried diffused ground plate is provided, the metal-containing region at least extending below the selection transistor.

Abstract: A structure includes a substrate comprising a region having a circuit or device which is sensitive to electrical noise. Additionally, the structure includes a first isolation structure extending through an entire thickness of the substrate and surrounding the region and a second isolation structure extending through the entire thickness of the substrate and surrounding the region.

Abstract: A semiconductor device according to an embodiment of the invention includes: a semiconductor substrate; a well, having a well contact connection region, formed in the semiconductor substrate; a transistor formed on the well; an isolation region formed between the transistor formed on the well, and the well contact connection region; and a silicide layer formed between a bottom surface of the isolation region, and the semiconductor substrate.

Abstract: A method for forming a semiconductor device, includes the steps of providing a substrate; forming a patterned stack on the substrate including a first dielectric layer on the substrate, a first conductive layer on the first dielectric layer and a mask layer on the first conductive layer, wherein a width of the mask layer is smaller than a width of the first conductive layer; forming a second dielectric layer on the sidewall of the patterned stack; forming a third dielectric layer on the substrate; forming a second conductive layer over the substrate; and removing the mask layer and a portion of the first conductive layer covered by the mask layer to form an opening so as to partially expose the first conductive layer.

Abstract: A method for fabricating a semiconductor device includes forming a device isolation structure on a semiconductor substrate to define an active region. A hard mask pattern defining a recess region is formed over the semiconductor substrate. The semiconductor substrate is selectively etched using the hard mask pattern to form a recess channel structure. The etching process for the semiconductor substrate is performed by two plasma etching methods under different etching conditions. The hard mask pattern is removed to expose the active region including the recess channel structure. A gate electrode is formed to fill the recess channel structure.

Abstract: The present invention provides a semiconductor device includes: an element isolation region configured to be formed in a semiconductor substrate; a P-type field effect transistor configured to be formed in a first element formation region of the semiconductor substrate for which isolation by the element isolation region is carried out; an N-type substrate region configured to be formed in the semiconductor substrate for which isolation by the element isolation region is carried out, arsenic being ion-implanted into the N-type substrate region; a nickel silicide layer configured to be formed on the N-type substrate region; a first insulating film configured to cover the P-type field effect transistor and have compressive stress; and a second insulating film configured to cover the N-type substrate region and have tensile stress or compressive stress lower than the compressive stress of the first insulating film.

Abstract: Methods for forming a contact hole in a semiconductor device are provided. An exposed portion of an isolation layer, which may be generated during a process of forming a borderless contact hole, can be covered with a material similar to that of the substrate.

Abstract: An integrated circuit system comprising: providing a substrate; forming a main feature using a first non-cross-junction assist feature over the substrate; forming the main feature using a second non-cross-junction assist feature, adjacent a location of the first non-cross-junction feature, over the substrate; and forming an integrated circuit having the substrate with the main feature thereover.

Abstract: An area where a lower electrode is in contact with a variable resistance material needs to be reduced in order to lower the power consumption of a variable resistance memory device. The present invention provides a method of producing a variable resistance memory element whereby the lower electrode can be more finely formed. The method of producing a semiconductor device according to the present invention includes forming a small opening by utilizing cubical expansion due to the oxidation of silicon. Thereby forming the lower electrode smaller than that can be formed by lithography techniques.

Abstract: A device isolation structure of semiconductor device includes a semiconductor substrate having a cell region, a low voltage region and a high voltage region defined therein. A cell trench isolation region is disposed in the cell region. A low voltage trench isolation region is disposed in the low voltage region and extends deeper into the substrate than the cell trench isolation region. A first high voltage trench isolation region is disposed in the high voltage region and extends deeper into the substrate than the low voltage trench isolation region. A second high voltage trench isolation region is disposed in the high voltage region and extends deeper into the substrate than the low voltage trench isolation region but shallower than the first high voltage trench isolation region.

Abstract: A semiconductor device is disclosed, which includes a semiconductor substrate including a device region and an isolation region having an isolation trench, a gate electrode formed on the device region through a gate insulating film, a first isolation insulating film formed in the isolation trench, the first isolation insulating film having a recess, a second isolation insulating film formed on the first isolation insulating film to be filled in the recess, the second isolation insulating film having an upper surface higher than the upper surface of the semiconductor substrate, and an impurity region formed in the semiconductor substrate under the first isolation insulating film, the impurity region having a conductivity type the same as a conductivity type of the semiconductor substrate, an impurity concentration higher than an impurity concentration of the semiconductor substrate, and a width of the impurity region smaller than a width of the isolation trench.

Abstract: The embodiments of the invention provide a device, method, etc. for a dual stress STI. A semiconductor device is provided having a substrate with a first transistor region and a second transistor region different than the first transistor region. The first transistor region includes a PFET; and, the second transistor region includes an NFET. Further, STI regions are provided in the substrate adjacent sides of and positioned between the first transistor region and the second transistor region, wherein the STI regions each include a compressive region, a compressive liner, a tensile region, and a tensile liner.

Abstract: A method of manufacturing an integrated circuit includes: forming a trench in a substrate, forming a high-k dielectric layer lining the trench, and removing a section of the high-k dielectric layer from the trench via an isotropic dry etch process.

Abstract: A semiconductor device includes a substrate where an isolation region and a plurality of active regions are defined, an anti-interference layer formed over the substrate in the isolation region, and a gate line simultaneously crossing the active region and the anti-interference layer.

Abstract: The present invention generally provides a method for forming multilevel interconnect structures, including multilevel interconnect structures that include an air gap. One embodiment provides a method for forming conductive lines in a semiconductor structure comprising forming trenches in a first dielectric layer, wherein air gaps are to be formed in the first dielectric layer, depositing a conformal dielectric barrier film in the trenches, wherein the conformal dielectric barrier film comprises a low k dielectric material configured to serve as a barrier against a wet etching chemistry used in forming the air gaps in the first dielectric layer, depositing a metallic diffusion barrier film over the conformal low k dielectric layer, and depositing a conductive material to fill the trenches.

Abstract: Disclosed herein is a method of manufacturing semiconductor devices. After first isolation trenches are formed in a cell region, second isolation trenches are formed in a peripheral region by an etch process using a photoresist as a mask. As such, top corner portions of an active substrate of the peripheral region are rounded. It is thus possible to fundamentally prevent a hump phenomenon incurred by thinning of the gate oxide film.

Abstract: A method of isolating semiconductor devices formed on a semiconductor substrate having a silicon on insulator (SOI) layer is provided. The method includes forming at least one shallow trench area on a pad nitride layer deposited on a surface of the SOI layer, wherein the at least one shallow trench area includes an opening for exposing a portion of the SOI layer; applying diblock copolymer material over the pad nitride layer and the at least one shallow trench area; annealing the applied copolymer material to form self-organized patterns; and partially etching the shallow trench area using the diblock copolymer material as an etch mask. A semiconductor structures is also described having an isolation structure formed on a SOI layer of a semiconductor substrate the isolation structure having an oxidized substrate region; and a void region formed on the oxidized substrate region.

Abstract: A method of manufacturing a superjunction device includes providing a semiconductor wafer having at least one die. At least one first trench having a first orientation is formed in the at least one die. At least one second trench having a second orientation that is different from the first orientation is formed in the at least one die.

Abstract: A semiconductor device 1 includes a first semiconductor region 2B and a second semiconductor region 5 provided on a main surface of a substrate 2, being apart from each other and having first conductivity; a third semiconductor region 4 provided between the first semiconductor region 2B and the second semiconductor region 5 and having second conductivity opposite to the first conductivity; a fourth semiconductor region 41 provided on a main surface of the substrate 2, connected to the third semiconductor region 4, manufactured together with the third semiconductor region 4 in the same manufacturing process, and having the conductivity same as that of the third semiconductor region 4; and trenches 42 made on the main surface of the fourth semiconductor region 41 and having a depth smaller than a junction depth of the fourth semiconductor region 41.

Abstract: A MOS transistor and a method for manufacturing the transistor are disclosed. The method for manufacturing the MOS transistor may include successively stacking a pad oxide layer and a mask layer on a semiconductor substrate, patterning the pad oxide layer and the mask layer, to expose a trench forming region of the semiconductor substrate, forming a trench in the semiconductor substrate by etching the exposed trench forming region, and forming an anti-diffusion layer and an oxide layer over the entire surface of the semiconductor substrate including the trench. This method can reduce leakage current, among other things, resulting in improved characteristics of transistor products.

Abstract: Integrated circuits and methods of manufacture and design thereof are disclosed. For example, a method of manufacturing includes using a first mask to pattern a gate material forming a plurality of first and second features. The first features form gate electrodes of the semiconductor devices, whereas the second features are dummy electrodes. Based on the location of these dummy electrodes, selected dummy electrodes are removed using a second mask. The use of the method provides greater flexibility in tailoring individual devices for different objectives.

Abstract: A semiconductor device according to the present invention includes: a semiconductor layer made of silicon; a trench formed by digging in from a top surface of the semiconductor layer; a gate insulating film formed on an inner wall surface of the trench and made of silicon oxide; a gate electrode embedded in the trench via the gate insulating film and made of a polysilicon doped with an impurity; and an oxidation-resistant metal film disposed on a top surface of the gate electrode and covering the top surface.

Abstract: A method for fabricating a semiconductor device includes forming an insulating pattern over a semiconductor substrate. An epitaxial growth layer is formed over the semiconductor substrate exposed by the insulating pattern to fill the insulating pattern with the epitaxial growth layer. A recess gate having a recess channel is formed. The recess channel is disposed between two neighboring insulating patterns.

Abstract: In a nonvolatile semiconductor memory device which has a nonvolatile memory cell portion, a low-voltage operating circuit portion of a peripheral circuit region and a high-voltage operating circuit portion of the peripheral circuit region formed on a substrate and in which elements of the above portions are isolated from one another by filling insulating films, the upper surface of the filling insulating films in the high-voltage operating circuit portion lies above the surface of the substrate and the upper surface of at least part of the filling insulating films in the low-voltage operating circuit portion is pulled back to a portion lower than the surface of the substrate.

Abstract: A method of fabricating a semiconductor device includes forming an ion implanted region on a semiconductor substrate in a cell/core region. The semiconductor substrate is selectively etched to form a recess. The recess exposes a boundary of the ion implanted region. The ion implanted region exposed at the bottom of the recess is removed to form an under-cut space in the semiconductor substrate. An insulating film is formed to form a substrate having a silicon-on-insulator (SOI) structure in the cell/core region. The insulating film fills the under-cut space and the recess.

Abstract: High voltage semiconductor devices with high-voltage termination structures are constructed on lightly doped substrates. Lightly doped p-type substrates are particularly prone to depletion and inversion from positive charges, degrading the ability of associated termination structures to block high voltages. To improve the efficiency and stability of termination structures, second termination regions of the same dopant type as the substrate, more heavily doped than the substrate but more lightly doped than first termination regions, are positioned adjoining the first termination regions. The second termination regions raise the field threshold voltage where the surface is vulnerable and render the termination structure substantially insensitive to positive charges at the surface. The use of higher dopant concentration in the gap region without causing premature avalanche is facilitated by only creating second termination regions for regions lacking field plate protection.

Abstract: A substrate provided with an alignment mark in a substantially transmissive process layer overlying the substrate, said mark comprising high reflectance areas for reflecting radiation of an alignment beam of radiation, and low reflectance areas for reflecting less radiation of the alignment beam, wherein the high reflectance areas comprise at least one substantially linear sub-grating. In one example, a substantially linear sub-grating comprises a plurality of spaced square regions.

Abstract: In a method of forming an isolation layer of a semiconductor device, a gate insulating layer, a first conductive layer, and a hard mask are formed in an active region of a semiconductor substrate and a trench is formed in an isolation region. The trench is partially gap-filled by forming a first insulating layer in the trench. The trench is fully gap-filled by forming a second insulating layer on the first insulating layer. A polishing process is performed on the first insulating layer and the second insulating layer formed over the hard mask. An etchback process is performed to lower a height of the second insulating layer in the trench. The trench is gap-filled by forming a third insulating layer over the first insulating layer and the second insulating layer, thereby forming an isolation layer in the trench. Accordingly, the occurrence of a void within the isolation layer is prevented.

Abstract: A method of manufacturing the semiconductor device includes forming a first polysilicon film on an active region and an element isolation region made of a dielectric material provided in a semiconductor substrate; forming a hard mask on the first polysilicon film; etching the first polysilicon film, the semiconductor substrate in the active region and the dielectric material in the element isolation region by using the hard mask to form first and second gate trenches in the active region and the element isolation region, respectively; and filling the first and second gate trenches with a second polysilicon film before the hard mask is removed.

Abstract: A device and method of reducing residual STI corner defects in a hybrid orientation transistor comprising, forming a direct silicon bonded substrate wherein a second silicon layer with a second crystal orientation is bonded to a handle substrate with a first crystal orientation, forming a pad oxide layer on the second silicon layer, forming a nitride layer on the pad oxide layer, forming an isolation trench within the direct silicon bonded substrate through the second silicon layer and into the handle substrate, patterning a PMOS region of the direct silicon bonded substrate utilizing photoresist including a portion of the isolation trench, implanting and amorphizing an NMOS region of the direct silicon bonded substrate, removing the photoresist, performing solid phase epitaxy, performing a recrystallization anneal, forming an STI liner, completing front end processing, and performing back end processing.

Abstract: A high voltage/power semiconductor device has a semiconductor layer having a high voltage terminal end and a low voltage terminal end. A drift region extends between the high and low voltage terminal ends. A dielectric layer is provided above the drift region. An electrical conductor extends across at least a part of the dielectric layer above the drift region, the electrical conductor being connected or connectable to the high voltage terminal end. The drift region has plural trenches positioned below the electrical conductor. The trenches extend laterally across at least a part of the drift region in the direction transverse the direction between the high and low voltage terminal ends of the semiconductor layer, each trench containing a dielectric material. The trenches improve the distribution of electric field in the device in the presence of the electrical conductor.