Abstract: A method for forming trench isolation on a substrate includes providing a substrate having thereon a pad layer and a hard mask; forming a first shallow trench in a first area and a second trench in a second area on the substrate; forming a resist layer covering the first area while exposing the second area; etching the second shallow trench to form a deep trench; forming oxide liner within the first shallow trench and the deep trench; and filling the shallow trench and the deep trench with an oxide layer.

Abstract: A method and structure provide for customizing STI, shallow trench isolation, structures in various parts of a system-on-chip, SOC, or other semiconductor integrated circuit device. Within an individual chip, STI structures are formed to include different dielectric thicknesses that are particularly advantageous for the particular device portion of the SOC chip in which the STI structure is formed.

Abstract: Disclosed are embodiments of a lateral, extended drain, metal oxide semiconductor, field effect transistor (LEDMOSFET) having a high drain-to-body breakdown voltage. Discrete conductive field (CF) plates are adjacent to opposing sides of the drain drift region, each having an angled sidewall such that the area between the drain drift region and the CF plate has a continuously increasing width along the length of the drain drift region from the channel region to the drain region. The CF plates can comprise polysilicon or metal structures or dopant implant regions within the same semiconductor body as the drain drift region. The areas between the CF plates and the drain drift region can comprise tapered dielectric regions or, alternatively, tapered depletion regions within the same semiconductor body as the drain drift region. Also disclosed are embodiments of a method for forming an LEDMOSFET and embodiments of a silicon-controlled rectifier (SCR) incorporating such LEDMOSFETs.

Abstract: A body contacted semiconductor-on-insulator (SOI) metal gate containing transistor that has a reduced parasitic gate capacitance is provided in which a metal portion of a gate stack is removed over the body contact region and a silicon-containing material is formed that contacts the gate dielectric in the body contact region of an SOI substrate. This causes an increase of the effective gate dielectric thickness on the body contact region by greater than 5 angstroms (?). This results in a lower parasitic capacitance at the body contact region.

Abstract: A lateral, extended drain, metal oxide semiconductor, field effect transistor (LEDMOSFET) with a high drain-to-body breakdown voltage (Vb) incorporates gate structure extensions on opposing sides of a drain drift region. The extensions are tapered such that a distance between each extension and the drift region increases linearly from one end adjacent to the channel region to another end adjacent to the drain region. In one embodiment, these extensions can extend vertically through the isolation region that surrounds the LEDMOSFET. In another embodiment, the extensions can sit atop the isolation region. In either case, the extensions create a strong essentially uniform horizontal electric field profile within the drain drift. Also disclosed are a method for forming the LEDMOSFET with a specific Vb by defining the dimensions of the extensions and a program storage device for designing the LEDMOSFET to have a specific Vb.

Abstract: A high voltage diode in which the n-type cathode is surrounded by an uncontacted heavily doped n-type ring to reflect injected holes back into the cathode region for recombination or collection is disclosed. The dopant density in the heavily doped n-type ring is preferably 100 to 10,000 times the dopant density in the cathode. The heavily doped n-type region will typically connect to an n-type buried layer under the cathode. The heavily doped n-type ring is optimally positioned at least one hole diffusion length from cathode contacts. The disclosed high voltage diode may be integrated into an integrated circuit without adding process steps.

Abstract: A method of manufacturing an IC, comprising providing a substrate having a first side and a second opposite side, forming a STI opening in the first side of the substrate and forming a partial TSV opening in the first side of the substrate and extending the partial TSV opening. The extended partial TSV opening is deeper into the substrate than the STI opening. The method also comprises filling the STI opening with a first solid material and filling the extended partial TSV opening with a second solid material. Neither the STI opening, the partial TSV opening, nor the extended partial TSV opening penetrate an outer surface of the second side of the substrate. At least either: the STI opening and the partial TSV opening are formed simultaneously, or, the STI opening and the extended partial TSV opening are filled simultaneously.

Abstract: In sophisticated semiconductor devices, a semiconductor alloy, such as a threshold adjusting semiconductor material in the form of silicon/germanium, may be provided in an early manufacturing stage selectively in certain active regions, wherein a pronounced degree of recessing and material loss, in particular in isolation regions, may be avoided by providing a protective material layer selectively above the isolation regions. For example, in some illustrative embodiments, a silicon material may be selectively deposited on the isolation regions.

Abstract: A method of manufacturing a semiconductor device includes forming a plurality of strings spaced a first distance from each other, each string including first preliminary gate structures spaced a second distance, smaller than the first distance, between second preliminary gate structures, forming a first insulation layer to cover the first and second preliminary gate structures, forming an insulation layer structure to fill a space between the strings, forming a sacrificial layer pattern to partially fill spaces between first and second preliminary gate structures, removing a portion of the first insulation layer not covered by the sacrificial layer pattern to form a first insulation layer pattern, reacting portions of the first and second preliminary gate structures not covered by the first insulation layer pattern with a conductive layer to form gate structures, and forming a capping layer on the gate structures to form air gaps between the gate structures.

Abstract: Circuits, structures and techniques for independently connecting a surrounding material in a part of a semiconductor device to a contact of its respective device. To achieve this, a combination of one or more conductive wells that are electrically isolated in at least one bias polarity are provided.

Abstract: A 3D memory device includes an array of semiconductor body pillars and bit line pillars, dielectric charge trapping structures, and a plurality of levels of word line structures arranged orthogonally to the array of semiconductor body pillars and bit line pillars. The semiconductor body pillars have corresponding bit line pillars on opposing first and second sides, providing source and drain terminals. The semiconductor body pillars have first and second channel surfaces on opposing third and fourth sides. Dielectric charge trapping structures overlie the first and second channel surfaces, providing data storage sites on two sides of each semiconductor body pillar in each level of the 3D array. The device can be operated as a 3D AND-decoded flash memory.

Abstract: A method for producing a semiconductor component includes providing a semiconductor body with a first surface and a second surface opposite the first surface, forming an insulation trench which extends into the semiconductor body from the first surface and which in a horizontal plane of the semiconductor body has a geometry such that the insulation trench defines a via region of the semiconductor body, forming a first insulation layer on one or more sidewalls of the insulation trench, removing semiconductor material of the semiconductor body from the second surface to expose at least parts of the first insulation layer, to remove at least parts of the first insulation layer, or to leave at least partially a semiconductor layer with a thickness of less than 1 ?m between the first insulation layer and the second surface, and forming first and second contact electrodes on the via region.

Abstract: A method includes forming first insulating films on first and second faces of a substrate, removing the first insulating film on the second face, forming polysilicon films on the first insulating film on the first face and the second face, forming second insulating films on the polysilicon films on the first face and the second face, etching the second insulating film on the first face using a mask including an opening, removing the second insulating films on the first face and the second face, removing the polysilicon film on the side of the first face and forming a passivation film which protects the polysilicon film on the side of the second face so that the polysilicon film on the side of the second face is not removed in the polysilicon film removing step, after the polysilicon film forming step and before the polysilicon film removing step.

Abstract: Semiconductors devices and methods of making semiconductor devices are provided. According to one embodiment, a semiconductor device can include a p-type field effect transistor area having an active region with an epitaxial layer grown thereupon and an isolation feature adjacent to the active region. A height of the isolation feature equals or exceeds a height of an interface between the epitaxial layer and the active region. More particularly, a height of the isolation feature in the corner of a junction between the isolation feature and the action region equals or exceeds the height to the interface between the epitaxial layer and the active region.

Abstract: A contact plug 40 electrically connected to an impurity diffusion region between sidewalls of an adjacent pair of memory cells 1 is provided to pass through an interlayer dielectric film 18. A side wall of a contact hole 41 is covered with a sealing film 42 denser than the interlayer dielectric film 18. The contact plug 40 includes a barrier metal film 43 formed to cover a surface of the sealing film 42 and a bottom surface portion of the contact hole 41 and a metal plug 44 embedded in the contact hole 41 in a state surrounded by the barrier metal film 43.

Abstract: The present invention relates to substrates for ICs and method for forming the same. The method comprises the steps of: forming a hard mask layer on the bulk silicon material; etching the hard mask layer and the bulk silicon material to form a first part for shallow trench isolation of at least one trench; forming a dielectric film on the sidewall of the at least one trench; further etching the bulk silicon material to deepen the at least one trench so as to form a second part of the at least one trench; completely oxidizing or nitridizing parts of the bulk silicon material which are between the second parts of the trenches, and parts of the bulk silicon material which are between the second parts of the trenches and side surfaces of the bulk silicon substrate; filling dielectric materials in the first and second parts of the at least one trench; and removing the hard mask layer.

Abstract: Semiconductor device manufacturing method includes forming a first mask, having a first opening to implant ion into semiconductor substrate and being used to form first layer well, on semiconductor substrate; forming first-layer well having first and second regions by implanting first ion into semiconductor substrate using first mask; forming second mask, having second opening to implant ion into semiconductor substrate and being used to form second layer well, on semiconductor substrate; and forming second-layer well below first layer well by implanting second ion into semiconductor substrate using second mask. First region is formed closer to an edge of first-layer well than second region. Upon implanting first ion, first ion deflected by first inner wall of first mask is supplied to first region. Upon implanting second ion, second ion deflected by second inner wall of second mask is supplied to second region.

Abstract: A semiconductor device includes a substrate having an active region and an isolation region, a gate pattern crossing both the active region and the isolation region of the substrate, and a protrusion having a surface higher than that of the substrate over at least an edge of the active region contacting a portion of the isolation region under the gate pattern.

Abstract: A structure for reducing partially etched materials is described. The structure includes a layout of an intersection area between two trenches. First, a large intersection area having a trapezoidal corner may be replaced with an orthogonal intersection between two trenches. The layout reduces the intersection area as well as the possibility of having partially etched materials left at the intersection area. The structure also includes an alternative way to fill the intersection area with either an un-etched small trapezoidal area or multiple un-etched square areas, so that the opening area at the intersection point is reduced and the possibility of having partially etched materials is reduced too.

Abstract: An integrated circuit (IC) includes an active region; a pair of active field effect transistors (FETs) in the active region; and an isolation FET located between the pair of active FETs in the active region, the isolation FET configured to provide electrical isolation between the pair of active FETs, wherein the isolation FET has at least one different physical parameter or electrical parameter from the pair of active FETs.

Abstract: A semiconductor device and manufacturing method is disclosed. One embodiment provides a common substrate of a first conductivity type and at least two wells of a second conductivity type. A buried high resistivity region and at least an insulating structure is provided insulating the first well from the second well. The insulating structure extends through the buried high resistivity region and includes a conductive plug in Ohmic contact with the first semiconductor region. A method for forming an integrated semiconductor device is also provided.

Abstract: A method of making a semi-insulating epitaxial layer includes implanting a substrate or a first epitaxial layer formed on the substrate with boron ions to form a boron implanted region on a surface of the substrate or on a surface of the first epitaxial layer, and growing a second epitaxial layer on the boron implanted region of the substrate or on the boron implanted region of the first epitaxial layer to form a semi-insulating epitaxial layer.

Abstract: A semiconductor device includes a first line pattern and a second line pattern formed in parallel on a semiconductor substrate, third line patterns formed in parallel between the first line pattern and the second line pattern, fourth line patterns formed in parallel between the first line pattern and the second line pattern, a first connection structure configured to couple a first of the third line patterns with a first of the fourth lines patterns, which are adjacent to the first line pattern, and a second connection structure configured to couple a second of the first lines patterns with a second of the fourth lines patterns, which are adjacent to the second line pattern.

Abstract: The invention relates to a semiconductor structure and a manufacturing method of the same. The semiconductor structure includes a semiconductor substrate, an isolation layer, a first metal layer, and a second metal layer. The semiconductor substrate includes an upper substrate surface and a semiconductor device below the upper substrate surface. The isolation layer has opposite a first side wall and a second side wall. The first metal layer is disposed on the upper substrate surface. The first metal layer and the second metal layer are disposed on the first side wall and the second side wall, respectively. A lower surface of the second metal layer is below the upper substrate surface.

Abstract: Techniques for forming devices, such as transistors, having vertical junction edges. More specifically, shallow trenches are formed in a substrate and filled with an oxide. Cavities may be formed in the oxide and filled with a conductive material, such a doped polysilicon. Vertical junctions are formed between the polysilicon and the exposed substrate at the trench edges such that during a thermal cycle, the doped polysilicon will out-diffuse doping elements into the adjacent single crystal silicon advantageously forming a diode extension having desirable properties.

Abstract: A method for forming a semiconductor device with stressed trench isolation is provided, comprising: providing a silicon substrate (S11); forming at least two first trenches in parallel on the silicon substrate and forming a first dielectric layer which is under tensile stress in the first trenches (S12); forming at least two second trenches, which have an extension direction perpendicular to that of the first trenches, in parallel on the silicon substrate, and forming a second dielectric layer in the second trenches (S13); and after forming the first trenches, forming a gate stack on a part of the silicon substrate between two adjacent first trenches, wherein the channel length direction under the gate stack is parallel to the extension direction of the first trenches (S14). The present invention supply tensile stress in the channel width direction of a MOS transistor, so as to improve performance of PMOS and/or NMOS transistors.

Abstract: Techniques for fabricating thin film solar cells are provided. In one aspect, a method of fabricating a solar cell includes the following steps. A molybdenum (Mo)-coated substrate is provided. Absorber layer constituent components, two of which are sulfur (S) and selenium (Se), are deposited on the Mo-coated substrate. The S and Se are deposited on the Mo-coated substrate using thermal evaporation in a vapor chamber. Controlled amounts of the S and Se are introduced into the vapor chamber to regulate a ratio of the S and Se provided for deposition. The constituent components are annealed to form an absorber layer on the Mo-coated substrate. A buffer layer is formed on the absorber layer. A transparent conductive electrode is formed on the buffer layer.

Abstract: A method for producing a device with at least one suspended membrane, including the following steps: Producing a trench through a first sacrificial layer and a second layer deposited on the first sacrificial layer, the trench completely surrounding at least a portion of the first sacrificial layer and at least a portion of the second layer, filling all or a portion of the trench with at least one material capable of resisting at least one etching agent, and etching the portion of the first sacrificial layer with the etching agent through at least one opening made in the second layer, the portion of the second layer forming at least one portion of the suspended membrane.

Abstract: Stacking faults are reduced or eliminated by epitaxially growing a III-V compound semiconductor region in a trench followed by capping and annealing the region. The capping layer limits the escape of atoms from the region and enables the reduction or elimination of stacking faults along with the annealing.

Abstract: A semiconductor device having strain material is disclosed. In a particular embodiment, the semiconductor device includes a first cell including a first gate between a first drain and a first source. The semiconductor device also includes a second cell adjacent to the first cell. The second cell includes a second gate between a second drain and a second source. The semiconductor device further includes a shallow trench isolation area between the first source and the second source. A first amount of strain material over the first source and over the second source is greater than a second amount of strain material over the first drain and over the second drain.

Abstract: A transistor includes a notched fin covered under a shallow trench isolation layer. One or more notch may be used, the size of which may vary along a lateral direction of the fin. In some embodiments, The notch is formed using anisotropic wet etching that is selective according to silicon orientation. Example wet etchants are tetramethylammonium hydroxide (TMAH) or potassium hydroxide (KOH).

Abstract: A vertical semiconductor device (e.g. a vertical power device, an IGBT device, a vertical bipolar transistor, a UMOS device or a GTO thyristor) is formed with an active semiconductor region, within which a plurality of semiconductor structures have been fabricated to form an active device, and below which at least a portion of a substrate material has been removed to isolate the active device, to expose at least one of the semiconductor structures for bottom side electrical connection and to enhance thermal dissipation. At least one of the semiconductor structures is preferably contacted by an electrode at the bottom side of the active semiconductor region.

Abstract: Integrated circuits with guard rings are provided. Integrated circuits may include internal circuitry that is sensitive to external noise sources. A guard ring may surround the functional circuitry to isolate the circuitry from the noise sources. The guard ring may include first, second, and third regions. The first and third regions may include p-wells. The second region may include an n-well. Stripes of diffusion regions may be formed at the surface of a substrate in the three regions. Areas in the guard ring that are not occupied by the diffusion regions are occupied by shallow trench isolation (STI) structures. Stripes of dummy structures may be formed over respective STI structures and may not overlap the diffusion regions. The diffusion regions in the first and third regions may be biased to a ground voltage. The diffusion regions in the second section may be biased to a positive power supply voltage.

Abstract: In one embodiment, a method of manufacturing a semiconductor memory device is disclosed. The method can comprise forming a tunnel insulating film on a substrate, forming a charge storage layer including a conductor on the tunnel insulating film, forming an isolation trench which isolate the charge storage layer and the tunnel insulating film in the substrate, embedding an isolation insulating film in the isolation trench, removing a native oxide film which is formed on a surface of the charge storage layer, and forming an insulating film on a surface of the isolation insulating film and the surface of the charge storage layer. The process from the removing the native oxide film to the forming the insulating film carried out in a manufacture apparatus in which an oxygen concentration is controlled.

Abstract: When forming complex gate electrode structures, a double exposure double etch strategy may be applied, in which the lateral distance in the width direction of the gate electrode structures may be defined prior to forming mask features for defining the gate length. In this case, the width dimension of the mask opening may be adjusted on the basis of a spacer element, which may thus allow providing a reduced dimension on the basis of well-established process techniques.

Abstract: A semiconductor device 1 includes a first semiconductor region 2B and a second semiconductor region 5 provided on a main surface of a substrate 2, being apart from each other and having first conductivity; a third semiconductor region 4 provided between the first semiconductor region 2B and the second semiconductor region 5 and having second conductivity opposite to the first conductivity; a fourth semiconductor region 41 provided on a main surface of the substrate 2, connected to the third semiconductor region 4, manufactured together with the third semiconductor region 4 in the same manufacturing process, and having the conductivity same as that of the third semiconductor region 4; and trenches 42 made on the main surface of the fourth semiconductor region 41 and having a depth smaller than a junction depth of the fourth semiconductor region 41.

Abstract: An isolated epitaxial modulation device comprises a substrate; a barrier structure formed on the substrate; an isolated epitaxial region formed above the substrate and electrically isolated from the substrate by the barrier structure; a semiconductor device, the semiconductor device located in the isolated epitaxial region; and a modulation network formed on the substrate and electrically coupled to the semiconductor device. The device also comprises a bond pad and a ground pad. The isolated epitaxial region is electrically coupled to at least one of the bond pad and the ground pad. The semiconductor device and the epitaxial modulation network are configured to modulate an input voltage.

Abstract: A structure for aligning a first set of features of a fabrication level of an integrated circuit chip to an electron beam alignment target. The structure including a first trench in a semiconductor substrate, the first trench extending from a top surface of the substrate into the substrate a first distance; an electron back-scattering layer in a bottom of the first trench; a dielectric capping layer in the trench over the back-scattering layer; and a second trench in the substrate, the second trench extending from the top surface of the substrate into the substrate a second distance, the second distance less than the first distance.

Abstract: According to one embodiment, a semiconductor device includes a semiconductor substrate, a first insulating layer, an electrode pad, a through hole, a second insulating layer, and a conductive material. A through groove passes through the semiconductor substrate from a surface to an opposite surface. The first insulating layer fills the through groove. The electrode pad is connected with an interconnection layer. The second insulating layer is provided between the electrode pad and the first insulating layer. The through hole communicates with the electrode pad and passes through the first insulating layer and the second insulating layer. The conductive material is provided in the through hole so as to be connected with the electrode pad.

Abstract: A semiconductor device manufacturing method has forming element isolation trenches in a semiconductor substrate, forming a silicon compound film in insides of the element isolation trenches in order to embed the element isolation trenches, conducting a first oxidation processing at a first temperature to reform a surface of the silicon compound film to a volatile matter emission preventing layer which permits passage of an oxidizing agent and impurities and which does not permit passage of a volatile matter containing silicon atoms, and conducting a second oxidation processing at a second temperature which is higher than the first temperature to form a coated silicon oxide film inside the element isolation trenches.

Abstract: A conductive film having a first width in a first direction, an ONO film, and a control gate are formed above a tunnel gate insulating film. With the control gate as a mask, the conductive film is etched to form a floating gate. Then, an inter-layer insulating film is formed. A contact hole whose width in the first direction is larger than the first width is formed in the inter-layer insulating film. Then, sidewall spacer is formed on an inside wall of the contact hole.

Abstract: A method of manufacturing a semiconductor device includes forming a resist pattern on a first region on a substrate, bringing a descum solution including an acid source into contact with the resist pattern and with a second region of the substrate, decomposing resist residues remaining on the second region of the substrate by using acid obtained from the acid source in the descum solution and removing the decomposed resist residues and the descum solution from the substrate.

Abstract: In a reliable semiconductor device and a method of fabricating the semiconductor device, a difference in height between upper surfaces of a cell region and a peripheral region (also referred to as a level difference) is minimized by optimizing dummy gate parts. The semiconductor device includes a semiconductor substrate including a cell region and a peripheral region surrounding the cell region, a plurality of dummy active regions surrounded by a device isolating region and formed apart from each other, and a plurality of dummy gate parts formed on the dummy active regions and on the device isolating regions located between the dummy active regions, wherein each of the dummy gate parts covers two or more of the dummy active regions.

Abstract: An embodiment of a method for producing traceable integrated circuits includes forming on a wafer of semiconductor material functional regions for implementing specific functionalities of corresponding integrated circuits, forming at least one seal ring around each functional region of the corresponding integrated circuit, and forming on each integrated circuit at least one marker indicative of information of the integrated circuit. Forming on each integrated circuit at least one marker may include forming the at least one marker on at least a portion of the respective seal ring that is visible.

Abstract: Disclosed herein is a semiconductor device including an element isolation region configured to be formed on a semiconductor substrate, wherein the element isolation region is formed of a multistep trench in which trenches having different diameters are stacked and diameter of an opening part of the lower trench is smaller than diameter of a bottom of the upper trench.

Abstract: A low gate charging rectifier having a MOS structure and a P-N junction and a manufacturing method thereof are provided. The low gate charging rectifier is a combination of an N-channel MOS structure and a lateral P-N junction diode. A portion of the gate-covering region is replaced by a thicker dielectric layer or a low conductivity polysilicon layer. In a forward mode, the N-channel MOS structure and the P-N junction diode are connected with each other in parallel. Under this circumstance, like the Schottky diode, the low gate charging rectifier has low forward voltage drop and rapid switching speed. Whereas, in a reverse mode, the leakage current is pinched off and the N-channel is shut off by the depletion region of the P-N junction diode, so that the low gate charging rectifier has low leakage current.

Abstract: A method for fabricating a semiconductor device includes forming a plurality of first trenches by etching a substrate, forming first spacers covering both sidewalls of each of the first trenches, forming a plurality of second trenches by etching a bottom of each of the first trenches, forming second spacers covering both sidewalls of each of the second trenches, forming a plurality of third trenches by etching a bottom of each of the second trenches, forming an insulation layer covering exposed surfaces of the plurality of the substrate, and forming a contact which exposes one sidewall of each of the second trenches by selectively removing the second spacers.

Abstract: A semiconductor device, including a substrate having first and second active regions, the first and second active regions being disposed on opposite sides of an isolation structure, and a bit line electrically coupled to a contact plug that is on the isolation structure between the first active region and the second active region, and electrically coupled to an active bridge pattern directly contacting at least one of the first and second active regions, wherein the contact plug is electrically coupled to the first active region and the second active region, and a bottom surface of the active bridge pattern is below a top surface of the first and second active regions.

Abstract: A semiconductor device fabricated in the semiconductor substrate includes a FinFET transistor having opposed source and drain pillars, and a fin interposed between the source and drain pillars. A cavity is formed in the semiconductor substrate extending at least partially between the fin and the semiconductor substrate. The cavity may be formed within a shallow trench isolation structure, and it may also extend at least partially between the semiconductor substrate and one or both of the pillars. The cavities increase the impedance between the semiconductor substrate and the fin and/or pillars to decrease the sub-threshold leakage of the FinFET transistor.

Abstract: A semiconductor device comprises a gate structure on a semiconductor substrate and a recessed region in the semiconductor substrate. The recessed region has a widest lateral opening that is near a top surface of the semiconductor substrate. The widest lateral opening undercuts the gate structure.