Abstract: The present invention discloses a method of fabricating a semiconductor memory device including forming sequentially a gate insulating layer and a first conductive pattern on a semiconductor substrate; forming a protective layer on surfaces of the first conductive pattern and the gate insulating layer; performing an etching process to form a trench, the etching process being performed such that the protective layer remains on side walls of the first conductive pattern to form a protective pattern; forming an isolation layer in the trench; etching the isolation layer; removing the protective pattern above a surface of the isolation layer; and forming sequentially a dielectric layer and a second conductive layer on surfaces of the isolation layer, the protective pattern and the first conductive pattern.

Abstract: There is a method of forming a contact post and surrounding isolation trench in a semiconductor-on-insulator (SOI) substrate. The method comprises etching a contact hole and surrounding isolation trench from an active layer of the substrate to the insulating layer, masking the trench and further etching the contact hole to the base substrate layer, filling the trench and contact hole with undoped intrinsic polysilicon and then performing a doping process in respect of the polysilicon material filling the contact hole so as to form in situ a highly doped contact post, while the material filling the isolation trench remains non-conductive. The isolation trench and contact post are formed substantially simultaneously so as to avoid undue interference with the device fabrication process.

Abstract: A method for forming a transistor of a semiconductor device, includes forming a trench by etching a semiconductor substrate on which a pad oxide film and a pad nitride film are sequentially formed; forming a isolation oxide film by filling the trench with oxide; removing an upper portion of the isolation oxide film until an upper lateral portion of the semiconductor substrate is exposed; forming a barrier nitride film over the isolation oxide film, the semiconductor substrate, and the pad nitride film; forming a sacrificial oxide film over the barrier nitride film; performing a planarization process until the pad nitride film is exposed; performing a wet etching process until the active region is exposed; forming a photoresist pattern over the active region and the barrier nitride film; and performing a dry etching process by using the photoresist pattern as an etching mask, thereby forming a recessed gate trench.

Abstract: A nonvolatile memory cell is provided. A semiconductor substrate is provided. A conducting layer and a spacer layer are sequentially disposed above the semiconductor substrate. At least a trench having a bottom and plural side surfaces is defined in the conducting layer and the spacer layer. A first oxide layer is formed at the bottom of the trench. A dielectric layer is formed on the first oxide layer, the spacer layer and the plural side surfaces of the trench. A first polysilicon layer is formed in the trench. And a first portion of the dielectric layer on the spacer layer is removed, so that a basic structure for the nonvolatile memory cell is formed.

Abstract: A method for fabricating a semiconductor device with a recess gate includes providing a substrate, forming an isolation layer over the substrate to define an active region, forming mask patterns with a first width opening exposing a region where recess patterns are to be formed, and a second width opening smaller than the first width and exposing the isolation layer, forming a passivation layer along a height difference of the mask patterns, etching the substrate using the passivation layer and the mask patterns as an etch barrier to form recess patterns, removing the passivation layer and the mask patterns, and forming gate patterns protruding from the substrate to fill the recess patterns.

Abstract: A method of manufacturing a semiconductor device structure, such as a FinFET device structure, is provided. The method begins by providing a substrate comprising a bulk semiconductor material, a first conductive fin structure formed from the bulk semiconductor material, and a second conductive fin structure formed from the bulk semiconductor material. The first conductive fin structure and the second conductive fin structure are separated by a gap. Next, spacers are formed in the gap and adjacent to the first conductive fin structure and the second conductive fin structure. Thereafter, an etching step etches the bulk semiconductor material, using the spacers as an etch mask, to form an isolation trench in the bulk semiconductor material. A dielectric material is formed in the isolation trench, over the spacers, over the first conductive fin structure, and over the second conductive fin structure.

Abstract: An integrated circuit chip and a method of fabricating an integrated circuit chip. The integrated circuit chip includes: a set of wiring levels stacked from a first wiring level to a last wiring level; and a respective void in each wiring level of two or more wiring levels of the set wiring levels, each respective void extending in a continuous ring parallel and proximate to a perimeter of the integrated circuit chip, a void of a higher wiring level stacked directly over but not contacting a void of a lower wiring level, the respective voids forming a crack stop.

Abstract: A semiconductor device can include a semiconductor substrate, a first trench formed in the semiconductor substrate, a second trench formed in the semiconductor substrate, a first device isolation layer formed in the first trench, a second device isolation layer formed in the second trench having a different structure than the first device isolation layer.

Abstract: A semiconductor device with a field electrode and method. One embodiment provides a controllable semiconductor device including a control electrode for controlling the semiconductor device and a field electrode. The field electrode includes a number of longish segments which extend in a first lateral direction and which run substantially parallel to one another. The control electrode includes a number of longish segments extending in a second lateral direction and running substantially parallel to one another, wherein the first lateral direction is different from the second lateral direction.

Abstract: A semiconductor structure which includes a trench gate FET is formed as follows. A plurality of trenches is formed in a semiconductor region using a mask. The mask includes (i) a first insulating layer over a surface of the semiconductor region, (ii) a first oxidation barrier layer over the first insulating layer, and (iii) a second insulating layer over the first oxidation barrier layer. A thick bottom dielectric (TBD) is formed along the bottom of each trench. The first oxidation barrier layer prevents formation of a dielectric layer along the surface of the semiconductor region during formation of the TBD.

Abstract: An integrated circuit includes flash memory cells, and peripheral circuitry including low voltage transistors (LVT) and high voltage transistors (HVT). The integrated circuit includes a tunnel barrier layer comprising SiON, SiN or other high-k material. The tunnel barrier layer may comprise a part of the gate dielectric of the HVTs. The tunnel barrier layer may constitute the entire gate dielectric of the HVTs. The corresponding tunnel barrier layer may be formed between or upon shallow trench isolation (STIs). Therefore, the manufacturing efficiency of a driver chip IC may be increased.

Abstract: A method of forming a device is presented. The method includes providing a structure having first and second regions. A diffusion barrier is formed between at least a portion of the first and second regions. The diffusion barrier comprises cavities that reduce diffusion of elements between the first and second regions.

Abstract: One-transistor (1T) capacitor-less DRAM cells each include a MOS transistor having a bias gate layer that separates a floating body region from a base substrate. The MOS transistor functions as a storage device, eliminating the need of the storage capacitor. Logic “1” is written to and stored in the storage device by causing majority carriers (holes in an NMOS transistor) to accumulate and be held in the floating body region next to the bias gate layer, and is erased by removing the majority carriers from where they are held.

Abstract: A vertical transistor with integrated isolation is provided. The vertical transistor includes a vertical semiconductor structure and an isolation layer on a bottom surface of the vertical semiconductor structure. The vertical transistor further includes a plurality of terminals on a top surface of the vertical semiconductor structure.

Abstract: An integrated circuit with stress enhanced channels, a design structure and a method of manufacturing the integrated circuit is provided. The method includes forming a dummy gate structure on a substrate and forming a trench in the dummy gate structure. The method further includes filling a portion of the trench with a strain inducing material and filling a remaining portion of the trench with gate material.

Abstract: Methods of isolating gates in a semiconductor structure. In one embodiment, isolation is achieved using a spacer material in combination with fins having substantially vertical sidewalls. In another embodiment, etch characteristics of various materials utilized in fabrication of the semiconductor structure are used to increase the effective gate length (“Leffective”) and the field gate oxide. In yet another embodiment, a V-shaped trench is formed in the semiconductor structure to increase the Leffective and the field gate oxide. Semiconductor structures formed by these methods are also disclosed.

Abstract: An integrated circuit includes an array of transistors and wordlines, where individual wordlines are coupled to a number of the transistors. Conductive structures that are insulated from the wordlines are disposed in a layer beneath the wordlines and are arranged between the transistors.

Abstract: A semiconductor package including an interconnect air gap and method for making the same. The semiconductor package includes a dielectric layer, a metallic interconnect, an air gap disposed between the dielectric layer and interconnect, and a spacer interspersed between the metallic interconnect and air gap. The metallic interconnect is laterally supported by and isolated from the air gap by the spacer. A method for making the same is also provided.

Abstract: Methods for fabricating a non-planar transistor. Fin field effect transistors (finFETs) are often built around a fin (e.g., a tall, thin semiconductive member). During manufacturing, a fin may encounter various mechanical stresses, e.g., inertial forces during movement of the substrate and fluid forces during cleaning steps. If the forces on the fin are too large, the fin may fracture and possibly render a transistor inoperative. Supporting one side of a fin before forming the second side of a fin creates stability in the fin structure, thereby counteracting many of the mechanical stresses incurred during manufacturing.

Abstract: An integrated circuit (IC) with localized SiGe embedded in a substrate and a method of manufacturing the IC is provided. The method includes forming recesses in a substrate on each side of a gate structure and remote from a shallow trench isolation structure. The method further includes growing a stress material within the recesses such that the stress material is bounded on its side only by the substrate.

Abstract: A method for manufacturing a field plate in a trench of a power transistor in a substrate of a first conductivity type is disclosed. The trench is formed in a first main surface of the substrate.

Abstract: A method of depositing dielectric material into sub-micron spaces and resultant structures is provided. After a trench is etched in the surface of a wafer, an oxygen barrier is deposited into the trench. An expandable, oxidizable liner, preferably amorphous silicon, is then deposited. The trench is then filled with a spin-on dielectric (SOD) material. A densification process is then applied, whereby the SOD material contracts and the oxidizable liner expands. Preferably, the temperature is ramped up while oxidizing during at least part of the densification process. The resulting trench has a negligible vertical wet etch rate gradient and a negligible recess at the top of the trench.

Abstract: A method for manufacturing CMOS transistors includes an etching back process alternatively performed after the gate structure formation, the lightly doped drain formation, source/drain implantation, or SEG process to etch a hard mask layer covering and protecting a first type gate structure, and to reduce thickness deviation between the hard masks covering the first type gate structure and a second type gate structure. Therefore the damage to spacers, STIs, and the profile of the gate structures due to the thickness deviation is prevented.

Abstract: Provided are a semiconductor device with a channel of a FIN structure and a method for manufacturing the same. In the method, a device isolation layer defining an active region is formed on a semiconductor substrate. A recess trench with a first width is formed in the active region, and a trench with a second width larger than the first width is formed in the device isolation layer. The trench formed in the device isolation layer is filled with a capping layer. A cleaning process is performed on the recess trench to form a bottom protrusion of a FIN structure including a protrusion and a sidewall. Gate stacks filling the recess trench are formed. A landing plug, which is divided by the capping layer filling the trench, is formed between the gate stacks.

Abstract: The invention relates to a method includes etching at least one shallow trench in at least an SIO layer; forming a dielectric liner at an interface of the SIO layer and the SIO layer; forming a metal or metal alloy layer in the shallow trench on the dielectric liner; and filling the shallow trench with oxide material over the metal or metal alloy.

Abstract: A semiconductor structure includes a semiconductor substrate; a planar transistor on a first portion of the semiconductor substrate, wherein the first portion of the semiconductor substrate has a first top surface; and a multiple-gate transistor on a second portion of the semiconductor substrate. The second portion of the semiconductor substrate is recessed from the first top surface to form a fin of the multiple-gate transistor. The fin is electrically isolated from the semiconductor substrate by an insulator.

Abstract: Methods of pitch doubling of asymmetric features and semiconductor structures including the same are disclosed. In one embodiment, a single photolithography mask may be used to pitch double three features, for example, of a DRAM array. In one embodiment, two wordlines and a grounded gate over field may be pitch doubled. Semiconductor structures including such features are also disclosed.

Abstract: The disclosure describes a multi-layer shallow trench isolation structure in a semiconductor device. The shallow trench isolation structure may include a first void-free, doped oxide layer in the shallow trench, and a second void-free layer above the first doped oxide layer. The first layer may be formed by vapor deposition of precursors of a source of silicon, a source of oxygen and sources of doping materials and making the layer void-free by reflowing the initial layer by an annealing process. The second layer may be formed by vapor deposition of precursors of silicon and doping materials and making the layer void-free by reflowing the initial layer by an annealing process. Alternatively, the second layer may be a silicon oxide layer that may be formed by an atomic layer deposition method. The processing conditions for forming the two layers are different.

Abstract: A method for fabricating a semiconductor device is provided. The method includes forming a pad oxide layer on a semiconductor substrate, forming a pad nitride layer on the pad oxide layer, forming a capping layer on the pad nitride layer, patterning the capping layer, the pad nitride layer, and the pad oxide layer by a photolithography method to expose portions of the semiconductor substrate, forming a field oxidation layer having bird's beaks, the bird's beaks being formed under the pad nitride layer, forming trenches in the semiconductor substrate by anisotropically etching the field oxide layer and the semiconductor substrate using the pad nitride layer as a mask, removing the capping layer, the pad nitride layer, the pad oxide layer, and the bird's beaks, and forming an isolation region in the trenches.

Abstract: In a method of fabricating a trench isolation structure of a semiconductor device, excellent gap filling properties are attained, without the generation of defects. In one aspect, the method comprises: loading a substrate with a trench formed therein into a high-density plasma (HDP) chemical vapor deposition apparatus; primarily heating the substrate; applying a first bias power to the apparatus so as to form an HDP oxide liner on side wall and bottom surfaces of the trench, a gap remaining in the trench following formation of the HDP oxide liner; removing the application of the first bias power and secondarily heating the substrate; applying a second bias power at a power level that is greater than that of the first bias power to the substrate so as to form an HDP oxide film to fill the gap in the trench; and unloading the substrate from the apparatus.

Abstract: A semiconductor device having assist features and manufacturing method thereof includes a substrate having at least an active region and a peripheral region defined thereon. The semiconductor device also includes a plurality of assist features positioned in the peripheral region, or in the active region with a dotted line pattern. The assist features are electrically connected to active circuits formed in the active region, respectively, for serving as redundant circuits that repair or replace defective circuits.

Abstract: In various embodiments, semiconductor structures and methods to manufacture these structures are disclosed. In one embodiment, a method includes forming a portion of the unidirectional transistor and a portion of a bidirectional transistor in or over a semiconductor material simultaneously. Other embodiments are described and claimed.

Abstract: According to an aspect of the present invention, there is provided a semiconductor device including: a semiconductor substrate; active areas with island-like shapes formed on the semiconductor substrate; an element isolation area surrounding the active areas and including an element isolation groove formed on the semiconductor substrate and an element isolation film embedded into the element isolation groove; gate insulating films each formed on corresponding one of the active areas and having a first end portion that overhangs from the corresponding active area onto the element isolation area at one side and a second end portion that overhangs from the corresponding active area onto the element isolation area at the other side, wherein an overhang of the first end portion has a different length from a length of an overhang of the second end portion.

Abstract: Disclosed herein is a method for manufacturing a semiconductor device that includes: etching a semiconductor substrate to form a recess region; forming a device isolation trench in a portion of the etched semiconductor substrate including a portion of the recess region; and forming a device isolation film in the device isolation trench. The recess region is formed before the device isolation film, which can prevent a gate subsequently formed over the device isolation film from leaning. As a result, a subsequent landing plug contact hole is opened, which can improve process defects.

Abstract: A semiconductor device includes a memory section formed at a semiconductor substrate and including a first transistor having an ONO film that can store charges between the semiconductor substrate and a memory electrode and a first STI region for isolating the first transistor, and a CMOS section formed at the semiconductor substrate and including a second transistor having a CMOS electrode and a gate dielectric and a second STI region for isolating the second transistor. The height of the top surface of the first STI region is set equal to or smaller than the height of the top surface of the second STI region.

Abstract: A method of fabricating an isolation structure and the structure thereof is provided. The method is compatible with the embedded memory process and provides the isolation structure with a poly cap thereon to protect the top corners of the isolation structure, without using an extra photomask.

Abstract: Provided are a high-voltage semiconductor device including a junction termination which electrically isolates a low voltage unit from a high voltage unit, and a method of fabricating the same. The high voltage semiconductor device includes a high voltage unit, a low voltage unit surrounding the high voltage unit, and a junction termination formed between the high voltage unit and the low voltage unit and surrounding the high voltage unit to electrically isolate the high voltage unit from the low voltage unit. The junction termination includes at least one level shifter which level shifts signals from the low voltage unit and supplies the same to the high voltage unit, a first device isolation region surrounding the high voltage unit to electrically isolate the high voltage unit from the level shifter, and a resistor layer electrically connecting neighboring level shifters.

Abstract: A hybrid orientation substrate includes a base substrate having a first orientation, a first surface layer having a first orientation disposed on the base substrate in a first region, and a second surface layer disposed on the base substrate in a second region. The second surface layer has an upper sub-layer having a second orientation, and a lower sub-layer between the base substrate and the upper sub-layer. The lower sub-layer having a first stress induces a second stress on the upper sub-layer.

Abstract: In a nonvolatile memory device and a method of fabricating the same, a device isolation layer is formed defining an active region in a semiconductor substrate. A gate insulation layer and a first conductive layer are formed on the semiconductor substrate. A pair of stack patterns are formed, each having a intergate dielectric layer pattern and a second conductive layer pattern on the first conductive layer. A mask pattern is formed on the first conductive layer pattern between the stack patterns, the mask pattern being spaced apart from each of the stack patterns. The first conductive layer is patterned using the stack patterns and the mask patterns as an etching mask. Impurity ions are implanted into the active region to form a pair of nonvolatile memory transistors and a select transistor. The resulting nonvolatile memory device includes a memory cell unit that includes the pair of nonvolatile memory transistors and the select transistor.

Abstract: A cell includes a plurality of diffusion region pairs, each of the diffusion region pairs being formed by a first impurity diffusion region which is a constituent of a transistor and a second impurity diffusion region such that the first and second impurity diffusion regions are provided side-by-side in a gate length direction with a device isolation region interposed therebetween. In each of the diffusion region pairs, the first and second impurity diffusion regions have an equal length in the gate width direction and are provided at equal positions in the gate width direction, and a first isolation region portion, which is part of the device isolation region between the first and second impurity diffusion regions, has a constant separation length. In the diffusion region pairs, the first isolation region portions have an equal separation length.

Abstract: A method is provided of forming a trench isolation region adjacent to a single-crystal semiconductor region for a transistor. Such method can include, for example, recessing a single-crystal semiconductor region to define a first wall of the semiconductor region, a second wall remote from the first wall and a plurality of third walls extending between the first and second walls, each of the first and second walls extending in a first direction. In one embodiment, the first direction may be a <110> crystallographic direction of a wafer such as a silicon direction, for example. Oxidation-inhibiting regions can be formed at the first and second walls of the semiconductor region selectively with respect to the third walls. A dielectric region can then be formed adjacent to the first, second and third walls of the semiconductor region for a trench isolation region.

Abstract: Isolation regions are formed on a substrate to define an active region. A gate electrode is formed on the active region. A spacer structure is formed on a sidewall of the gate electrode. A gate silicide layer is formed on the gate electrode and a source/drain silicide layer is formed on the active region adjacent to the gate electrode. An upper portion of the gate silicide layer and a portion of the spacer structure are simultaneously removed to form a spacer structure pattern and a gate silicide layer pattern. A stress layer is formed to cover the gate electrode and spacer structure pattern.

Abstract: Element characteristics disadvantageously fluctuate because the composition of the resultant silicide varies according to the change of the gate length when a full silicide gate electrode is formed by sintering a metal/poly-Si structure. The element characteristics also fluctuate due to element-to-element non-uniformity of the resultant silicide composition. By first forming full silicide having a metal-rich composition, depositing a Si layer thereon, and sintering the combined structure, the metal in the metal-rich silicide diffuses into the Si layer, so that the Si layer is converted into silicide. The entire structure thus is converted into full silicide having a smaller metal composition ratio.

Abstract: A method of forming a shallow trench isolation region is provided. The method includes providing a semiconductor substrate comprising a top surface; forming an opening extending from the top surface into the semiconductor substrate; performing a conformal deposition method to fill a dielectric material into the opening; performing a first treatment on the dielectric material, wherein the first treatment provides an energy high enough for breaking bonds in the dielectric material; and performing a steam anneal on the dielectric material.

Abstract: Methods of forming coplanar active regions and isolation regions and structures thereof are disclosed. One embodiment includes shallow-trench-isolation (STI) formation in a semiconductor-on-insulator (SOI) layer on a substrate of a semiconductor structure; and bonding a handle wafer to the STI and SOI layer to form an intermediate structure. The intermediate structure may have a single layer including at least one STI region and at least one SOI region therein disposed between the damaged substrate and the handle wafer. The method may also include cleaving the hydrogen implanted substrate and removing any residual substrate to expose a surface of the at least one STI region and a surface of the at least one SOI region. The exposed surface of the at least one STI region forms an isolation region and the exposed surface of the at least one SOI region forms an active region, which are coplanar to each other.

Abstract: Methods of manufacturing a semiconductor device, which can reduce hot electron induced punchthrough (HEIP) and/or improve the operating characteristics of the device include selectively forming an oxynitride layer in a device isolation layer according to the characteristics of transistors isolated by the device isolation layer. The methods include forming first trenches and second trenches on a substrate, forming an oxide layer on the surfaces of the first trenches and the second trenches, selectively forming an oxynitride layer on the second trenches by using plasma ion immersion implantation (PIII), and forming a buried insulating layer in the first trenches and the second trenches. The buried insulating layer may be planarized to form a first device isolation layer in the first trenches and a second device isolation layer in the second trenches.

Abstract: A semiconductor device is manufactured by forming trenches in a substrate and selectively performing Plasma Ion Immersion Implantation and Deposition (PIIID) on a subset of the trenches in the substrate. The PIIID may be performed on only a portion of a surface of at least one of the trenches in the substrate. Semiconductor devices can include a semiconductor substrate having first, second and third trenches therein, and an oxide liner layer that fully lines the first trenches, that does not line the second trenches and that partially lines the third trenches.

Abstract: A first oxide film (102) is formed on a semiconductor substrate (101). A first nitride film (103) is formed on first gate electrode formation regions of the first oxide film (102). A plurality of first gate electrodes (104) are provided on the first nitride film (103) so as to be spaced apart from one another with a predetermined distance therebetween. A second oxide film (105) covers upper part and side walls of each of the first gate electrodes (104). A sidewall spacer (106) of a third oxide film is buried in an overhang portion generated on each side wall of each of the first gate electrodes (104) covered by the second oxide film (105). A second nitride film (107) covers the second oxide film (105), the sidewall spacer (106) and part of the first oxide film (102) located between the first gate electrodes (104). A plurality of second gate electrodes (108) are formed on at least part of the second nitride film (107) located between adjacent two of the first gate electrodes (104).

Abstract: A semiconductor chip 11 comprising an element formation layer which is formed on a first main surface 35A of a semiconductor substrate 35 and has a semiconductor element, through electrodes 15, 16 which are electrically connected to the semiconductor element and extend through the semiconductor chip 11, and a patch antenna 33 formed on the side of a second main surface 35B of the semiconductor substrate 35 are disposed, and the patch antenna 33 is electrically connected to the through electrode 15 electrically connected to a line for power feeding of the semiconductor element.

Abstract: A semiconductor component with at least one field plate. One embodiment provides the field plate to make contact with the semiconductor body at a connection contact. The semiconductor body has in the region of the connection contact a doping concentration that is less than 5·1017 cm?3.