Read-only Memory Structures (rom), I.e., Nonvolatile Memory Structures (epo) Patents (Class 257/E21.662)

  • Publication number: 20090112009
    Abstract: Germanium, tellurium, and/or antimony precursors are usefully employed to form germanium-, tellurium- and/or antimony-containing films, such as films of GeTe, GST, and thermoelectric germanium-containing films. Processes for using these precursors to form amorphous films are also described. Further described is the use of [{nBuC(iPrN)2}2Ge] or Ge butyl amidinate to form GeTe smooth amorphous films for phase change memory applications.
    Type: Application
    Filed: October 31, 2008
    Publication date: April 30, 2009
    Applicant: Advanced Technology Materials, Inc.
    Inventors: Philip S.H. Chen, William Hunks, Tianniu Chen, Matthias Stender, Chongying Xu, Jeffrey F. Roeder, Weimin Li
  • Patent number: 7521751
    Abstract: To provide a nonvolatile memory device suppressing a reduction of a data retention characteristic even if charges injected and stored into a local area of a nitride film is redistributed to achieve a reduction of voltage, the nonvolatile memory device in which hot electrons are injected into the local area of the nitride film at one or both of source•drain regions side to store data in a memory transistor is satisfied with a standard for evaluating a film quality of the nitride film, the standard being defined by one of the followings: a density of the bond group of silicon and hydrogen being under 1×1021 cm?3; an extinction coefficient in an ultraviolet region at a wavelength of 240 nm being under 0.10 or the extinction coefficient in 230 nm being under 0.14; an optical energy, a peak wavelength of an luminance spectrum, or a peak energy thereof.
    Type: Grant
    Filed: September 16, 2005
    Date of Patent: April 21, 2009
    Assignee: Sony Corporation
    Inventor: Ichiro Fujiwara
  • Patent number: 7521743
    Abstract: Disclosed is a nonvolatile magnetic memory device including a magntoresistance device having a recording layer formed of a ferromagnetic material for storing information by use of variation in resistance depending on the magnetization inversion state. The plan-view shape of the recording layer includes a pseudo-rhombic shape having four sides, at least two of the four sides each include a smooth curve having a central portion curved toward the center of the pseudo-rhombic shape. The easy axis of magnetization of the recording layer is substantially parallel to the longer axis of the pseudo-rhombic shape. The hard axis of magnetization of the recording layer is substantially parallel to the shorter axis of the pseudo-rhombic shape. The sides constituting the plan-view shape of the recording layer are smoothly connected to each other.
    Type: Grant
    Filed: June 8, 2005
    Date of Patent: April 21, 2009
    Assignee: Sony Corporation
    Inventor: Hajime Yamagishi
  • Patent number: 7510929
    Abstract: A memory cell device, including a memory material element switchable between electrical property states by the application of energy, includes depositing an electrical conductor layer, depositing dielectric material layers and etching to create a first electrode and voids. A memory material is applied into a void to create a memory material element in contact with the first electrode. A second electrode is created to contact the memory material element.
    Type: Grant
    Filed: October 18, 2006
    Date of Patent: March 31, 2009
    Assignee: Macronix International Co., Ltd.
    Inventor: Chieh Fang Chen
  • Publication number: 20090053866
    Abstract: A p-type source region 2 and a p-type drain region 3 are formed on the surface of an n-type semiconductor layer 1. In the position located above a channel region interposed between the p-type source region 2 and the p-type drain region 3 and overlapping the p-type drain region 3, a charge accumulation electrode 5 is formed with a tunnel oxide film 4 interposed therebetween. In the position located above the channel region interposed between the p-type source region 2 and the p-type drain region 3 and overlapping the p-type source region 2, a select electrode 7 is formed with an insulating film 6 interposed therebetween. Above the charge accumulation electrode 5, a control electrode 9 is formed with the insulating film 8 interposed therebetween.
    Type: Application
    Filed: September 18, 2008
    Publication date: February 26, 2009
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Keiichi Hirooka, Katsujirou Arai
  • Patent number: 7491573
    Abstract: A memory device utilizing a phase change material as the storage medium, the phase change material based on antimony as the solvent in a solid solution.
    Type: Grant
    Filed: March 13, 2008
    Date of Patent: February 17, 2009
    Assignee: International Business Machines Corporation
    Inventors: Alejandro G Schrott, Chung H Lam, Simone Raoux, Chieh-Fang Chen
  • Publication number: 20090032891
    Abstract: A structure of magnetic random access memory includes a magnetic memory cell formed on a substrate. An insulating layer covers over the substrate and the magnetic memory cell. A write current line is in the insulating layer and above the magnetic memory cell. A magnetic cladding layer surrounds the periphery of the write current line. The magnetic cladding layer includes a first region surrounding the top of the write current line, and a second region surrounding the side edge of the write current line, and extending towards the magnetic memory cell and exceed by a distance.
    Type: Application
    Filed: December 12, 2007
    Publication date: February 5, 2009
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Cheng-Tyng Yen, Wei-Chuan Chen, Yung-Hsiang Chen, Yung-Hung Wang
  • Publication number: 20090003082
    Abstract: A method of making a two terminal nonvolatile memory cell includes forming a first electrode, forming a charge storage medium, forming a resistive element, and forming a second electrode. The charge storage medium and the resistive element are connected in parallel between the first and the second electrodes, and a presence or absence of charge being stored in the charge storage medium affects a resistivity of the resistive element.
    Type: Application
    Filed: June 28, 2007
    Publication date: January 1, 2009
    Inventors: Albert Meeks, Xiaoyu Yang, Kim Le
  • Publication number: 20090003070
    Abstract: A semiconductor memory device includes a memory cell string provided on a semiconductor substrate, and a first select transistor including a gate insulation film, which is provided on the semiconductor substrate having a recess structure which is lower, only at a central portion thereof, than the semiconductor substrate on which the memory cell string is provided, and a gate electrode provided on the gate insulation film, the first select transistor selecting the memory cell string.
    Type: Application
    Filed: October 9, 2007
    Publication date: January 1, 2009
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kenji Gomikawa, Kenji Sawamura, Mitsuhiro Noguchi
  • Publication number: 20080296650
    Abstract: A metal oxide semiconductor (MOS) structure having a high dielectric constant gate insulator layer containing gold (Au) nano-particles is presented with methods for forming the layer with high step coverage of underlying topography, high surface smoothness, and uniform thickness. The transistor may form part of a logic device, a memory device, a persistent memory device, a capacitor, as well as other devices and systems. The insulator layer may be formed using atomic layer deposition (ALD) to reduce the overall device thermal exposure. The insulator layer may be formed of a metal oxide, a metal oxycarbide, a semiconductor oxide, or semiconductor oxide oxycarbide, and the gold nano-particles in insulator layer increase the work function of the insulator layer and affect the tunneling current and the threshold voltage of the transistor.
    Type: Application
    Filed: June 4, 2007
    Publication date: December 4, 2008
    Inventors: Kie Y. Ahn, Leonard Forbes
  • Publication number: 20080272424
    Abstract: Disclosed herein is a nonvolatile memory device that includes a substrate, a tunneling layer over the substrate, a charge trapping layer over the tunneling layer, an insulating layer for improving retention characteristics over the charge trapping layer, a blocking layer over the insulating layer, and a control gate electrode over the blocking layer. Also disclosed herein is a method of making the device.
    Type: Application
    Filed: November 15, 2007
    Publication date: November 6, 2008
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventors: Yong Top Kim, Hong Seon Yang, Tae Yoon Kim, Yong Soo Kim, Seung Ryong Lee, Moon Sig Joo
  • Patent number: 7427536
    Abstract: A non-planar, stepped NROM array is comprised of cells formed in trenches and on pillars that are etched into a substrate. Each cell has a plurality of charge storage regions in its nitride layer and a pair of source/drain regions that are shared with adjacent cells in a column. The source/drain regions, formed in the pillar/trench sidewalls, couple the column cells serially into bitlines. The rows of the array are each coupled by a wordline. A second set of trenches separates the columns of cells.
    Type: Grant
    Filed: April 7, 2006
    Date of Patent: September 23, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Leonard Forbes, Kie Y. Ahn
  • Patent number: 7422932
    Abstract: A nonvolatile semiconductor memory device includes a semiconductor substrate, a memory cell region which is disposed on the semiconductor substrate and has a transistor array of a stacked gate structure having a floating gate, a Ti-containing barrier which is disposed in an upper layer of the memory cell region and covers the memory cell region, and a passivation layer disposed above the Ti-containing barrier.
    Type: Grant
    Filed: September 11, 2006
    Date of Patent: September 9, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuo Saito, Shogo Takamura
  • Patent number: 7419868
    Abstract: A gated diode nonvolatile memory cell with a charge storage structure includes a diode structure with an additional gate terminal. Various embodiments may include or exclude a diffusion barrier structure between the diode nodes. Example embodiments include the individual memory cell, an array of such memory cells, methods of operating the memory cell or array of memory cells, and methods of manufacturing the same.
    Type: Grant
    Filed: January 2, 2007
    Date of Patent: September 2, 2008
    Assignee: Macronix International Co., Ltd.
    Inventors: Tien Fan Ou, Wen Jer Tsai, Erh-Kun Lai, Hsuan Ling Kao
  • Patent number: 7358120
    Abstract: A silicon-on-insulator (SOI) Read Only Memory (ROM), and a method of making the SOI ROM. ROM cells are located at the intersections of stripes in the surface SOI layer with orthogonally oriented wires on a conductor layer. Contacts from the wires connect to ROM cell diodes in the upper surface of the stripes. ROM cell personalization is the presence or absence of a diode and/or contact.
    Type: Grant
    Filed: February 7, 2007
    Date of Patent: April 15, 2008
    Assignee: International Business Machines Corporation
    Inventors: Toshiharu Furukawa, Mark C. Hakey, Steven J. Holmes, David V. Horak, Charles W. Koburger, III, Jack A. Mandelman
  • Publication number: 20080019165
    Abstract: A one time programmable memory cell having a gate, a gate dielectric layer, a source region, a drain region, a capacitor dielectric layer and a conductive plug is provided herein. The gate dielectric layer is disposed on a substrate. The gate is disposed on the gate dielectric layer. The source region and the drain region are disposed in the substrate at the sides of the gate, respectively. The capacitor dielectric layer is disposed on the source region. The capacitor dielectric layer is a resistive protection oxide layer or a self-aligned salicide block layer. The conductive plug is disposed on the capacitor dielectric layer. The conductive plug is served as a first electrode of a capacitor and the source region is served as a second electrode of the capacitor. The one time programmable memory (OTP) cell is programmed by making the capacitor dielectric layer breakdown.
    Type: Application
    Filed: April 5, 2007
    Publication date: January 24, 2008
    Applicant: EMEMORY TECHNOLOGY INC.
    Inventors: Chrong-Jung Lin, Hsin-Ming Chen, Ya-Chin King
  • Publication number: 20080020530
    Abstract: A manufacturing method of a semiconductor device disclosed herein, comprises: forming a first member to be patterned on a semiconductor substrate; forming a second member to be patterned on the first member; forming a third member to be patterned on the second member; patterning the third member to form a first line pattern and a first connecting portion in the third member, the first line pattern having a plurality of parallel linear patterns and the first connecting portion connecting the linear patterns on at least one end side of the linear patterns of the first line pattern; etching the second member with the third member as a mask to form a second line pattern and a second connecting portion in the second member, the second line pattern being the same pattern as the first line pattern and the second connecting portion being the same pattern as the first connecting portion; removing the second connecting portion of the second member; and etching the first member with the second member as a mask.
    Type: Application
    Filed: July 27, 2007
    Publication date: January 24, 2008
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Hideyuki Kinoshita
  • Patent number: 7312490
    Abstract: Method and apparatus are described for a memory cell includes a substrate, a body extending vertically from the substrate, a first gate having a vertical member and a horizontal member and a second gate comprising a vertical member and a horizontal member. The first gate is disposed laterally from the body and the second gate is disposed laterally from the first gate. The horizontal member of the first gate overlaps the horizontal member of the second gate.
    Type: Grant
    Filed: March 31, 2005
    Date of Patent: December 25, 2007
    Assignee: Intel Corporation
    Inventors: Jun-Fei Zheng, Pranav Kalavade
  • Publication number: 20070275509
    Abstract: A method of manufacturing a NOR-type mask ROM device includes forming a first gate electrode for an OFF cell and a second gate electrode for an ON cell on a semiconductor substrate of a first conductivity type. To code the mask ROM device, a plurality of source/drain regions is formed by implanting impurities of a second conductivity type, opposite the first conductivity type, into the semiconductor substrate adjacent only to one side of the first gate electrode and adjacent to both sides of the second gate electrode. To prevent misalignment of a bit line contact hole with a contact region, additional impurities are implanted only into a bit line contact region of the mask ROM device region. When a semiconductor device formed on the same substrate as the mask ROM device includes a double diffused region, additional implantation for both may be realized simultaneously.
    Type: Application
    Filed: August 3, 2007
    Publication date: November 29, 2007
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyun-Khe Yoo, Weon-ho Park, Byoung-ho Kim
  • Patent number: 7279736
    Abstract: Nonvolatile memory devices and methods of fabricating and driving the same are disclosed. Disclosed devices and method comprises: growing an oxide layer on a substrate and depositing a nitride layer on the oxide layer; patterning the nitride layer; forming injection gates on the lateral faces of the nitride layer; depositing a first polysilicon, a dielectric layer and a second polysilicon on the surface of the resulting structure, sequentially; patterning the second polysilicon, the dielectric layer and the second polysilicon to form gate electrodes; removing the nitride layer between the injection gates; forming source and drain extension regions around each of the gate electrodes by performing an ion implantation process; forming sidewall spacers on the lateral faces of the gate electrodes; and forming source and drain regions in the substrate by performing an ion implantation process with the sidewall spacers as an ion implantation mask.
    Type: Grant
    Filed: December 27, 2004
    Date of Patent: October 9, 2007
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Jin Hyo Jung
  • Patent number: 7265409
    Abstract: A non-volatile semiconductor memory having a memory transistor including a stacked-layer film formed between a semiconductor substrate and a gate electrode and having a charge storage ability, a first conductivity type region of the semiconductor substrate in which a channel is formed under the control of the gate electrode via the stacked-layer film, and two second conductivity type regions formed at the semiconductor substrate sandwiching the first conductivity type region therebetween, the memory transistor having a channel length L which is between channel lengths L1 and L2. with the channel length L1 being estimated as the boundary of occurrence of a short channel effect at the time of a write operation and the channel length L2 the time of a read operation, with the channel length L1 being different from the channel length L2.
    Type: Grant
    Filed: June 14, 2005
    Date of Patent: September 4, 2007
    Assignee: Sony Corporation
    Inventors: Toshio Kobayashi, Hideto Tomiie
  • Patent number: 7256444
    Abstract: Provided are a local SONOS-type memory device and a method of manufacturing the same. The device includes a gate oxide layer formed on a silicon substrate; a conductive spacer and a dummy spacer, which are formed on the gate oxide layer and separated apart from each other, the conductive spacer and the dummy spacer having round surfaces that face outward; a pair of insulating spacers formed on a sidewall of the conductive spacer and a sidewall of the dummy spacer which face each other; an ONO layer formed in a self-aligned manner between the pair of insulating spacers; a conductive layer formed on the ONO layer in a self-aligned manner between the pair of insulating spacers; and source and drain regions formed in the silicon substrate outside the conductive spacer and the dummy spacer.
    Type: Grant
    Filed: March 1, 2006
    Date of Patent: August 14, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong-suk Choi, Seung-beom Yoon, Seong-gyun Kim
  • Patent number: 7247539
    Abstract: A manufacturing method of a semiconductor device disclosed herein, comprises: forming a first member to be patterned on a semiconductor substrate; patterning the first member to be patterned to form a plurality of parallel linear patterns and a connecting portion which connects the linear patterns on at least one end side of the linear patterns; and etching a region between the linear patterns and the connecting portion to separate the linear patterns and the connecting portion.
    Type: Grant
    Filed: January 13, 2005
    Date of Patent: July 24, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hideyuki Kinoshita
  • Patent number: 7244981
    Abstract: A plurality of select gates are formed over a substrate. In one embodiment, the select gates are formed vertically on the sidewalls of trenches. The substrate includes a plurality of diffusion regions that are each formed between a pair of planar select gates. In a vertical embodiment, the diffusion regions are formed at the bottom of the trenches and the tops of the mesas formed by the trenches. An enriched region is formed in the substrate adjacent to and substantially surrounding each diffusion region in the substrate. Each enriched region has a matching conductivity type with the substrate. A gate insulator stack is formed over the substrate and each of the plurality of select gates. A word line is formed over the gate insulator stack.
    Type: Grant
    Filed: February 25, 2005
    Date of Patent: July 17, 2007
    Assignee: Micron Technology, Inc.
    Inventor: Arup Bhattacharyya
  • Patent number: 7227233
    Abstract: A silicon-on-insulator (SOI) Read Only Memory (ROM), and a method of making the SOI ROM. ROM cells are located at the intersections of stripes in the surface SOI layer with orthogonally oriented wires on a conductor layer. Contacts from the wires connect to ROM cell diodes in the upper surface of the stripes. ROM cell personalization is the presence or absence of a diode and/or contact.
    Type: Grant
    Filed: September 12, 2005
    Date of Patent: June 5, 2007
    Assignee: International Business Machines Corporation
    Inventors: Toshiharu Furukawa, Mark C. Hakey, Steven J. Holmes, David V. Horak, Charles W. Koburger, III, Jack A. Mandelman
  • Patent number: 7202523
    Abstract: An NROM flash memory cell is implemented in an ultra-thin silicon-on-insulator structure. In a planar device, the channel between the source/drain areas is normally fully depleted. An oxide layer provides an insulation layer between the source/drain areas and the gate insulator layer on top. A control gate is formed on top of the gate insulator layer. In a vertical device, an oxide pillar extends from the substrate with a source/drain area on either side of the pillar side. Epitaxial regrowth is used to form ultra-thin silicon body regions along the sidewalls of the oxide pillar. Second source/drain areas are formed on top of this structure. The gate insulator and control gate are formed on top.
    Type: Grant
    Filed: November 17, 2003
    Date of Patent: April 10, 2007
    Assignee: Micron Technology, Inc.
    Inventor: Leonard Forbes
  • Publication number: 20060249735
    Abstract: There is provided a monolithic three dimensional TFT mask ROM array. The array includes a plurality of device levels. Each of the plurality of device levels contains a first set of enabled TFTs and a second set of partially or totally disabled TFTs.
    Type: Application
    Filed: July 12, 2006
    Publication date: November 9, 2006
    Inventors: Andrew Walker, Christopher Petti
  • Patent number: 7129135
    Abstract: A first conductive film for forming a plurality of word lines is formed in a memory cell array formation region of a semiconductor substrate for a nonvolatile semiconductor memory device, and a second conductive film is formed in a semiconductor device formation region of the semiconductor substrate. Next, openings are formed in the first conductive film by a first dry etching process such that the word lines in the memory cell array formation region are located apart from one another. Thereafter, sidewall insulating films for the word lines are formed in the openings. Next, parts of the sidewall insulating films located adjacent to the ends of the word lines are removed by wet etching. Next, a part of the first conductive film located around a word line formation region is removed by a second dry etching process.
    Type: Grant
    Filed: August 3, 2005
    Date of Patent: October 31, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Yoshinori Odake
  • Patent number: 7112486
    Abstract: The present invention provides a method for fabricating a semiconductor device having a dual gate dielectric structure capable of obtaining a simplified process and improving device reliability. The method includes the steps of: forming an insulation layer on a substrate; forming a nitride layer on the insulation layer; selectively etching the nitride layer in a predetermined region of the substrate; performing a radical oxidation process to form an oxide layer on the insulation layer and the etched nitride layer; forming a gate conductive layer on the oxide layer; and performing a selective etching process to the gate conductive layer, the oxide layer, the nitride layer and the insulation layer, so that the first dielectric structure formed in the predetermined region includes the insulation layer and the oxide layer and the second gate dielectric structure formed in regions other than the predetermined region includes the insulation layer, the nitride layer and the oxide layer.
    Type: Grant
    Filed: December 20, 2004
    Date of Patent: September 26, 2006
    Assignee: Hynix Semiconductor Inc.
    Inventors: Heung-Jae Cho, Se-Aug Jang, Kwan-Yong Lim, Jae-Geun Oh, Hong-Seon Yang, Hyun-Chul Shon