Abstract: In a semiconductor device by which peripheral circuit sections, such as a semiconductor element, a matching circuit section, a bias circuit section, a capacitor element, are placed on and connected to a substrate, the semiconductor element can be grounded, and the semiconductor device which can make heat radiation characteristics of the semiconductor element satisfactory is provided, without providing a via hole into a semiconductor substrate. It includes: a semiconductor element (2) placed on a substrate (1); peripheral circuit sections (30) and (40) placed on the substrate (1) and connected with the semiconductor element (2); an electrode (30e) provided in the peripheral circuit section (30) and grounded; an electrode (30s) for grounding connected to a metal layer (30m), a metal layer (30m) and a source electrode (2s) of the semiconductor element (2); and an electrode (30d) connected to a gate electrode (2g) of the semiconductor element (2).

Abstract: A semiconductor substrate having a first side and a second side made of single crystal silicon carbide is prepared. A mask layer having a plurality of openings and made of silicon oxide is formed on the second side. The plurality of openings expose a plurality of regions included in the second side, respectively. A plurality of diamond portions are formed by epitaxial growth on the plurality of regions, respectively. The epitaxial growth is stopped before the plurality of diamond portions come into contact with each other. A Schottky electrode is formed on each of the plurality of diamond portions. An ohmic electrode is formed on the first side.

Abstract: A semiconductor device including an oxide semiconductor can have stable electric characteristics and high reliability. A transistor in which an oxide semiconductor layer containing indium, titanium, and zinc is used as a channel formation region and a semiconductor device including the transistor are provided. As a buffer layer in contact with the oxide semiconductor layer, a metal oxide layer containing an oxide of one or more elements selected from titanium, aluminum, gallium, zirconium, hafnium, and a rare earth element can be used.

Abstract: A Graphene Flash Memory (GFM) device is disclosed. In general, the GFM device includes a number of memory cells, where each memory cell includes a graphene channel, a graphene storage layer, and a graphene electrode. In one embodiment, by using a graphene channel, graphene storage layer, and graphene electrode, the memory cells of the GFM device are enabled to be scaled down much more than memory cells of a conventional flash memory device. More specifically, in one embodiment, the GFM device has a feature size less than 25 nanometers, less than or equal to 20 nanometers, less than or equal to 15 nanometers, less than or equal to 10 nanometers, or less than or equal to 5 nanometers.

Abstract: The present invention is related to the field of semiconductor processing and, more particularly, to the formation of low resistance layers on germanium substrates. One aspect of the present invention is a method comprising: providing a substrate on which at least one area of a germanium layer is exposed; depositing over the substrate and said germanium area a metal, e.g., Co or Ni; forming over said metal, a capping layer consisting of a silicon oxide containing layer, of a silicon nitride layer, or of a tungsten layer, preferably of a SiO2 layer; then annealing for metal-germanide formation; then removing selectively said capping layer and any unreacted metal, wherein the temperature used for forming said capping layer formation is lower than the annealing temperature.

Abstract: A semiconductor device which is downsized while a short-channel effect is suppressed and whose power consumption is reduced is provided. A downsized SRAM circuit is formed, which includes a first inverter including a first transistor and a second transistor overlapping with each other; a second inverter including a third transistor and a fourth transistor overlapping with each other; a first selection transistor; and a second selection transistor. An output terminal of the first inverter, an input terminal of the second inverter, and one of a source and a drain of the first selection transistor are connected to one another, and an output terminal of the second inverter, an input terminal of the first inverter, and one of a source and a drain of the second selection transistor are connected to one another.

Abstract: A transistor may include an active layer having a plurality of oxide semiconductor layers and an insulating layer disposed therebetween. The insulating layer may include a material that has higher etch selectivity with respect to at least one of the plurality of oxide semiconductor layers. The electronic device may include a first transistor and a second transistor connected to the first transistor. The second transistor may include an active layer having a different structure from that of the active layer included in the first transistor. The active layer of the second transistor may have the same structure as one of the plurality of oxide semiconductor layers constituting the active layer of the first transistor.

Abstract: In an oxide semiconductor film formed over an insulating surface, an amorphous region remains in the vicinity of the interface with the base, which is thought to cause a variation in the characteristics of a transistor and the like. A base surface or film touching the oxide semiconductor film is formed of a material having a melting point higher than that of a material used for the oxide semiconductor film. Accordingly, a crystalline region is allowed to exist in the vicinity of the interface with the base surface or film touching the oxide semiconductor film. An insulating metal oxide is used for the base surface or film touching the oxide semiconductor film. The metal oxide used here is an aluminum oxide, gallium oxide, or the like that is a material belonging to the same group as the material of the oxide semiconductor film.

Abstract: The object is to suppress deterioration in electrical characteristics in a semiconductor device comprising a transistor including an oxide semiconductor layer. In a transistor in which a channel layer is formed using an oxide semiconductor, a p-type silicon layer is provided in contact with a surface of the oxide semiconductor layer. Further, the p-type silicon layer is provided in contact with at least a region of the oxide semiconductor layer, in which a channel is formed, and a source electrode layer and a drain electrode layer are provided in contact with regions of the oxide semiconductor layer, over which the p-type silicon layer is not provided.

Abstract: In a method for making a GaN article, an epitaxial nitride layer is deposited on a single-crystal substrate. A 3D nucleation GaN layer is grown on the epitaxial nitride layer by HVPE under a substantially 3D growth mode. A GaN transitional layer is grown on the 3D nucleation layer by HVPE under a condition that changes the growth mode from the substantially 3D growth mode to a substantially 2D growth mode. A bulk GaN layer is grown on the transitional layer by HVPE under the substantially 2D growth mode. A polycrystalline GaN layer is grown on the bulk GaN layer to form a GaN/substrate bi-layer. The GaN/substrate bi-layer may be cooled from the growth temperature to an ambient temperature, wherein GaN material cracks laterally and separates from the substrate, forming a free-standing article.

Abstract: A semiconductor device which is designed based on RDR, suppresses the occurrence of a trouble at the boundary between an active region and a power wire and therearound and is small in size and highly integrated. The semiconductor device includes a first conductive impurity region for functional elements which is formed over the main surface of a semiconductor substrate and a second conductive impurity region for power potential to which power potential is applied in at least one standard cell. It also includes insulating layers which are formed over the main surface of the semiconductor substrate and have throughholes reaching the main surface of the semiconductor substrate, and a conductive layer for contact formed in the throughholes of the insulating layers.

Abstract: An example embodiment relates to a method of manufacturing an array of electric devices that includes attaching a platform including a micro-channel structure to a substrate. The method includes injecting first and second solutions into the micro-channel structure to form at least three liquid film columns, where the first and second solutions include different solvent composition ratios and the liquid columns each, respectfully, include different solvent composition ratios. The method further includes detaching the platform the substrate, removing solvent from the liquid film columns to form thin film columns, and treating the thin film columns under different conditions along a length direction of the thin film columns. The solvent is removed from the thin film columns and the thin film columns are treated under different conditions along a length direction of the thin film columns.

Abstract: Nonvolatile memory elements are provided that have resistive switching metal oxides. The nonvolatile memory elements may be formed by depositing a metal-containing material on a silicon-containing material. The metal-containing material may be oxidized to form a resistive-switching metal oxide. The silicon in the silicon-containing material reacts with the metal in the metal-containing material when heat is applied. This forms a metal silicide lower electrode for the nonvolatile memory element. An upper electrode may be deposited on top of the metal oxide. Because the silicon in the silicon-containing layer reacts with some of the metal in the metal-containing layer, the resistive-switching metal oxide that is formed is metal deficient when compared to a stoichiometric metal oxide formed from the same metal.

Abstract: A repair layer forming process includes the following steps. Firstly, a substrate is provided, and a gate structure is formed on the substrate, wherein the gate structure at least includes a gate dielectric layer and a gate conductor layer. Then, a nitridation process is performed to form a nitrogen-containing superficial layer on a sidewall of the gate structure. Then, a thermal oxidation process is performed to convert the nitrogen-containing superficial layer into a repair layer. Moreover, a metal-oxide-semiconductor transistor includes a substrate, a gate dielectric layer, a gate conductor layer and a repair layer. The gate dielectric layer is formed on the substrate. The gate conductor layer is formed on the gate dielectric layer. The repair layer is at least partially formed on a sidewall of the gate conductor layer.

Abstract: A graphene structure and a method of manufacturing the graphene structure, and a graphene device and a method of manufacturing the graphene device. The graphene structure includes a substrate; a growth layer disposed on the substrate and having exposed side surfaces; and a graphene layer disposed on the side surfaces of the growth layer.

Abstract: A light-emitting device in which reduction in performance due to moisture is suppressed is provided. The light-emitting device has a structure in which a partition having a porous structure surrounds each of light-emitting elements. The partition having a porous structure physically adsorbs moisture; therefore, in the light-emitting device, the partition functions as a hygroscopic film at a portion extremely close to the light-emitting element, so that moisture or water vapor remaining in the light-emitting device or entering from the outside can be effectively adsorbed. Thus, reduction in performance of the light-emitting device due to moisture or water vapor can be effectively suppressed.

Abstract: A suspension or solution for an organic optoelectronic device is disclosed. The composition of the suspension or solution includes at least one kind of micro/nano transition metal oxide and a solvent. The composition of the suspension or solution can selectively include at least one kind of transition metal oxide ions or a precursor of transition metal oxide. Moreover, the method of making and applications of the suspension or solution are also disclosed.

Abstract: An undoped AlGaN layer 13 is formed on a buffer layer composed of a GaN series material formed on a semiconductor substrate, a drain electrode 15 and a source electrode 16 forming ohmic junction with the undoped AlGaN layer 13 are formed separately from each other on the undoped AlGaN layer 13. A gate electrode 17 composed of metal Ni and Au laminated in this order is formed between the drain electrodes 15 and the source electrode 16 on the undoped AlGaN layer 13. The end portion 17-2 of the gate electrode 17 is formed on the underlying metal 18 formed by a metal containing Ti via an insulating film 14 on a GaN buffer layer 12 surrounding the undoped AlGaN layer 13.

Abstract: A group III nitride-based transistor capable of achieving terahertz-range cutoff and maximum frequencies of operation at relatively high drain voltages is provided. In an embodiment, two additional independently biased electrodes are used to control the electric field and space-charge close to the gate edges.

Abstract: A semiconductor device and manufacturing method therefor includes a ?-shaped embedded source or drain regions. A U-shaped recess is formed in a Si substrate using dry etching and a SiGe layer is grown epitaxially on the bottom of the U-shaped recess. Using an orientation selective etchant having a higher etching rate with respect to Si than SiGe, wet etching is performed on the Si substrate sidewalls of the U-shaped recess, to form a ?-shaped recess.

Abstract: An electrostatic discharge (ESD) protection element includes a collector area, a first barrier area, a semiconductor area, a second barrier area and an emitter area. The collector area has a first conductivity type. The first barrier area borders on the collector area and has a second conductivity type. The semiconductor area borders on the first barrier area and is an intrinsic semiconductor area, or has the first or second conductivity type and a dopant concentration which is lower than a dopant concentration of the first barrier area. The second barrier area borders on the semiconductor area and has the second conductivity type and a higher dopant concentration than the semiconductor area. The emitter area borders on the second barrier area and has the first conductivity type.

Abstract: A semiconductor chip comprises: a semiconductor structure having a single crystal substrate having a non-cubic crystallographic structure and epitaxial layers disposed on the substrate wherein adjacent sides of the semiconductor structure are at oblique angles. A method for separating a plurality of integrated circuit chips. The method includes: providing a semiconductor wafer having single crystal substrate, such substrate having a non-cubic crystallographic structure with an epitaxial layer disposed on the substrate; forming scribe lines at oblique angles to one another in the epitaxial layer; and cutting or cleaving through the substrate along the scribe lines to separate the chips.

Abstract: One embodiment of the present invention provides a highly reliably display device in which a high mobility is achieved in an oxide semiconductor. A first oxide component is formed over a base component. Crystal growth proceeds from a surface toward an inside of the first oxide component by a first heat treatment, so that a first oxide crystal component is formed in contact with at least part of the base component. A second oxide component is formed over the first oxide crystal component. Crystal growth is performed by a second heat treatment using the first oxide crystal component as a seed, so that a second oxide crystal component is formed. Thus, a stacked oxide material is formed. A transistor with a high mobility is formed using the stacked oxide material and a driver circuit is formed using the transistor.

Abstract: The present invention describes a hybrid integrated circuit comprising both CMOS and III-V devices, monolithically integrated in a single chip. It allows the almost complete elimination of the contamination issues related to the integration of different technologies, maintaining at the same time a good planarization of the structure. It further simplifies the fabrication process, allowing the growth of high quality III-V materials on (100) silicon substrates lowering the manufacturing cost. Moreover, differently from many prior art attempts, it does not require silicon on insulator technologies and/or other expensive process steps. This invention enables the consolidation on the same integrated circuit of a hybrid switching power converter that takes advantage of the established circuit topologies of CMOS circuitries and of the higher mobility and voltage withstanding of III-V HEMT devices.

Abstract: It is an object to manufacture a highly reliable semiconductor device including a thin film transistor whose electric characteristics are stable. An insulating layer which covers an oxide semiconductor layer of the thin film transistor contains a boron element or an aluminum element. The insulating layer containing a boron element or an aluminum element is formed by a sputtering method using a silicon target or a silicon oxide target containing a boron element or an aluminum element. Alternatively, an insulating layer containing an antimony (Sb) element or a phosphorus (P) element instead of a boron element covers the oxide semiconductor layer of the thin film transistor.

Abstract: Disclosed is a highly reliable semiconductor device and a manufacturing method thereof, which is achieved by using a transistor with favorable electrical characteristics and high reliability as a switching element. The semiconductor device includes a driver circuit portion and a pixel portion over one substrate, and the pixel portion comprises a light-transmitting bottom-gate transistor. The light-transmitting bottom-gate transistor comprises: a transparent gate electrode layer; an oxide semiconductor layer over the gate electrode layer, a superficial layer of the oxide semiconductor layer including comprising a microcrystal group of nanocrystals; and source and drain electrode layers formed over the oxide semiconductor layer, the source and drain electrode layers comprising a light-transmitting oxide conductive layer.

Abstract: A wafer processing method includes the steps of: (a) annealing a silicon wafer at a temperature higher than 650° C.; (b) after step (a), depositing a silicon-germanium layer on the silicon wafer; (c) after step (b), implanting oxygen ions into the silicon wafer; and (d) after step (c), annealing the silicon wafer at a temperature higher than 650° C. to form a silicon oxide layer underneath the silicon-germanium layer.

Abstract: Semiconductor devices are formed with a thin layer of fully strain relaxed epitaxial silicon germanium on a substrate. Embodiments include forming a silicon germanium (SiGe) epitaxial layer on a semiconductor substrate, implanting a dopant into the SiGe epitaxial layer, and annealing the implanted SiGe epitaxial layer.

Abstract: An object is to increase an aperture ratio of a semiconductor device. The semiconductor device includes a driver circuit portion and a display portion (also referred to as a pixel portion) over one substrate. The driver circuit portion includes a channel-etched thin film transistor for a driver circuit, in which a source electrode and a drain electrode are formed using metal and a channel layer is formed of an oxide semiconductor, and a driver circuit wiring formed using metal. The display portion includes a channel protection thin film transistor for a pixel, in which a source electrode layer and a drain electrode layer are formed using an oxide conductor and a semiconductor layer is formed of an oxide semiconductor, and a display portion wiring formed using an oxide conductor.

Abstract: A semiconductor device includes a p-type semiconductor layer and an n-type semiconductor layer that are joined by sandwiching a depletion layer with a thickness that allows transmission of a plurality of electrons and holes by direct-tunneling.

Abstract: According to one embodiment, a semiconductor light emitting device includes a first semiconductor layer of a first conductivity type and having a major surface, a second semiconductor layer of a second conductivity type, and a light emitting layer provided between the first and second semiconductor layers. The major surface is opposite to the light emitting layer. The first semiconductor layer has structural bodies provided in the major surface. The structural bodies are recess or protrusion. A centroid of a first structural body aligns with a centroid of a second structural body nearest the first structural. hb, rb, and Rb satisfy rb/(2·hb)?0.7, and rb/Rb<1, where hb is a depth of the recess, rb is a width of a bottom portion of the recess, and Rb is a width of the protrusion.

Abstract: The present invention makes it possible to lower the on resistance of a semiconductor element without hindering the function of a diffusion prevention film in a semiconductor device having the semiconductor element that uses a wire in a wiring layer as a gate electrode and has a gate insulation film in an identical layer to the diffusion prevention film. A first wire and a gate electrode are embedded into the surface layer of an insulation layer comprising a first wiring layer. A diffusion prevention film is formed between the first wiring layer and a second wiring layer. A gate insulation film is formed by: forming a recess over the upper face of the diffusion prevention film in the region overlapping with the gate electrode and around the region; and thinning the part.

Abstract: It is disclosed that a semiconductor device includes an oxide semiconductor layer provided over a gate insulating layer, a source electrode layer, and a drain electrode layer, in which a thickness of the gate insulating layer located in a region between the source electrode layer and the drain electrode layer is smaller than a thickness of the gate insulating layer provided between the gate electrode layer and at least one of the source electrode layer and the drain electrode layer.

Abstract: A high-voltage electronic device comprising high-voltage electrodes, located in a dielectric envelope with an internal surface coated with a material having a conductivity which is greater than the conductivity of the envelope, characterized in that the areas subject to high field strength are coated with composite material, based on a polycrystalline material with a bulk conductivity of particles 10?9 to 10?13 Ohm?1 cm?1, each of which contains a surface nanolayer of bonding inorganic material. The high-voltage electrodes may be placed in a vacuum envelope and fixed on coated insulators. Preferred coating materials include materials from a group of materials comprising; oxides of chromium, boron or zirconium in the form of polycrystalline porous substance with a particle size of 30 nm-30 microns, connected to each other with an inorganic material, for instance silicon oxide (SiO2) with a layer thickness not more than 100 nm.

Abstract: A content addressable memory has many elements in one memory cell; thus, the area of one memory cell tends to be large. In view of the above, it is an object of an embodiment of the present invention to reduce the area of one memory cell. Charge can be held with the use of a channel capacitance in a reading transistor (capacitance between a gate electrode and a channel formation region). In other words, the reading transistor also serves as a charge storage transistor. One of a source and a drain of a charge supply transistor is electrically connected to a gate of the reading and charge storage transistor.

Abstract: One exemplary embodiment includes a semiconductor device. The semiconductor device can include a channel including one or more compounds of the formula AxBxOx wherein each A is selected from the group of Ga, In, each B is selected from the group of Ge, Sn, Pb, each O is atomic oxygen, each x is independently a non-zero integer, and each of A and B are different.

Abstract: The embodiments of the disclosed technology provide a liquid crystal display, a thin film transistor array substrate and a method for manufacturing thin film transistor array substrate. The TFT array substrate comprises: a semiconductor layer, a source electrode and a drain electrode formed adjoining the semiconductor layer, a thin film transistor channel region being defined between the source electrode and the drain electrode; and an ohmic contact layer formed between the semiconductor layer and the drain electrode and between the semiconductor layer and the source electrode, wherein the material of the semiconductor layer is zinc oxide (ZnO) and the material of the ohmic contact layer is GaxZn1?xO, where 0?x?1.

Abstract: In a transistor including a wide band gap semiconductor layer as a semiconductor layer, a wide band gap semiconductor layer is separated into an island shape by an insulating layer with passivation properties for preventing atmospheric components from permeating. The edge portion of the island shape wide band gap semiconductor layer is in contact with the insulating film; thus, moisture or atmospheric components can be prevented from entering from the edge portion of the semiconductor layer to the wide band gap semiconductor layer.

Abstract: An electronic device and manufacturing thereof. One embodiment provides a carrier and multiple contact elements. The carrier defines a first plane. A power semiconductor chip is attached to the carrier. A body is formed of an electrically insulating material covering the power semiconductor chip. The body defines a second plane parallel to the first plane and side faces extends from the first plane to the second plane. At least one of the multiple contact elements has a cross section in a direction orthogonal to the first plane that is longer than 60% of the distance between the first plane and the second plane.

Abstract: Implementations and techniques for producing substrates suitable for growing graphene monolayers are generally disclosed.

Abstract: A semiconductor device includes a drift layer having a first conductivity type, a well region in the drift layer having a second conductivity type opposite the first conductivity type, and a source region in the well region, The source region has the first conductivity type and defines a channel region in the well region. The source region includes a lateral source region adjacent the channel region and a plurality of source contact regions extending away from the lateral source region opposite the channel region. A body contact region having the second conductivity type is between at least two of the plurality of source contact regions and is in contact with the well region. A source ohmic contact overlaps at least one of the source contact regions and the body contact region. A minimum dimension of a source contact area of the semiconductor device is defined by an area of overlap between the source ohmic contact and the at least one source contact region.

Abstract: Metal oxide structures, devices, and fabrication methods are provided. In addition, applications of such structures, devices, and methods are provided. In some embodiments, an oxide material can include a substrate and a single-crystal epitaxial layer of an oxide composition disposed on a surface of the substrate, where the oxide composition is represented by ABO2 such that A is a lithium cation, B is a cation selected from the group consisting of trivalent transition metal cations, trivalent lanthanide cations, trivalent actinide cations, trivalent p-block cations, and combinations thereof, and O is an oxygen anion. The unit cell of crystal structure of the oxide composition can be characterized by first layer of a plane of lithium cations and a second layer of a plurality of edge-sharing octahedra having a B cation positioned in a center of each octahedron and an oxygen anion at each corner of each octahedron.

Abstract: The invention provides a Ferro-RRAM, a method of operating the Ferro-RRAM, and a method of fabricating the Ferro-RRAM, and pertains to the technical field of memory. The Ferro-RRAM comprises an upper electrode, a lower electrode, and a ferroelectric semiconducting thin-film layer provided between the upper electrode and the lower electrode and serving as a storage function layer; wherein the ferroelectric semiconducting thin-film layer is operable to generate a diode conduction characteristic by ferroelectric domain reorientation, and is operable to modulate the diode conduction characteristic by variation of the ferroelectric domain orientation; the Ferro-RRAM stores information according to variation of modulation of the diode conduction characteristic. The Ferro-RRAM has such characteristics of being simple in structure and fabrication, non-destructive readout and nonvolatile storage.

Abstract: A precursor solution for producing a semiconductor includes at least one of an alkali metal or an alkali metal compound dissolved in a solvent, and a metal chalcogenide dissolved in the solvent. A method of producing a precursor solution for a semiconductor includes preparing a first precursor solution that has at least one of an alkali metal or an alkali metal compound dissolved in a first solvent, preparing a second precursor solution that has a metal chalcogenide dissolved in a second solvent, and combining the first and second precursor solutions to obtain the precursor solution for producing the semiconductor. A method of producing a semiconductor device includes providing a precursor solution for producing a semiconductor layer on a substructure, and forming a layer of the precursor solution on the substructure. The precursor solution includes at least one of an alkali metal or an alkali metal compound dissolved in a solvent, and a metal chalcogenide dissolved in the solvent.

Abstract: Methods and substrates for laser annealing are disclosed. The substrate includes a target region to be annealed and a plurality of reflective interfaces. The reflective interfaces cause energy received by the substrate to resonate within the target region. The method includes emitting energy toward the substrate with a laser, receiving the energy with the substrate, and reflecting the received energy with a plurality of reflective interfaces embedded in the substrate to generate a resonance within the target region.

Abstract: A sputtering target including an oxide sintered body, the oxide sintered body containing indium (In) and at least one element selected from gadolinium (Gd), dysprosium (Dy), holmium (Ho), erbium (Er) and ytterbium (Yb), and the oxide sintered body substantially being of a bixbyite structure.

Abstract: The semiconductor device includes transistors which are stacked. The transistors include a semiconductor substrate having a groove portion and a pair of low-resistance regions between which the groove portion is provided, a first gate insulating film over the semiconductor substrate, a gate electrode overlapping with the groove portion with the first gate insulating film interposed therebetween, a second gate insulating film covering the gate electrode, a pair of electrodes provided over the second gate insulating film so that the groove portion is sandwiched between the pair of electrodes, and a semiconductor film in contact with the pair of electrodes. One of the pair of low-resistance region is electrically connected to one of the pair of electrodes. One of the transistors includes an n-type semiconductor and the other includes a p-type semiconductor, so that a complementary MOS circuit is formed.

Abstract: The invention relates to a liquid-phase method for the thermal production of silicon layers on a substrate, wherein at least one higher silicon that can be produced from at least one hydridosilane of the generic formula SiaH2a+2 (with a=3-10) being applied to a substrate and then being thermally converted to a layer that substantially consists of silicon, the thermal conversion of the higher silane proceeding at a temperature of 500-900° C. and a conversion time of ?5 minutes. The invention also relates to silicon layers producible according to said method and to their use.

Abstract: An embodiment is to include an inverted staggered (bottom gate structure) thin film transistor in which an oxide semiconductor film containing In, Ga, and Zn is used as a semiconductor layer and a buffer layer is provided between the semiconductor layer and a source and drain electrode layers. The buffer layer having higher carrier concentration than the semiconductor layer is provided intentionally between the source and drain electrode layers and the semiconductor layer, whereby an ohmic contact is formed.

Abstract: A semiconductor device that can transmit and receive data without contact is popular partly as some railway passes, electronic money cards, and the like; however, it has been a prime task to provide an inexpensive semiconductor device for further popularization. In view of the above current conditions, a semiconductor device of the present invention includes a memory with a simple structure for providing an inexpensive semiconductor device and a manufacturing method thereof. A memory element included in the memory includes a layer containing an organic compound, and a source electrode or a drain electrode of a TFT provided in the memory element portion is used as a conductive layer which forms a bit line of the memory element.