Abstract: A device is provided. The device includes a first electrode, an organic layer disposed over the first electrode and a second electrode disposed over the organic layer. The second electrode further includes a first conductive layer having an extinction coefficient and an index of refraction, a first separation layer disposed over the first conductive layer, and a second conductive layer disposed over the first separation layer. The first separation layer has an extinction coefficient that is at least 10% different from the extinction coefficient of the first conductive layer at 500 nm, or an index of refraction that is at least 10% different from the index of refraction of the first conductive layer at 500 nm. The device also includes a barrier layer disposed over the second conductive layer.

Abstract: Disclosed are a high-sensitivity transparent gas sensor and a method for manufacturing the same. The transparent gas sensor includes a transparent substrate, a transparent electrode formed on the transparent substrate and a transparent gas-sensing layer formed on the transparent electrode. The transparent gas-sensing layer has a nanocolumnar structure having nanocolumns formed on the transparent electrode and gas diffusion pores formed between the nanocolumns.

Abstract: An object of one embodiment of the present invention is to provide a semiconductor device with a novel structure in which stored data can be stored even when power is not supplied in a data storing time and there is no limitation on the number of times of writing. The semiconductor device includes a first transistor which includes a first channel formation region using a semiconductor material other than an oxide semiconductor, a second transistor which includes a second channel formation region using an oxide semiconductor material, and a capacitor. One of a second source electrode and a second drain electrode of the second transistor is electrically connected to one electrode of the capacitor.

Abstract: High yield substrate assembly. In accordance with a first method embodiment, a plurality of piggyback substrates are attached to a carrier substrate. The edges of the plurality of the piggyback substrates are bonded to one another. The plurality of piggyback substrates are removed from the carrier substrate to form a substrate assembly. The substrate assembly is processed to produce a plurality of integrated circuit devices on the substrate assembly. The processing may use manufacturing equipment designed to process wafers larger than individual instances of the plurality of piggyback substrates.

Abstract: A SiC semiconductor device having a Schottky barrier diode includes: a substrate made of SiC and having a first conductive type, wherein the substrate includes a main surface and a rear surface; a drift layer made of SiC and having the first conductive type, wherein the drift layer is disposed on the main surface of the substrate and has an impurity concentration lower than the substrate; a Schottky electrode disposed on the drift layer and has a Schottky contact with a surface of the drift layer; and an ohmic electrode disposed on the rear surface of the substrate. The Schottky electrode directly contacts the drift layer in such a manner that a lattice of the Schottky electrode is matched with a lattice of the drift layer.

Abstract: A method of forming a silicon carbide transient voltage suppressor (TVS) assembly and a system for a transient voltage suppressor (TVS) assembly are provided. The TVS assembly includes a semiconductor die in a mesa structure that includes a first layer of a first wide band gap semiconductor having a conductivity of a first polarity, a second layer of the first or a second wide band gap semiconductor having a conductivity of a second polarity coupled in electrical contact with the first layer wherein the second polarity is different than the first polarity. The TVS assembly also includes a third layer of the first, the second, or a third wide band gap semiconductor having a conductivity of the first polarity coupled in electrical contact with the second layer. The layer having a conductivity of the second polarity is lightly doped relative to the layers having a conductivity of the first polarity.

Abstract: It is an object to manufacture a highly reliable semiconductor device including a thin film transistor whose electric characteristics are stable. An insulating layer which covers an oxide semiconductor layer of the thin film transistor contains a boron element or an aluminum element. The insulating layer containing a boron element or an aluminum element is formed by a sputtering method using a silicon target or a silicon oxide target containing a boron element or an aluminum element. Alternatively, an insulating layer containing an antimony (Sb) element or a phosphorus (P) element instead of a boron element covers the oxide semiconductor layer of the thin film transistor.

Abstract: Transistors and electronic apparatuses including the same are provided, the transistors include a channel layer on a substrate. The channel layer includes a zinc (Zn)-containing oxide. The transistors include a source and a drain, respectively, contacting opposing ends of the channel layer, a gate corresponding to the channel layer, and a gate insulating layer insulating the channel layer from the gate. The channel layer has a first surface adjacent to the substrate, a second surface facing the first surface, and a channel layer-protection portion on the second surface. The channel layer-protection portion includes a fluoride material.

Abstract: A process for creating a beryllium oxide film on the surface of a semiconductor material is disclosed. The process is useful for making gate dielectric layers for metal-oxide-semiconductor (MOS) devices, particularly III-V semiconductor devices.

Abstract: A memory device in which a write error can be prevented is provided. The memory device includes a NAND cell unit including a plurality of memory cells connected in series, a first selection transistor connected to one of terminals of the NAND cell unit, a second selection transistor connected to the other of the terminals of the NAND cell unit, a source line connected to the first selection transistor, and a bit line which intersects with the source line and is connected to the second selection transistor. In the memory device, a channel region of each of the first selection transistor and the second selection transistor is formed in an oxide semiconductor layer.

Abstract: An object is to reduce leakage current and parasitic capacitance of a transistor used for an LSI, a CPU, or a memory. A semiconductor integrated circuit included in an LSI, a CPU, or a memory is manufactured using the transistor which is formed using an oxide semiconductor which is an intrinsic or substantially intrinsic semiconductor obtained by removal of impurities which serve as electron donors (donors) from the oxide semiconductor and has larger energy gap than a silicon semiconductor, and is formed over a semiconductor substrate. With the transistor which is formed over the semiconductor substrate and includes the highly purified oxide semiconductor layer with sufficiently reduced hydrogen concentration, a semiconductor device whose power consumption due to leakage current is low can be realized.

Abstract: A semiconductor module having one or more silicon carbide diode elements mounted on a switching element is provided in which the temperature rise is reduced by properly disposing each of the diode elements on the switching element, to thereby provide a thermal dissipation path for the respective diode elements. The respective diode elements are arranged on a non-central portion of the switching element, to facilitate dissipation of the heat produced by each of the diode elements, whereby the temperature rise in the semiconductor module is reduced.

Abstract: Semiconductor switching devices include a first wide band-gap semiconductor layer having a first conductivity type. First and second wide band-gap well regions that have a second conductivity type that is opposite the first conductivity type are provided on the first wide band-gap semiconductor layer. A non-wide band-gap semiconductor layer having the second conductivity type is provided on the first wide band-gap semiconductor layer. First and second wide band-gap source/drain regions that have the first conductivity type are provided on the first wide band-gap well region. A gate insulation layer is provided on the non-wide band-gap semiconductor layer, and a gate electrode is provided on the gate insulation layer.

Abstract: A nitride semiconductor substrate is provided in which leak current reduction and improvement in current collapse are effectively attained when using Si single crystal as a base substrate. The nitride semiconductor substrate is such that an active layer of a nitride semiconductor is formed on one principal plane of a Si single crystal substrate through a plurality of buffer layers made of a nitride, in the buffer layers, a carbon concentration of a layer which is in contact with at least the active layer is from 1×1018 to 1×1020 atoms/cm3, a ratio of a screw dislocation density to the total dislocation density is from 0.15 to 0.3 in an interface region between the buffer layer and the active layer, and the total dislocation density in the interface region is 15×109 cm?2 or less.

Abstract: A coating fluid comprising a boron compound, an organic binder, a silicon compound, an alumina precursor, and water and/or an organic solvent is used to diffuse boron into a silicon substrate to form a p-type diffusion layer. The coating fluid is spin coated onto the substrate to form a uniform coating having a sufficient amount of impurity whereupon a p-type diffusion layer having in-plane uniformity is formed.

Abstract: A multilayered stack including alternating layers of sacrificial material layers and semiconductor material layers is formed on a base substrate. The thickness of each sacrificial material layer of the stack increases upwards from the sacrificial material layer that is formed nearest to the base substrate. Because of this difference in thicknesses, each sacrificial material layer etches at different rates, with thicker sacrificial material layers etching faster than thinner sacrificial material layers. An etch is performed that first removes the thickest sacrificial material layer of the multilayered stack. The uppermost semiconductor device layer within the multilayered stack is accordingly first released. As the etch continues, the other sacrificial material layers are removed sequentially, in the order of decreasing thickness, and the other semiconductor device layers are removed sequentially.

Abstract: A semiconductor element 100 including an MISFET according to the present invention is characterized by having diode characteristics in a reverse direction through an epitaxial channel layer 50. The semiconductor element 100 includes a silicon carbide semiconductor substrate 10 of a first conductivity type, a semiconductor layer 20 of the first conductivity type, a body region 30 of a second conductivity type, a source region 40 of the first conductivity type, an epitaxial channel layer 50 in contact with the body region, a source electrode 45, a gate insulating film 60, a gate electrode 65 and a drain electrode 70. If the voltage applied to the gate electrode of the MISFET is smaller than a threshold voltage, the semiconductor element 100 functions as a diode in which current flows from the source electrode 45 to the drain electrode 70 through the epitaxial channel layer 50.

Abstract: A p-type MgxZn1-xO-based thin film (1) is formed on a substrate (2) made of a ZnO-based semiconductor. The p-type MgxZn1-xO-based thin film (1) is composed so that X as a ratio of Mg with respect to Zn therein can be 0?X<1, preferably 0?X?0.5. In the p-type MgZnO thin film (1), nitrogen as p-type impurities which become an acceptor is contained at a concentration of approximately 5.0×1018 cm?3 or more. The p-type MgZnO thin film (1) is composed so that n-type impurities made of a group IV element such as silicon that becomes a donor can have a concentration of approximately 1.0×1017 cm?3 or less. The p-type MgZnO thin film (1) is composed so that n-type impurities made of a group III element such as boron and aluminum which become a donor can have a concentration of approximately 1.0×1016 cm?3 or less.

Abstract: A substrate having a graphene film grown thereon according to the present invention includes: a base substrate; a patterned aluminum oxide film formed on the base substrate, the patterned aluminum oxide film having an average composition of Al2?xO3+x (where x is 0 or more); and a graphene film preferentially grown only on the patterned aluminum oxide film, the graphene film having one or more graphene atomic layers, the graphene film growing parallel to a surface of the patterned aluminum oxide film, the graphene film having an electrical conductivity of 1×104 S/cm or more measured by a four-probe resistive method using an inter-voltage-probe distance of 0.2 mm.

Abstract: Provided is a semiconductor device including a transistor with large on-state current even when it is miniaturized. The transistor includes a pair of first conductive films over an insulating surface; a semiconductor film over the pair of first conductive films; a pair of second conductive films, with one of the pair of second conductive films and the other of the pair of second conductive films being connected to one of the pair of first conductive films and the other of the pair of first conductive films, respectively; an insulating film over the semiconductor film; and a third conductive film provided in a position overlapping with the semiconductor film over the insulating film. Further, over the semiconductor film, the third conductive film is interposed between the pair of second conductive films and away from the pair of second conductive films.

Abstract: According to one embodiment, a thin film transistor includes a substrate, a gate electrode, a first insulating film, an oxide semiconductor film, a second insulating film, a source electrode, and a drain electrode. The gate electrode is provided on a part of the substrate. The first insulating film covers the gate electrode. The oxide semiconductor film is provided on the gate electrode via the first insulating film. The second insulating film is provided on a part of the oxide semiconductor film. The source and drain electrodes are respectively connected to first and second portions of the oxide semiconductor film not covered with the second insulating film. The oxide semiconductor film includes an oxide semiconductor. Concentrations of hydrogen contained in the first and second insulating films are not less than 5×1020 atm/cm3, and not more than 1019 atm/cm3, respectively.

Abstract: A thin film transistor for a semiconductor device is disclosed. The thin film transistor comprises a substrate; a channel region formed on the substrate, the channel region being made of a first oxide semiconductor material; a source region and a drain region formed on each of lateral sides of the channel region, the source region and the drain region being made of a second oxide semiconductor material, the second oxide semiconductor material having a band gap smaller than a band gap of the first oxide semiconductor material; a gate electrode formed on the channel region; and a gate insulating layer sandwiched between the gate electrode and the channel region.

Abstract: A semiconductor device according to the present embodiment includes a diamond substrate having a surface plane inclined from a (100) plane in a range of 10 degrees to 40 degrees in a direction of <011> ±10 degrees, and an n-type diamond semiconductor layer containing phosphorus (P) and formed above the surface plane described above.

Abstract: According to example embodiments, an electrode structure includes a graphene layer on a semiconductor layer and an electrode containing metal on the graphene layer. A field effect transistor (FET) may include the electrode structure.

Abstract: According to one embodiment, a fabrication method for a semiconductor device includes: injecting an ion into a first substrate; joining the first substrate and a second substrate; irradiating a microwave to agglomerate the ion in a planar state in a desired position in the first substrate and form an agglomeration region spreading in a planar state; separating the second substrate provided with a part of the first substrate from the rest of the first substrate by exfoliating the joined first substrate from the second substrate in the agglomeration region; and grinding a part of the second substrate on a back surface opposite to an exfoliated surface in the second substrate provided with a part of the first substrate.

Abstract: Embodiments of a low resistivity contact to a semiconductor structure are disclosed. In one embodiment, a semiconductor structure includes a semiconductor layer, a semiconductor contact layer having a low bandgap on a surface of the semiconductor layer, and an electrode on a surface of the semiconductor contact layer opposite the semiconductor layer. The bandgap of the semiconductor contact layer is in a range of and including 0 to 0.2 electron-volts (eV), more preferably in a range of and including 0 to 0.1 eV, even more preferably in a range of and including 0 to 0.05 eV. Preferably, the semiconductor layer is p-type. In one particular embodiment, the semiconductor contact layer and the electrode form an ohmic contact to the p-type semiconductor layer and, as a result of the low bandgap of the semiconductor contact layer, the ohmic contact has a resistivity that is less than 1×10?6 ohms·cm2.

Abstract: A power MISFET using an oxide semiconductor is provided. A drain electrode and a gate electrode having a trapezoidal cross section are formed with a semiconductor layer provided therebetween, a semiconductor layer is formed on a side surface of the gate electrode, and a source electrode is in contact with the semiconductor layer at a portion which overlaps with the top of the gate electrode. Between the drain electrode and the source electrode of such a power MISFET, a power source of 500 V or more and a load are connected in series, and a control signal is input to the gate electrode. Other structures and operating methods are also disclosed.

Abstract: A III-N on silicon substrate with enhanced breakdown voltage including a rare earth oxide structure deposited on the silicon substrate and a layer of single crystal III-N semiconductor material deposited on the rare earth oxide structure. The rare earth oxide has a dielectric constant greater (approximately twice) than the III-N semiconductor material. The rare earth oxide structure is selected to cooperate with the layer of single crystal III-N semiconductor material to reduce the thickness of the layer of single crystal III-N semiconductor material required for a selected breakdown voltage to a value less than a thickness of the layer of single crystal III-N semiconductor material for the selected breakdown voltage without the cooperating single crystal rare earth oxide.

Abstract: The contact resistance between an oxide semiconductor film and a metal film is reduced. A transistor that uses an oxide semiconductor film and has excellent on-state characteristics is provided. A semiconductor device capable of high-speed operation is provided. In a transistor that uses an oxide semiconductor film, the oxide semiconductor film is subjected to nitrogen plasma treatment. Thus, part of oxygen included in the oxide semiconductor film is replaced with nitrogen, so that an oxynitride region is formed. A metal film is formed in contact with the oxynitride region. The oxynitride region has lower resistance than the other region of the oxide semiconductor film. In addition, the oxynitride region is unlikely to form high-resistance metal oxide at the interface with the contacting metal film.

Abstract: A substrate is provided with a main surface having an off angle of 5° or smaller relative to a reference plane. The reference plane is a {000-1} plane in the case of hexagonal system and is a {111} plane in the case of cubic system. A silicon carbide layer is epitaxially formed on the main surface of the substrate. The silicon carbide layer is provided with a trench having first and second side walls opposite to each other. Each of the first and second side walls includes a channel region. Further, each of the first and second side walls substantially includes one of a {0-33-8} plane and a {01-1-4} plane in the case of the hexagonal system and substantially includes a {100} plane in the case of the cubic system.

Abstract: A semiconductor device structure on a substrate and a manufacture method thereof is provided. The semiconductor device structure includes an oxide semiconductor transistor and a passivation layer containing free hydrogen. The semiconductor device structure is formed by following steps. A gate electrode is formed on the substrate. A gate dielectric layer covers the gate electrode. A source electrode is formed on the gate dielectric layer. A drain electrode is formed on the gate dielectric layer and separated from the source electrode and thereby forming a channel distance. An oxide semiconductor layer is formed on the gate dielectric layer, the source electrode and the drain electrode and between the source electrode and the drain electrode. The oxide semiconductor layer is further electrically connected with the source electrode and the drain electrode. A passivation layer covers the oxide semiconductor layer, the source electrode and the drain electrode.

Abstract: System and method for controlling the channel thickness and preventing variations due to formation of small features. An embodiment comprises a fin raised above the substrate and a capping layer is formed over the fin. The channel carriers are repelled from the heavily doped fin and confined within the capping layer. This forms a thin-channel that allows greater electrostatic control of the gate.

Abstract: The present disclosure provides for electronic devices that use low cost, conductive materials as transparent conductors. The devices contain corrosion preventative conductive polymer layers and conductive innerlayer barriers that separate corrosive electrolyte from the conductors which are prone to corrosion and dissolution, while providing an uninterrupted electrical circuit. The present disclosure also allows for the use of layers which have been applied from aqueous media thereby reducing both the cost and the environmental impact of the electronic devices. Methods of manufacture are also provided.

Abstract: A semiconductor device according to one embodiment includes an element isolation insulating film formed on a substrate, an element region and a dummy pattern region demarcated by the element isolation insulating film on the substrate, a first epitaxial crystal layer formed on the substrate within the element region, and a second epitaxial crystal layer formed on the substrate within the dummy pattern region. The first epitaxial crystal layer is made up of crystals that have a different lattice constant from that of the crystals that constitute the substrate. The second epitaxial crystal layer is made up of the same crystals as the first epitaxial crystal layer. The (111) plane of the substrate that includes any points on the interface between the second epitaxial crystal layer and the substrate is surrounded by the element isolation insulating film in a deeper region than the second epitaxial crystal layer.

Abstract: Polymerizable diazonium salts having redox properties and absorption in the visible range, a process for preparing them and uses thereof are disclosed. The salts have the general formula: [XX+LnDdEm(N2+)p][(B?)p+x] in which: X is chosen from transition metals, preferably X is chosen from ruthenium (Ru), osmium (Os), iron (Fe), cobalt (Co) and iridium (Ir), x is an integer ranging from 1 to 5 inclusive, L is a ligand chosen from pyridine, bipyridine, terpyridine, phenanthroline and phenylpyridine groups, and mixtures thereof, n is an integer ranging from 1 to 5 inclusive, D is a saturated or unsaturated, C1-C5 alkyl spacer compound, d=0 or 1, E is an aromatic or polyaromatic spacer compound that can contain one or more heteroatoms, m is an integer ranging from 0 to 5 inclusive, p is an integer, and B is a counterion.

Abstract: An oxide semiconductor transistor comprising an oxide semiconductor layer with high conductivity is provided. A semiconductor device including an oxide semiconductor layer comprising an oxide containing indium, gallium, and zinc (IGZO) and a particle of indium oxide; a gate electrode overlapping with a channel formation region in the oxide semiconductor layer with a gate insulating film interposed therebetween; and a source electrode and a drain electrode overlapping with a source region and a drain region in the oxide semiconductor layer. The semiconductor device may be a top-gate oxide semiconductor transistor or a bottom-gate oxide semiconductor transistor. The oxide semiconductor layer may be formed over or below the source electrode and the drain electrode.

Abstract: A semiconductor device according to an embodiment, includes a catalytic metal film, a graphene film, a contact plug, and an adjustment film. The catalytic metal film is formed above a substrate. The graphene film is formed on the catalytic metal film. The contact plug is connected to the graphene film. The adjustment film is formed in a region other than a region connected to the contact plug of a surface of the graphene film to adjust a Dirac point position in a same direction as the region connected to the contact plug with respect to a Fermi level.

Abstract: Passivated semiconductor nanoparticles and methods for the fabrication and use of passivated semiconductor nanoparticles is provided herein.

Abstract: Structures and methods for producing active layer stacks of lattice matched, lattice mismatched and thermally mismatched semiconductor materials, with low threading dislocation densities, no layer cracking and minimized wafer bowing, by using epitaxial growth onto elevated substrate regions in a mask-less process.

Abstract: An apparatus including a first layer configured to enable a flow of charge carriers from a source electrode to a drain electrode, a second layer configured to control the density of charge carriers in the first layer using an electric field formed between the first and second layers, and a third layer positioned between the first and second layers to shield the first layer from the electric field, wherein the third layer includes a layer of electrically conducting nanoparticles and is configured such that when stress is applied to the third layer, the strength of the electric field experienced by the first layer is varied resulting in a change in the charge carrier density and a corresponding change in the conductance of the first layer.

Abstract: The SrTiO3 buffer layer is formed by lamination of the Sr2+O2? layer and the Ti4+O24? layer. The surface of the buffer layer is terminated with the Ti4+O24? layer. On the buffer layer, a LaAlO3 thin film layer is formed. The thin film layer includes a La3+O2? layer and an Al3+O24? layer alternately laminated in order on the SrTiO3 buffer layer.

Abstract: Rare earth oxy-nitride buffered III-N on silicon includes a silicon substrate with a rare earth oxide (REO) structure, including several REO layers, is deposited on the silicon substrate. A layer of single crystal rare earth oxy-nitride is deposited on the REO structure. The REO structure is stress engineered to approximately crystal lattice match the layer of rare earth oxy-nitride so as to provide a predetermined amount of stress in the layer of rare earth oxy-nitride. A III oxy-nitride structure, including several layers of single crystal rare earth oxy-nitride, is deposited on the layer of rare earth oxy-nitride. A layer of single crystal III-N nitride is deposited on the III oxy-nitride structure. The III oxy-nitride structure is chemically engineered to approximately crystal lattice match the layer of III-N nitride and to transfer the predetermined amount of stress in the layer of rare earth oxy-nitride to the layer of III-N nitride.

Abstract: Disclosed is an active matrix substrate (20a) that includes: an insulating substrate (10a); a first thin film transistor (5a) that is formed on the insulating substrate (10a) and that includes a first oxide semiconductor layer (13a) having a first channel region (Ca); a second thin film transistor (5b) that is formed on the insulating substrate (10a) and that includes a second oxide semiconductor layer (13b) having a second channel region (Cb); and an interlayer insulating film (17) that covers the first oxide semiconductor layer (13a) and the second oxide semiconductor layer (13b). A channel protective film (25), which is formed of a material different from that of the interlayer insulating film (17), is provided between the second oxide semiconductor layer (13b) and the interlayer insulating film (17) on the second channel region (Cb) in the second oxide semiconductor layer (13b).

Abstract: A high temperature, non-cavity package for non-axial electronics is designed using a glass ceramic compound with that is capable of being assembled and operating continuously at temperatures greater that 300-400° C. Metal brazes, such as silver, silver colloid or copper, are used to connect the semiconductor die, lead frame and connectors. The components are also thermally matched such that the packages can be assembled and operating continuously at high temperatures and withstand extreme temperature variations without the bonds failing or the package cracking due to a thermal mismatch.

Abstract: A silicon nanowire including metal nanoclusters formed on a surface thereof at a high density. The metal nanocluster improves electrical and optical characteristics of the silicon nanowire, and thus can be usefully used in various electrical devices such as a lithium battery, a solar cell, a bio sensor, a memory device, or the like.

Abstract: Provided is a structure of a transistor, which enables a so-called normally-off switching element, and a manufacturing method thereof. Provided is a structure of a semiconductor device which achieves high-speed response and high-speed operation by improving on characteristics of a transistor, and a manufacturing method thereof. Provided is a highly reliable semiconductor device. In the transistor in which a semiconductor layer, source and drain electrode layers, a gate insulating layer, and a gate electrode layer are stacked in that order. As the semiconductor layer, an oxide semiconductor layer which contains at least four kinds of elements of indium, gallium, zinc, and oxygen, and has a composition ratio (atomic percentage) of indium as twice or more as a composition ratio of gallium and a composition ratio of zinc, is used.

Abstract: A thin film transistor may include a passivation layer formed of a metal-containing conductive material. The thin film transistor includes: a gate electrode; a gate insulating layer positioned on the gate electrode; a channel layer positioned on the gate insulating layer; a source electrode and a drain electrode which are in contact with the channel layer while being spaced apart from each other; and a passivation layer including a metal-containing conductive material and positioned on the channel layer while being spaced apart from each of the source electrode and the drain electrode. The passivation layer serves to prevent transmission of light, oxygen, water and/or impurities into the channel layer and to improve the electrical characteristics of the thin film transistor.

Abstract: A semiconductor device and a method of forming a structure in a target substrate for manufacturing a semiconductor device is provided. The method comprises the step of providing a masking layer on the target substrate and providing a stair-like profile in the masking layer such that the height of a step of the stair-like profile is smaller than the thickness of the masking layer. Further, the method comprises the step of performing anisotropic etching of the masking layer and the target substrate simultaneously such that a structure having a stair-like profile is formed in the target substrate. The semiconductor device comprises a target substrate including a first region made of a first type of semiconductor material and a second region made of a second type of semiconductor material.

Abstract: A semiconductor device which can operate at high speed and consumes a smaller amount of power is provided. In a semiconductor device including transistors each including an oxide semiconductor, the oxygen concentration of the oxide semiconductor film of the transistor having small current at negative gate voltage is different from that of the oxide semiconductor film of the transistor having high field-effect mobility and large on-state current. Typically, the oxygen concentration of the oxide semiconductor film of the transistor having high field-effect mobility and large on-state current is lower than that of the oxide semiconductor film of the transistor having small current at negative gate voltage.

Abstract: A wafer and a fabrication method include a base structure including a substrate for fabricating semiconductor devices. The base structure includes a front side where the semiconductor devices are formed and a back side opposite the front side. An integrated layer is formed in the back side of the base structure including impurities configured to alter etch selectivity relative to the base structure such that the integrated layer is selectively removable from the base structure to remove defects incurred during fabrication of the semiconductor devices.