Abstract: A probe device includes a probe body having a plurality of first holes extending through a first face thereof and a plurality of second holes aligned with the first holes and extending through an opposite second face thereof, a plurality of spaced-apart first probe pins inserted fittingly and removably into respective first holes and each including a first contact portion extending out of the first face, and a first connecting portion extending into the respective first hole, and a plurality of spaced-apart second probe pins inserted fittingly and removably into respective second holes and each including a second contact portion extending out of the second face, and a second connecting portion extending into the respective second hole and having an insert space. The first connecting portion is inserted fittingly and removably into the insert space, and mates with the second connecting portion.

Abstract: A semiconductor apparatus includes: a first power line coupled to a first power transfer pad; a second power line coupled to a second power transfer pad; and a test option unit coupled to the first and second power lines and configured to couple the first and second power lines.

Abstract: A probe card assembly can comprise an interface, which can be configured to receive from a tester test signals for testing an electronic device. The probe card assembly can further comprise probes for contacting the electronic device and electronic driver circuits for driving the test signals to ones of the probes.

Abstract: The present invention relates to a probe for determining an electrical property of an area of a surface of a test sample, the probe is intended to be in a specific orientation relative to the test sample. The probe may comprise a supporting body defining a first surface. A plurality of cantilever arms (12) may extend from the supporting body in co-planar relationship with the first surface. The plurality of cantilever arms (12) may extend substantially parallel to each other and each of the plurality of cantilever arms (12) may include an electrical conductive tip for contacting the area of the test sample by movement of the probe relative to the surface of the test sample into the specific orientation. The probe may further comprise a contact detector (14) extending from the supporting body arranged so as to contact the surface of the test sample prior to any one of the plurality of cantilever arms (12) contacting the surface of the test sample when performing the movement.

Abstract: A system for providing a reference voltage includes a tester adapted to provide a predetermined current, a first ground pad connected to a ground voltage of the tester, a second ground pad connected between the tester and the first ground pad, the second ground pad being connected to the tester through first and second resistors, a reference voltage pad connected to a node between the first and second resistors, the reference voltage pad adapted to provide a test reference voltage, and a multiplexer connected to the reference voltage pad, the multiplexer configured to output the test reference voltage as a reference voltage during substantial voltage variation.

Abstract: An inclination adjusting method adjusts an inclination of a probe card installed at a probe apparatus to make the probe card be in parallel with a mounting surface of a movable mounting table for mounting thereon an object to be inspected. The method includes: detecting an average tip height of multiple probes disposed at each of plural locations of the probe card by using a tip position detecting device; obtaining an inclination of the probe card with respect to the mounting table based on differences in the average tip heights detected from the plural locations of the probe card; and adjusting the inclination of the probe card based on the obtained inclination.

Abstract: A probe system that has a probe body comprising at least three arms extending from a central region and a probe tip centrally located on the probe body in the central region. A substrate is proximate the probe body opposite the probe tip. A first electrode is positioned to provide a centrally positioned voltage across the probe body and the substrate and a second electrode set is positioned radially outward from the first electrode, to provide an outer voltage across at least one of the at least three arms and the substrate. The probe structure may have, for example, four arms. Methods of actuating the probe tip are provided.

Abstract: A wafer test equipment system includes a performance board connected to a tester head of a tester. A universal block printed circuit board is positioned on the performance board, directly connecting a plurality of normal signal lines to a probe card and dividing each of a plurality of power signal lines into multiple paths and connecting them to the probe card. A cable assembly transfers the normal signal lines and the power signal lines between the universal block printed circuit board and the tester head. The cable assembly is soldered directly to the universal block printed circuit board in a perpendicular direction through a center portion of the performance board. A probe card is removably secured to the performance board including the universal block printed circuit board.

Abstract: A charged device model (CDM) electrostatic discharge (ESD) testing is carried out at wafer level. Wafer CDM pulses are repeatedly applied and monitored. The wafer CDM (WCDM) pulses are accomplished with a probe-mounted printed-circuit board and a high-frequency transformer that captures fast CDM pulses. Modeling of CDM and WCDM in the time and frequency domain illustrates the dominant effects, and shows that WCDM can reproduce all the major phenomena of package-level CDM testing.

Abstract: A diagnosis board is electrically connected with a test apparatus for testing a device-under-test and used in diagnosing the test apparatus. The test apparatus has a test head containing test modules for sending/receiving signals to/from the device-under-test. The diagnosis board has a plurality of sub-boards arranged substantially on the same plane, substantially forming a plane as a unit, and connected with each part of a plurality of terminals of the test modules and used for diagnosing the connected terminals, each of the plurality of sub-boards having a plate-like shape. The diagnosis board also has a fixing section for attaching and fixing the plurality of sub-boards in a body to the test head.

Abstract: A testing system module for testing printed circuit board (PCB) includes at least one robot having a pogo pin for moving to a testing point of the PCB; a pressure detecting unit for detecting a current pressure value on the printed circuit board; and a control system for keeping the pogo pin to contact with the PCB with constant pressure.

Abstract: A test system and method for identifying open and shorted connections on a printed circuit board (PCB). An integrated circuit (IC) unit on the PCB is configured to generate a test signal on an output pin connected to a test pin on a second device, connector, or socket on the PCB. For a connection, the test signal is capacitively coupled to a detector plate proximal the second device. Based on the signal coupled to the detector, time domain analysis is performed on the coupled signal to determine if the test pin has a good connection to the PCB or if the pin is open or shorted. Analysis may include cross-correlating the coupled signal with a learned signal obtained from a known “good” PCB. The test pin may pass the test if the cross-correlation is within a specified threshold window. If the test fails, additional tests may be performed to troubleshoot the cause of the testing failure.

Abstract: To permit electrical testing of a semiconductor integrated circuit device having test pads disposed at narrow pitches probes in a pyramid or trapezoidal pyramid form are formed from metal films formed by stacking a rhodium film and a nickel film successively. Via through-holes are formed in a polyimide film between interconnects and the metal films, and the interconnects are electrically connected to the metal films. A plane pattern of one of the metal films equipped with one probe and through-hole is obtained by turning a plane pattern of the other metal film equipped with the other probe and through-hole through a predetermined angle.

Abstract: An emitter follower or source follower transistor is provided in the channel of a wafer test system between a DUT and a test system controller to enable a low power DUT to drive a test system channel. A bypass resistor is included between the base and emitter of the emitter follower transistor to enable bi-directional signals to be provided between the DUT channel and test system controller, as well as to enable parametric tests to be performed. The emitter follower transistor and bypass resistor can be provided on the probe card, with a pull down termination circuit included in the test system controller. The test system controller can provide compensation for the base to emitter voltage drop of the emitter follower transistor.

Abstract: In order for a conduction path to have a reduced number of sliding portions for conduction, without increase in inductance nor resistance, thereby permitting an enhanced accuracy of inspection, a pair of plungers (3, 4) biased in opposite directions by a coil spring (2), to be electrically connected to a wiring plate (10), have electrical connections in which, in a tubular portion (15) as a tight wound spiral portion (15a) fixed on one plunger (4) to allow linear flow of electrical signal, the other plunger (3) is brought into slidable contact.

Abstract: A semiconductor integrated circuit includes first and second bump pads configured to output data, a probe test pad coupled to the first bump pad, and a pipe latch unit configured to selectively transfer data loaded on first and second data lines to one of the first and second bump pads in response to a pipe output dividing signal during a normal mode, and sequentially transfer the data loaded on the first and second data lines to the probe test pad in response to the pipe output dividing signal during a test mode.

Abstract: A test circuit and system for testing one or more electrical properties of an electronic circuit or other device under test (DUT) by applying and monitoring test signals to the DUT is disclosed. The test circuit can utilize a plurality of universal interface channel circuits in a single automated test system to provide a unique and flexible approach for testing electronic circuits or devices that has many advantages. A single data acquisition circuit can be coupled to one or more universal interface channel circuits. Each of the universal interface channel circuits can be independently commanded by the data acquisition circuit to provide one of a variety of test signals to a DUT as desired.

Abstract: Provided is a test apparatus including a test head main body 130 that communicates a signal with the device under test 200, a prober 110 on which the device under test 200 is mounted, and a probe card 300 positioned between the test head main body 130 and the prober 110, where the probe card 300 includes: a plurality of probe pins 320 provided on a surface thereof facing the prober 110 and electrically connected to a terminal of the device under test 200; a plurality of test head pads 330 provided on a surface thereof facing the test head main body 130 and electrically connected to spring pins 129 on the test head main body 130 and to the probe pins 320; and prober pads 340 provided on a surface thereof facing the prober 110 and electrically connected to the plurality of probe pins 320.

Abstract: The voltage application probe and the voltage measurement probe are connected to the voltage application pad and the voltage measurement pad of the semiconductor device. The voltage application pad and the voltage measurement pad are connected by the conductor, measuring the voltage applied to the voltage application pad through the voltage measurement probe. The voltage compensation circuit in the voltage development device operates to make the voltage applied to the voltage application pad equal to the set voltage for the voltage development device. Even when the resistance between the voltage application probe and the voltage application pad increases, the accurate setting voltage is applied to the voltage application pad.

Abstract: A device for sensing a position of a probe relative to a reference medium, the probe comprising a heater element with a temperature dependent electrical resistance and being adapted to determine probe position by measuring a parameter associated to a thermal relaxation time of the heater element.

Abstract: A vertically folded probe is provided that can provide improved scrub performance in cases where the probe height is limited. More specifically, such a probe includes a base and a tip, and an arm extending from the base to the tip as a single continuous member. The probe arm is vertically folded, such that it includes three or more vertical arm portions. The vertical arm portions have substantial vertical overlap, and are laterally displaced from each other. When such a probe is vertically brought down onto a device under test, the probe deforms. During probe deformation, at least two of the vertical arm portions come into contact with each other. Such contact between the arm portions can advantageously increase the lateral scrub motion at the probe tip, and can also advantageously reduce the probe inductance.

Abstract: The probe with printed tip consists of a substrate having a plurality of probe tips connected to its end edge, a plurality of test paths, each connected to one of the probe tips and extending along the substrate, and at least one of the test paths including an electrical component adjacent to the test path's probe tip. The electrical component may be a resistor. The probe tips may have a width equal to the thickness of the substrate. The probe tips may consist of a plurality of probe tip layers. The invention also includes a method of probing signals transmitted over target transmission lines on a target board. The disclosure also includes a method of manufacturing the claimed invention.

Abstract: An integrated circuit that supports testing of multiple pads via a subset of these pads includes at least two sections. Each section has multiple pads and multiple test access circuits coupled to these pads. For each section, one pad is designated as a primary pad and the remaining pads are designated as secondary pads. For each section, the test access circuits couple the secondary pads to the primary pad such that all of the pads in the section can be tested by probing just the primary pad. Each test access circuit may be implemented with a simple switch. A controller generates a set of control signals for the test access circuits in all sections. These control signals enable and disable the test access circuits such that all of the sections can be tested in parallel, and the pads in each section can be tested in a sequential order.

Abstract: A test system can include contact elements for making electrical connections with test points of a DUT. The test system can also include a DC test resource and a signal router, which can be configured to switch a DC channel from the DC test resource between individual contact elements in a group of contact elements.

Abstract: A reversible test probe and test probe tip. In one embodiment, a test probe tip is reversible relative to a test probe body. The reversible probe has a first probe tip at a first end and a second probe tip at a second end. The test probe body has an opening operable to receive the first probe tip and the second probe tip. When the first probe tip is positioned in the opening, the first probe tip is electrically coupled to a metal device in the test probe body. When the second probe tip is positioned in the opening, the second probe tip is electrically coupled to a metal device in the test probe body. In another embodiment, a test probe having two test probe tips is reversible relative to a test lead.

Abstract: An inspection method includes performing an inspection by applying a probe to pads of a contact check pattern located, together with a chip pattern, on a wafer, and performing an inspection by applying the probe to pads of the chip pattern if a result of the inspection using the contact check pattern is within a predetermined range. A pattern having the same size as that of the chip pattern, differing in external appearance from the chip pattern, and having the same pads as those of the chip pattern is used as the contact check pattern.

Abstract: Disclosed is a probe (21) for an oscilloscope (24) comprising a multi-stage transistor amplifier (26) which is used as an impedance transformer and the output of which is connected to the oscilloscope (24). An electronic switching device (27) that can be remote-controlled by means of the oscilloscope (24) is assigned to the input (Vin) of the amplifier (26). Said electronic switching device (27) allows frame potential or a reference voltage to be alternatively connected to the amplifier input (Vin) instead of the measuring-circuit voltage of the measuring tip (22) such that the direct voltage offset is measured when the amplifier input (Vin) is connected to frame while the gain error in the oscilloscope (24) is measured when the reference voltage is applied, and said direct voltage offset or gain error is adequately taken into account when the measuring-circuit voltage in the oscilloscope is evaluated.

Abstract: A method for producing a defect card for individual dies located on a wafer, comprising: producing first and second defect cards, where the defective individual dies whose adjoining individual dies form an environment having a defect density up to a first value (?1) are classified as defective on the first defect card, and where the defective individual dies which are not considered upon the production of the first defect card are classified as defective on the second defect card; producing a third defect card by classifying additional individual dies on the second defect card as defective, where adjoining individual dies of the additional defective individual dies form an environment having at least one defect density of a second value (?2), which second value is less than the first value (?1); and producing a fourth defect card by unifying the third defect card with the first defect card.