Abstract: A design for a wide input common mode voltage comparator is provided which reduces the delay between outputs from component comparators. The wide input common mode voltage comparator includes a first comparator configured to receive a differential input. The first comparator is further configured to accommodate high common mode voltages. The wide input common mode voltage comparator further includes a second comparator configured to receive the differential input. The first comparator is further configured to accommodate low common mode voltages. Additionally, the threshold voltages of the active devices within the comparator are between ?100 to 100 mV. Furthermore, the wide input common mode voltage comparator includes a summing circuit configured to receive the outputs of the first and second comparators to create a single-ended output.

Abstract: This device for quantization of an analogue signal, called the input signal, includes an electronic circuit, called the sign analysis circuit (110), designed to supply a first bit of the output signal, called the sign signal (Bs) which takes a first value when the input signal (Ve) is positive and a second value when the input signal (Ve) is negative. It includes in addition an electronic circuit, called the envelope analysis circuit (112), designed to supply a second bit of the output signal called the envelope variation bit (Bvar env), which takes a first value, called high value, when an envelope signal (Venv) of the input signal is increasing, and a second value, called low value, when the envelope signal (Venv) is decreasing.

Abstract: A current source generates a reference current. A first transistor is a depletion-type MOSFET arranged such that one terminal thereof is connected to the current source and its gate is connected to its source. A second transistor is an enhancement-type MOSFET arranged such that one terminal thereof is connected to the other terminal of the first transistor, the other terminal thereof is connected to a fixed voltage terminal, and its gate and drain are connected. A third MOSFET is an enhancement-type P-channel MOSFET arranged such that one terminal thereof is connected to the current source, the other terminal thereof is connected to the fixed voltage terminal, and its gate is connected to a connection node connecting the first and second transistors. A constant voltage circuit outputs at least a voltage that corresponds to the gate voltage of the third transistor or a voltage that corresponds to the gate voltage thereof.

Abstract: A communication system comprises a twisted pair communication link operably coupled to at least two driver stages for providing at least two independent input signals on the twisted pair communication link. The at least two independent input signals on the twisted pair communication link are summed and input to a comparator arranged to compare the summed signal to a reference value. The output of the comparator is input to the at least two driver stages. The outputs from the at least two driver stages are summed and fed back and summed with one or more of the independent input signals. In this manner, adverse effects due to non-ideal symmetry between components in a twisted pair communication link, such as a Controller Area Network system, are reduced.

Abstract: This document discusses, among other things, a multiple accessory detection apparatus and methods for identifying accessories coupled to a multi-pin connector of an electronic device. The apparatus can include a first reference generator, a second reference generator, a plurality of switches to couple an output of the second generator to an accessory device and a comparator. The comparator can generate identifying information about the accessory device using the reference information received from the first reference generator and test information received using the second reference generator.

Abstract: An electronic circuit (1) comprises an input stage (2) and a driver stage (3). The input stage (2) comprises first, second, third and fourth inputs (In1-In4), and is configured to generate a first intermediate signal (Int1) which is the sum or the weighted sum of the first and third input signals (In1, In3), and a second intermediate signal (Int2) which is the sum or the weighted sum of the second and fourth input signals (In2, In4). The driver stage (3) comprises an output (OUT), is configured to generate an output signal (6) present at the output (OUT), and is configured to directly compare the first and second intermediate signals (Int1, Int2) such that the output signal (6) indicates which of the two intermediate signals (Int1, Int2) is larger.

Abstract: A switch can be configured to receive a first signal at a first input and provide an output signal at an output, depending on a state of the switch. A switch state change can be delayed until an indication of a requested switch state different than a current switch state is received and the first signal reaches a threshold.

Abstract: A skew detection circuit includes a data sensing block configured to sense a first data that is transferred earliest and a last data that is transferred latest among a plurality of data which are transferred through different transfer paths, and generate a sensing result signal; and a detection signal generation block configured to compare an output signal of the data sensing block with a certain time, and generate a skew detection signal.

Abstract: Embodiments related to an undervoltage detector are described and depicted. An undervoltage detector is formed to detect a low input bias voltage with a voltage divider network including first and second series circuits of semiconductor devices coupled to terminals of the input bias voltage source, and a resistor voltage divider including first and second voltage divider resistors coupled in series with the first and second series circuits. A ratio representing the numbers of semiconductor devices in the series circuits is substantially equal to a ratio of resistances in the resistor voltage divider. The equality of the ratios may be corrected by the presence of other resistances in the undervoltage detector. The semiconductor devices are each coupled in a diode configuration. The first series circuit is coupled to a current mirror to provide a bias current for a comparator that produces an output signal for the undervoltage detector.

Abstract: A bulk voltage (VBB) level sensor for a semiconductor memory apparatus is disclosed. The VBB level detector includes a reference voltage generator for generating a first reference voltage of which level varies with temperature, a reference voltage comparator for receiving a second reference voltage and the first reference voltage to generate a third reference voltage, a bias generator for receiving the third reference voltage to generate a specific bias level, and a VBB sensor for receiving the bias level to detect VBB level.

Abstract: A system has a corrected unit, and a correction unit that performs binary search of a correction value with which an output of the corrected unit gets close to a reference value and feeds back the correction value to the corrected unit. The correction unit performs the additional comparison for comparing a first output of the corrected unit corresponding to a first correction value searched by the binary search and a second output, which is an output of the corrected unit corresponding to a second correction value that is adjacent to the first correction value and is an output that the voltage relationship to the reference value is opposite to the first output, and for selecting the first or second correction value corresponding to the first or second output closer to the reference value, and feeds back the selected correction value to the corrected unit.

Abstract: A comparator comprises a differential amplifier (T1, T2, T8, T9) having differential inputs (IN1, IN2) forming the comparator inputs, and a first and a second amplifier output (f1, f2) forming the comparator outputs of a first comparator stage, wherein the differential amplifier has first (T1, T8) and second (T2, T9) parallel branches. The comparator has a first current source circuit (32) defines a current to be driven through the differential amplifier, a second current source circuit (34) comprising a load driven by the first branch and a third current source circuit (36), comprising a load driven by the second branch. Circuitry (T6,T7) is provided for defining the voltage difference between the first and second amplifier outputs when the differential amplifier is in a stable state providing a differential output. This arrangement drives current through the two branches independently, so that the main transistors in each branch can be kept on to enable rapid response times.

Abstract: A power-on detector and a method thereof are provided. The power-on detector includes four transistors, two resistors, and a comparator. The power-on detector can detect an input voltage and then determine whether the power is turned on or not. The power-on determination is substantially immune to temperature variation. The power-on detector is noise-free and stable in various temperatures.

Abstract: A transmission circuit, which transmits a differential signal having pulse time larger than a predetermined minimum pulse time, includes: a driving unit for feeding the differential signal as a potential difference between two transmission lines; a driven unit for operating on the basis of the differential signal by receiving the differential signal by the potential difference between the two transmission lines; and a connecting resistor for electrically connecting the two transmission lines. Further, a connecting MOS transistor may be provided near a receiving end of the driven unit.

Abstract: A peak-hold circuit includes a differential amplifier having first and second transistors as a differential pair, the first transistor receiving an input signal at its gate, a third transistor connected between a first power supply and an output node connecting a gate of the second transistor, connectivity of the third transistor being controlled by the output of the differential amplifier, a capacitor for holding a peak voltage, connected between the output node and a second power supply, a resistor for discharging, which is connected in parallel to the capacitor, and a fourth transistor connected to the first transistor in parallel, the fourth transistor receiving at its gate an a reference voltage for limiting a voltage.

Abstract: Dead-time detector includes an N-type power switch and a resistor. The N-type power switch includes a first end coupled to the output end of the output-stage circuit for receiving an output voltage, a second end for outputting a dead-time detecting signal, and a control end for receiving a gate-controlling voltage. The resistor is coupled between the second end of the N-type power switch and a voltage source providing a high voltage for keeping the voltage of the dead-time detecting signal when the N-type power switch does not output the dead-time detecting signal representing “ON”. When the output voltage is so lower than the gate-controlling voltage that the N-type power switch is turned on, the N-type power switch outputs the dead-time detecting signal representing “ON”. When the dead-time detecting signal represents “ON”, the output-stage circuit leaves the dead-time state.

Abstract: A power-on detector and a method thereof are provided. The power-on detector includes four transistors, two resistors, and a comparator. The power-on detector can detect an input voltage and then determine whether the power is turned on or not. The power-on determination is substantially immune to temperature variation. The power-on detector is noise-free and stable in various temperatures.

Abstract: A comparator has P-channel field effect transistors that are supplied at respective gates with input voltages Vin and Vref, which are objects of comparison, and that act as a differential transistor pair; and N-channel field effect transistors that serve as current channels for respective drain currents of these two P-channel field effect transistors and that act as a current mirror circuit. The comparator outputs a drain voltage Vx of an N-channel field effect transistor as a signal showing a result of comparison between the two input voltages. An N-channel field effect transistor diode-connected to the comparator is interposed between drains of the N-channel field effect transistors.

Abstract: Method and means for random or systematic mismatch compensation for a memory sensing system are disclosed. A sense amplifier includes a bulk voltage source to set the bulk of the sensing transistor to be a voltage different than the voltage driving the sensing transistor. For an NMOS sensing transistor, a triple well is used with the variable bulk voltage. Differential sense amplifiers with various offset compensation are included. Intentional offset creation for useful purpose is also included.

Abstract: A switching apparatus and method for detecting an operating state is disclosed. One embodiment has a MOS transistor, a replica of the MOS transistor and an evaluation arrangement and detects the start of switching of the MOS transistor by comparing the gate-source voltages of the transistors.

Abstract: A semiconductor package includes a semiconductor chip having a circuit section. A first chip selection electrode passes through a first position of the semiconductor chip, and the first chip selection electrode has a first resistance and outputs a first signal. A second chip selection electrode passes through a second position of the semiconductor chip, and the second chip selection electrode has a second resistance greater than the first resistance and outputs a second signal. A signal comparison part is formed in the semiconductor chip and is electrically connected to the first and second chip selection electrodes. The signal comparison part compares the first signal applied from the first chip selection electrode to the second signal applied from the second chip selection electrode and outputs a chip selection signal to the circuit section depending upon the result of the comparison.

Abstract: A CMOS comparator having a high-speed reduced-output-swing is provided. The high-speed reduced-output-swing comparator may have a fully complementary CMOS design, be self-biased, and have a rail-to-rail input common-mode range. The self-biasing scheme yields a robust comparator with a low sensitivity to temperature, processing variations, supply-voltage variations, and common-mode input voltages. The fully-complementary design leads to a physically small device with low power consumption. The rail-to-rail input common-mode range leads to a versatile comparator which may take a wide range of inputs. The high-speed reduced-output-swing allows for a quick output response to changes in the input.

Abstract: There is provided a method that includes comparing a voltage level (Vs1) of a lower voltage supply bus to a voltage level (Vs2) of a higher voltage supply bus, and routing current from the lower voltage supply bus to the higher voltage supply bus if Vs2<Vs1. The lower and higher voltage supply busses provide power to a complementary metal oxide semiconductor (CMOS) circuit. There is also provided a circuit that employs the method.

Abstract: A device for comparing the peak value of a periodic voltage signal or a linear combination of periodic voltage signals with a reference voltage includes a reference transconductor element for converting the reference voltage into a reference current, respective transconductor elements for converting each of the periodic voltage signals into respective periodic current signals, a current-comparison node for comparing the respective periodic current signals with the reference current, generating a comparison current as a difference between the sum of the aforesaid periodic current signals and the reference current, a current rectifier supplied with the comparison current, a hold capacitor charged with the output current of the current rectifier, and a discharge-current generator in parallel to the hold capacitor.

Abstract: There is provided a PLL circuit 15, a voltage follower 19, and an output terminal 23, and a control voltage V1 of a voltage controlled oscillator circuit in the PLL circuit 15 is outputted to the output terminal 23 via the voltage follower 19.

Abstract: In a program circuit that can reduce exhaustion of a switching element that uses oxidation-reduction reactions of an electrolyte material, a voltage source (106) applies voltage to a switching element (100), a measurement circuit (107) measures a parameter that changes in accordance with the resistance value of the switching element (100), and a control circuit (104) causes the voltage source (106) to apply voltage to the switching element (100) while progressively increasing the voltage. The control circuit (104) further causes the voltage source (106) to halt the application of voltage when the parameter measured by the measurement circuit (107) reaches a prescribed value.

Abstract: A semiconductor device includes a differential circuit for receiving a differential signal at an input terminal and a detection circuit for outputting a detection signal when a predetermined signal is inputted to the input terminal. The detection circuit detects whether the differential signal becomes outside an electric input standard and outputs the detection signal.

Abstract: A voltage detection circuit of the present invention includes an NMOS transistor diode-connected, a gate and a drain thereof being supplied with a power supply voltage, a resistor connected between a source of the NMOS transistor and a ground potential, and a source voltage detection circuit receiving a voltage of the source, wherein an NMOS type transistor is employed as the NMOS transistor, a channel width and a channel length of the NMOS type transistor being set in such a manner that an operating point on a VG-ID curve of the NMOS type transistor may come to a certain point, at the certain point, a drain current of the NMOS type transistor being constant even if the temperature fluctuates.

Abstract: A method compensates for errors in an output signal of a comparator based/zero crossing based circuit. The method includes generating with a comparator based/zero crossing based switched capacitor circuit a first output signal with an input signal, generating with the comparator based/zero crossing based switched capacitor circuit a second output signal with the input signal of an opposite polarity, and subtracting the second output signal from the first output signal to generate a final output signal for the comparator based/zero crossing based switched capacitor circuit.

Abstract: An output-voltage control device includes a comparator which generates a comparison result after a given time passes from first timing of a first periodic signal, the comparison result being obtained by comparing a difference between an output voltage and a reference voltage with the first periodic signal, a first signal generator which generates a timing control signal which is at a first level before the given time passes from the first timing and which changes from the first level to a second level in a period in which the comparator outputs the comparison result after the given time passes, and a second signal generator which generates a control signal for controlling the output voltage in accordance with the comparison result and the timing control signal.

Abstract: A differential amplifier circuit, a differentiation circuit and an output amplifier circuit are provided. The differential amplifier circuit differentially amplifies differentially inputted signals and provides an output. The differentiation circuit differentiates the output of the differential amplifier circuit, and adds the differentiated output to a bias voltage of a constant current transistor of the output amplifier circuit. A voltage comparator capable of higher speed operation without increasing its current consumption is provided.

Abstract: A synchronous detection circuit includes: an offset compensation circuit which generates an offset compensation voltage to compensate an offset voltage superposed on a direct current voltage signal; and a temperature compensation circuit which generates a temperature compensation voltage to compensate variation of a direct current reference voltage that depends on a temperature in a signal path of a sensing circuit. In the circuit, the synchronous detection circuit synchronously detects an alternating current signal, the offset compensation voltage and the temperature compensation voltage are respectively superposed on the alternating current signal which is input into the synchronous detection circuit, and the synchronous detection circuit synchronously detects the alternating current signal on which the offset compensation voltage and the temperature compensation voltage have been superposed.

Abstract: The present invention relates to a method and an apparatus for reducing the quantity of values of a sampled signal which need to be stored. A value of the signal is stored if the value is outside, or at the edge of a, predefined value range whose size is determined by an upper limiting value and a lower limiting value. According to the invention, the size of the value range is changed, in particular is continuously reduced to zero, staring from a predefined starting size of the value range, which the values are being recorded.

Abstract: A test circuit with which the cost for checking the duty ratio of a clock signal is restrained. A sampling timing generating circuit, to which the measurement-target clock signal MCK is input, outputs first and second sampling trigger signals to A sample-and-hold circuit 102 respective prescribed timings before and after a timing that is one-half period of the measurement-target clock signal after a first edge of the measurement-target clock signal. The sample-and-hold circuit samples and holds the measurement-target clock signal in correspondence with respective ones of the first and second sampling trigger signals. The sample-and-hold circuit forms all or part of a scan path and outputs a signal, which is being held for checking the duty ratio, from a scan output terminal in response to a scan clock signal.

Abstract: A comparator circuit according to an embodiment of the present invention includes a comparator configured to compare an input signal voltage with a reference voltage obtained by smoothing the input signal by use of a resistor and a capacitor, and output a result of the comparison, a discharge circuit configured to compare a first addition signal which is obtained by adding a positive first voltage to the input signal voltage, with the reference voltage, and discharge the capacitor when the first addition signal is lower than the reference voltage, and a charge circuit configured to compare a second addition signal which is obtained by adding a negative second voltage to the input signal voltage, with the reference voltage, and charge the capacitor when the second addition signal is higher than the reference voltage.

Abstract: A comparator includes: a signal input terminal; a capacitor connected between the signal input terminal and a signal line; and a switching transistor for calibration which is turned on/off to periodically charge the capacitor with a voltage difference between a signal voltage and an operating point of the comparator, wherein an on-resistance of the switching transistor which is turned on when performing the charging is dynamically controlled by a control pulse having a limited amplitude.

Abstract: A semiconductor package includes a semiconductor chip having a circuit section. A first chip selection electrode passes through a first position of the semiconductor chip, and the first chip selection electrode has a first resistance and outputs a first signal. A second chip selection electrode passes through a second position of the semiconductor chip, and the second chip selection electrode has a second resistance greater than the first resistance and outputs a second signal. A signal comparison part is formed in the semiconductor chip and is electrically connected to the first and second chip selection electrodes. The signal comparison part compares the first signal applied from the first chip selection electrode to the second signal applied from the second chip selection electrode and outputs a chip selection signal to the circuit section depending upon the result of the comparison.

Abstract: A digital filter device capable of removing the effect of noise such as chattering from a zero crossing signal is provided. A digital filter device 4 filtering a binary digital signal DIN and outputting a binary digital signal DOUT is provided with a toggle flip-flop 12 which switches a signal level of the digital signal DOUT each time a trigger signal is input; an XOR circuit 13 which outputs a first enable signal EN1 while a signal level of the digital signal DIN does not match with the signal level of the output digital signal DOUT; and a charge counter 14 which counts in synchronization with a clock signal CLK while the first enable signal EN1 is input and resets the count to an initial value and outputs a carry on signal ON_RCO as the trigger signal to the toggle flip-flop 12 when the count has reached an upper limit value.

Abstract: Described are methods and circuits for margin testing digital receivers. These methods and circuits prevent margins from collapsing in response to erroneously received data, and can thus be used in receivers that employ historical data to reduce intersymbol interference (ISI). Some embodiments detect receive errors for input data streams of unknown patterns, and can thus be used for in-system margin testing. Such systems can be adapted to dynamically alter system parameters during device operation to maintain adequate margins despite fluctuations in the system noise environment due to e.g. temperature and supply-voltage changes. Also described are methods of plotting and interpreting filtered and unfiltered error data generated by the disclosed methods and circuits. Some embodiments filter error data to facilitate pattern-specific margin testing.

Abstract: Techniques pertaining to a comparator circuit with reduced power consumption are disclosed. According to one aspect of the present invention, the comparator unit has a pair of input signal pins VIP and VIN, a pair of output signal pins VOR and VOS, and a clock signal pin CLK. In operation, when the CLK signal is at an idle voltage level, the comparator unit comes into an idle state. At the idle state, the comparator unit does not compare the two input signals VIP and VIN so that the output signals are identical. When the CLK signal is at a busy voltage level, the comparator comes into a busy state. At the busy state, the comparator compares the input signals VIP and VIN, and determines the values of the output signals VOR and VOS depending on the comparing result, e.g., if the input signal VIP is larger than the input signal VIN, the output signal VOR is high and the output signal VOS is low; otherwise, the output signal VOR is low and the output signal VOS is high.

Abstract: A method includes receiving a set of voltages comprising at least a first voltage, a second voltage, and a third voltage and biasing a well of a transistor based on the extreme voltage of the set of voltages. Biasing the well of the transistor can include concurrently providing a first signal and a second signal based on a comparison of the first voltage and the second voltage and selectively coupling the well of the transistor to a source of the extreme voltage of the set of voltages based on the first signal, the second signal, and the third voltage. An electronic device comprises a transistor and a power switching module. The power switching module includes a set of inputs, each input configured to receive a corresponding one of a set of voltages comprising at least a first voltage, a second voltage, and a third voltage, and includes an output coupled to a well of the transistor, the output configured to provide the extreme voltage of the set of voltages.

Abstract: A circuit and method for providing a sense amplifier for a DRAM memory with reduced distortion in a control signal, the sense amplifier particularly useful for embedding DRAM memory with other logic and memory functions in an integrated circuit. A sense enable circuit is provided for a differential sensing latch in a sense amplifier having a cascade coupled pair of transistors, each transistor receiving a separate control signal. The separate control signals are provided by a control circuit with a delayed overlap. Differential sensing is enabled when the delayed overlap exists between the separate control signals. An array of DRAM memory cells are coupled to a plurality of the sense amplifiers. The DRAM memory incorporating the sense amplifiers may be embedded with other circuitry in an integrated circuit. Methods for providing the control signals and for laying out the DRAM memory with the sense amplifiers are provided.

Abstract: A zero-crossing detector with effective offset cancellation includes a set of series connected capacitors and an amplifier having an input terminal. An offset capacitor is operatively connected between the amplifier and the set of series connected capacitors. A switch is operatively connected to the input terminal, and an offset sampling capacitor is operatively connected to the switch. The switch connects the offset sampling capacitor to the input terminal of the amplifier during a charge transfer phase.

Abstract: A CMOS comparator having a high-speed reduced-output-swing is provided. The high-speed reduced-output-swing comparator may have a fully complementary CMOS design, be self-biased, and have a rail-to-rail input common-mode range. The self-biasing scheme yields a robust comparator with a low sensitivity to temperature, processing variations, supply-voltage variations, and common-mode input voltages. The fully-complementary design leads to a physically small device with low power consumption. The rail-to-rail input common-mode range leads to a versatile comparator which may take a wide range of inputs. The high-speed reduced-output-swing allows for a quick output response to changes in the input.

Abstract: Described are methods and circuits for margin testing receivers equipped with Decision Feedback Equalization (DFE) or other forms of feedback that employ historical data to reduce intersymbol interference (ISI). In one example, a high-speed serial receiver with DFE injects the correct received data (i.e., the “expected data”) into the feedback path irrespective of whether the receiver produces the correct output data. The margins are therefore maintained in the presence of receiver errors, allowing in-system margin tests to probe the margin boundaries without collapsing the margin limits. Some receivers include local expected-data sources that either store or generate expected data for margin tests. Other embodiments derive the expected data from test data applied to the receiver input terminals.

Abstract: A low-current differential signal activity detector circuit may be configured to reject large common mode signals on differential input lines, while still detecting smaller differential signals applied to the same set of differential input lines. The detector circuit may comprise a translinear buffer that is driven at the buffer input and at the buffer output by the differential input signals. The differential signal thereby driving the inputs of the detector circuit may be half-wave rectified through the buffer output devices and may be filtered to provide the detected output. When applying a common mode signal, the buffer's input and output may track each other, and no current may be rectified in the output devices, thus providing common-mode signal rejection. The detector circuit may also be configured with two buffers having their outputs coupled to a common node, each buffer input driven by a respective one of the differential input signals.

Abstract: A radio frequency (RF) receiver device comprises a receiver system that receives an analog radio frequency signal and downconverts the analog radio frequency signal to a downconverted analog signal, the receiver system further including a peak signal detector configured to determine a peak signal level of the downconverted analog signal, and an automatic gain control adjustment element configured to determine whether the peak signal level falls within a predetermined range, and configured to generate, in the RF receiver, a gain control signal controlling the gain of at least one analog component based on whether the peak signal level falls within the predetermined range.

Abstract: The present invention involves an electrical system in which an analog signal channel passes through various integrated circuit chips (ICs). The channel can carry one or more analog signals. Each IC can modify the signal(s) passing through it and pass it on to another IC or system component. The channel can be programmable. Each IC can include a comparator or a multiplexor to receive the channel signal from another IC or system component and to modify the received signal before transmitting it to another IC or system component. The comparator or the multiplexor can be programmable and can be selectively configured to compare the incoming signal from the channel with a variety of other signals and thresholds, or to simply act as a flow through gate and allow the signal to pass without any modification. The comparison can determine the output of the comparator.

Abstract: Described are methods and circuits for margin testing digital receivers. These methods and circuits prevent margins from collapsing in response to erroneously received data, and can thus be used in receivers that employ historical data to reduce intersymbol interference (ISI). Some embodiments allows feedback timing to be adjusted independent of the sample timing to measure the effects of some forms of phase misalignment and jitter.

Abstract: A detecting circuit is disclosed. In the detecting circuit, when an input detection voltage Vsns which is obtained by dividing an input voltage Vin by resistors is equal to a reference voltage Vref or more and a temperature detection voltage Tsns is equal to the reference voltage Vref or more due to a low temperature, a detection signal SNS from a comparator becomes a high level. In addition, when the input detection voltage Vsns is less than the reference voltage Vref and/or the temperature detection voltage Tsns is less than the reference voltage Vref due to a high temperature, the detection signal SNS from the comparator becomes a low level.