Abstract: A semiconductor device includes a circuit section having an output impedance which changes in accordance with a switching signal for switching between drive capabilities, and transforming an input signal into an output signal in accordance with the output impedance, a reference voltage generating section generating a reference voltage in accordance with the switching signal and the input signal, and a comparing section comparing a voltage of the output signal to the reference voltage.

Abstract: A memory cell for storing a charge that gives rise to a cell voltage representing a bit value, the memory cell being capable of having the cell voltage boosted to a boost value at a time following reading of the stored charge. The memory cell includes a first capacitor connected between a first node and ground. A second capacitor is connected between a second node and ground, and a first switch is connected between the first node and the second node. A second switch and a third capacitor are connected in series between the first node and the second node, with a terminal of the second switch being connected to the first node, the common connection node of the second switch and the third capacitor comprising a third node. A third switch is connected between the third node and ground. In operation, in a first storage phase the first and third switches are closed and the second switch is open.

Abstract: A level translator has an inverter comprising a first transistor having a first predetermined voltage threshold and a second transistor having a second predetermined voltage threshold. The two transistors have control gates being of complementary conductivity. A first capacitor is connected at one end to the gate of the first transistor and at a second end to an input signal. A second capacitor is connected at one end to the gate of the second transistor, the input signal being applied to a second end of the second capacitor. A comparator is used for detecting the relationship between the input signal and a reference voltage. A first current mirror has one terminal connected to an output of the comparator, and another terminal connected to the gate of the first transistor. A second current mirror has one terminal connected to an output of the comparator, and another terminal connected to the gate of the second transistor. A first clamp circuit is used for limiting a gate voltage of said first transistor.

Abstract: A data holding circuit including a first input terminal through which data is inputted; at least one delay element for delaying the data inputted through the first input terminal; and a first element for holding data, wherein, when the data inputted through the first input terminal and the data delayed by the delay element are equal to each other, the first element holds data corresponding to the data inputted through the first input terminal and wherein, when the data inputted through the first input terminal and the data delayed by the delay element are different from each other, the first element continues to hold the data presently held by the first element.

Abstract: A memory module having a DRAM device configured to generate a low DQS state on a DQS line, and a buffer coupled to the DRAM device, the buffer having a plurality of drivers, wherein the buffer is configured to detect the low DQS state by comparing the low DQS state to a low voltage level of one of the plurality of drivers.

Abstract: A voltage comparison circuit makes a comparison between a first voltage and a second voltage. A resistor and a constant current source are provided in series between the first voltage and the ground voltage. A comparator receives the second voltage via one input terminal (non-inverting input terminal), and the voltage at a connection node between the aforementioned resistor and the constant current source via the other input terminal (inverting terminal). The first voltage is preferably used as the power supply voltage for the comparator.

Abstract: An automatic adjustment system that includes: a transmission device that includes a constant voltage output unit that outputs a constant-voltage signal to a cable; and a reception device that includes a voltage detecting unit and a control unit. The voltage detecting unit receives the constant-voltage signal transmitted through the cable and detects the voltage of the signal, and the control unit determines signal attenuation based on the voltage detected by the voltage detecting unit and adjusts the gain of a receiving unit that receives the signal from the transmission device. This automatic adjustment system performs gain adjustment on the receiving unit when a cable insertion/pull-out sensing unit senses that the cable is connected to a connector.

Abstract: A semiconductor device 10a includes a normal circuit 11 and a voltage fluctuation detection circuit 12a connected to a power supply 100 in common with the normal circuit 11. The voltage fluctuation detection circuit 12a includes an inverting amplifier 13a, a switching element 14, which is connected between input and output terminals of the inverting amplifier 13a, and a capacitance element 15 connected to the input terminal of the inverting amplifier 13a. After the normal circuit 11 and the switching element 14 are set to an operating state and ON state, respectively, when the switching element 14 is set to OFF state at an arbitrary time, charge corresponding to a power supply voltage Vc0 at that time accumulates in the capacitance element 15.

Abstract: A circuit drives an LED array and controls the brightness of the LED array by regulating the current flowing through the array. The LED array is driven by a pulse-shaped current of which the mean value is regulated with at least one or two of the following types of modulation: frequency modulation, pulse-width modulation, and amplitude modulation.

Abstract: According to the present invention, there is provided a semiconductor device comprising: a power line to be externally supplied with a power supply voltage; a ground line for grounding; a first signal line for transmitting a first signal; a second signal line for transmitting a second signal; a first switching element and first resistance element connected in series between said first signal line and a power terminal which supplies a predetermined potential; a second switching element and second resistance element connected in series between said second signal line and said ground line; and a controller which is connected to said power line, said ground line, said first signal line, and said second signal line, and, when detecting that a potential of said power line has reached the power supply voltage, turns on said first switching element and said second switching element, and turns off said second switching element after an elapse of a predetermined time.

Abstract: The present invention relates to a simple and small-sized circuit configuration (10) for significantly reducing resettling time of a peak or zero current comparator. This circuit configuration (10) provides the comparator input stage with an alternative current path at the comparator input submitted to a large voltage variation able to disturb the DC-settings. This circuit configuration (10) comprises a pair of small transistors (P3, P4) coupled to a differential pair of transistors (N1, N2) of the comparator input stage and having a polarity different from said pair of transistors (P3, P4). The gates of the transistors P3 and P4 share a common terminal connected to said comparator input. The currents and voltages across the comparator are always maintained close to the normal DC-setting values during the voltage transition phase. This circuit configuration (10) can be used in any current comparator for detecting a peak or a zero current, in particular, in DC-DC converters based on a switched operating mode.

Abstract: In one embodiment of the present invention, an operational amplifier circuit, a switching element is closed and a switching element is opened. A latch circuit DL latches an output voltage of an operational amplifier and supplies a Q output corresponding to the output voltage. A control circuit supplies an offset adjustment signal to an offset adjustment input terminal OR of the operational amplifier, thereby adjusting an offset of the output voltage. The latch circuit DL latches again the output voltage thus adjusted and minutely adjusts the offset adjustment signal so as to adjust the remaining offset. Weighting is carried out in accordance with how many times latching has been carried out, and the offset of the output voltage of the operational amplifier is quantized, thereby obtaining a binary logical signal and storing the signal in the control circuit.

Abstract: A system for identifying asserted signals includes a plurality of input ports, a priority encoding module, and a match module. The plurality of input ports receive one of a plurality of input signals. The priority encoding module is coupled to the plurality of input ports and outputs a signal indicating a highest-priority input signal that is asserted. The match module is also coupled to the plurality of input ports and receives a plurality of match detect signals from the priority encoding module. Each match detect signal is associated with a particular input signal and indicates whether another input signal having a higher-priority than the associated input signal is asserted. The match module also generates a multiple match signal based on the input signals and the match detect signals. The multiple match signal indicates whether more than one of the input signals is asserted.

Abstract: A voltage comparator having hysteresis includes a comparing section that compares an input voltage with a reference voltage so as to output a high-level or low-level signal; and a reference voltage changing section that changes the reference voltage when a low-level signal is output from the comparing section.

Abstract: Aspects of a method and system for wide range amplitude detection are provided. In this regard, many electronic systems may require amplitude detection of a variety of signals with widely varying amplitudes. Aspects of the invention may comprise suitable logic, circuitry, and/or code to perform amplitude detection and may be easily configured to accommodate a wide range of amplitudes. In this regard, the configuration of the amplitude detector may be performed via simple design changes and/or may be dynamically configured by suitable logic, circuitry, and/or code. Accordingly, multiplexing a single instance of the wide range amplitude detector and/or multiplexing multiple instances of the wide range amplitude detector may result in reduced design time, reduced circuit size, and/or reduced cost.

Abstract: An on-chip mode-setting circuit and method are provided for a chip having an output driver with an output terminal connected to a pin of the chip. The pin may be defined between two states from exterior of the chip. The on-chip mode-setting circuit includes an electronic element connected to a bias input of the output driver for producing a voltage when the pin is defined at one of the two states, and a voltage detector for monitoring the voltage to determine which one of the two states the pin is at, and producing a mode-setting signal accordingly.

Abstract: This invention provides a comparator circuit which outputs a stable waveform without oscillation even if a gradient of a change of a comparison input signal is small and determines a magnitude of the comparison input signal within a predetermined threshold value regardless of the increase/decrease direction of the comparison input signal.

Abstract: Various embodiments of the present invention are directed to a binary signal converter that facilitates distinguishing an original direct signal on a nanowire by superimposing an alternating signal on the original direct signal. The binary signal converter includes an alternating signal source connected to the nanowire that superimposes an alternating signal with an initial amplitude on the nanowire. The binary signal converter may also include a selective alternating signal filter that selectively passes the alternating signal from the nanowire to a signal sink.

Abstract: A low current consumption detector circuit, and its applications are described herein.

Abstract: A system for controlling bias of a delay-locked loop includes a peak detector and a comparator in the form of a differential amplifier. The peak detector detects the amplitude of a signal output from the DLL, and the comparator compares the DLL output signal amplitude to a reference signal. The comparator then generates a tail current control signal for the DLL based on a result of the comparison. In one embodiment, the reference signal is indicative of a predetermined tail current value for the DLL, and the tail current control signal adjusts delay of the DLL to equal the predetermined tail current value. Preferably, the tail current control signal maintains the DLL signal output at a substantially constant amplitude in spite of frequency variations and may also be used to set the voltage swing for the DLL.

Abstract: Current through a wire is sensed with a shunt resistor and a sense resistor in a current divider circuit. The values of the shunt resistor and sense resistor are related to provide a specified gain ratio to increase a dynamic range of current measurement. The sense resistor is a trimmable resistor, the configuration of which can be discerned from a look-up table based on a level of precision needed for current measurement. The two resistors can also be related by thermal coefficients to improve linearity of current measurements.

Abstract: A comparator circuit that operates over a wide range of input voltage from Vss to Vdd is offered. This comparator circuit includes a first comparator receiving a pair of differential input signals from input terminals, a second comparator to which a pair of differential outputs of the first comparator is inputted, a current source that provides the pair of differential outputs of the first comparator with a very low current that flows to a ground and a third comparator that receives the pair of differential input signals from the input terminals. A differential output of the second comparator and a differential output of the third comparator are combined to make an output signal. The output signal is received by to an inverter. The first comparator is a P-type comparator while the second and the third comparators are N-type comparators.

Abstract: A sense amplifier according to the present invention for detecting a potential difference of signals input to a first input terminal and a second input terminal, includes a first means for applying voltages corresponding to threshold voltages of first and second transistors to gate-source voltages of the first and second transistors, and a second means for transferring signals input to the first and second input terminals to gates of the first and second transistors. In this case, a threshold variation of the first and second transistors is corrected.

Abstract: A valid data strobe detection technique detects a valid data strobe contained within a strobe signal by first determining whether a measured voltage level of the strobe signal is above or below a preselected threshold level. A time period in which the measured voltage level is continuously one of either above or below the preselected threshold level is then measured and a valid data strobe is detected upon the measured time period being greater than a preselected period of time. A comparator may be used to determine whether the measured voltage level of the strobe signal is above or below the preselected threshold level and a sample and hold unit may be used to measure the time period in which the strobe signal is one of either above or below the preselected threshold level.

Abstract: Two all pass filters (11, 12) with 90° phase-shifted different center frequencies are employed to pass an alternating signal S with jitters in the period to generate signals S1 and S2, 90° phase-shifted from each other. A pulse generator (22) generates a sampling pulse Sp by detecting a zero cross point of the phase-shifted signal S2. A full-wave rectifier (21) rectifies full waves of the phase-shifted signal S1 and provides a rectified output to a sampling circuit (23), which extracts a peak value of the amplitude at the timing of the sampling pulse Sp.

Abstract: A method and circuit are disclosed for detecting the performance of an oscillator circuit. In particular, the circuit may detect a signal, such as the output of the oscillator circuit, failing to oscillate as desired. The second circuit may be capable of detecting whether the signal oscillates at a frequency that is less than a predetermined frequency. The second circuit may include timing circuits for determining whether the signal remains in a first logic state for at least a predetermined period of time and whether the signal remains in a second logic state for at least the predetermined period of time.

Abstract: In transmitting a first pair of differential clock signals UCLK, UXCLK having an extremely small amplitude voltage based on a power-source potential and a second pair of differential clock signals LCLK, LXCLK having an extremely small amplitude voltage based on the power-source potential, an inverting circuit as a signal receiving circuit is composed of a CMOS inverting circuit. A PMOS transistor composing the CMOS inverting circuit has a gate electrode and a source electrode receiving the first pair of differential clock signals. An NMOS transistor composing the CMOS inverting circuit has a gate electrode and a source electrode receiving the second pair of differential clock signals. When the potentials of the differential clock signals change, potentials at the respective gate and source electrodes of the two transistors shift in opposite directions, which surely cuts off the transistors.

Abstract: A frequency margin testing blade is adapted for use in a bladed server. The testing blade is further adapted to provide one or more output clock signals for use as clock inputs to one or more server blades internal to the bladed server in which the testing blade is installed and/or one or more server blades external to the bladed server in which the testing blade is installed.

Abstract: A multi-way set associative cache memory includes a set selection signal operating a sense amplifier. In reading data stored in a set, a set selection signal enables the sense amplifier to select one of sets while plural sets are active by a row address. The simplified structure of the present cache memory reduces power consumption by the rate of 1/N (N is the number of sets).

Abstract: The present invention relates to a temperature detecting circuit. The temperature detecting circuit includes a first delay means for outputting a reference signal that is delayed by some time according to an input signal without being affected by variation in temperature, a second delay means for delaying the input signal in different delay time according to variation in temperature to generate a plurality of delay signals, a detecting means for comparing the reference signal and the plurality of the delay signals, respectively, to output a plurality of detecting signals, an encoder for encoding the plurality of the detecting signals into given numbers of output signals, a buffer for outputting the output signal of the encoder to the outside and receiving a control signal from the outside as an input, and a select means that can be programmed according to the control signal, for selecting one of the detecting signals according to a program state.

Abstract: A device which uses a detection circuit to determine whether an output current thereof is source-induced or load-induced, and the method therefor. The device which performs some type of operation based upon the determination as to whether the output current thereof is source-induced or load-induced, and method therefor. The detection circuit determines whether polarities of the output current and an output voltage are the same, and determines the output current to be source-induced if the polarities are the same and load-induced if the polarities are opposite each other. Such a device may have many applications, including use in systems where distinctions between source and load-induced currents are employed in feedback systems to control the system voltage source, systems where the system voltage source is not controlled, but other sources are controlled to influence a summation of voltages and currents at sensing locations, and systems for measurement instrumentation.

Abstract: Provided is a circuit to perform single-ended to differential conversion while providing common-mode voltage control. The circuit includes a converter to convert a single-ended signal to a differential signal and a stabilizing circuit adapted to receive the differential signal. The stabilizing circuit includes a sensor configured to sense a common-mode voltage level of the differential signal and a comparator having an output port coupled to the converter. The comparator is configured to compare the differential signal common-mode voltage level with a reference signal common-mode voltage level and produce an adjusting signal based upon the comparison. The adjusting signal is applied to the converter via the output port and is operative to adjust a subsequent common-mode voltage level of the differential signal.

Abstract: A device which uses a detection circuit to determine whether an output current thereof is source-induced or load-induced, and the method therefor. The device which performs some type of operation based upon the determination as to whether the output current thereof is source-induced or load-induced, and method therefor. The detection circuit determines whether polarities of the output current and an output voltage are the same, and determines the output current to be source-induced if the polarities are the same and load-induced if the polarities are opposite each other. Such a device may have many applications, including use in systems where distinctions between source and load-induced currents are employed in feedback systems to control the system voltage source, systems where the system voltage source is not controlled, but other sources are controlled to influence a summation of voltages and currents at sensing locations, and systems for measurement instrumentation.

Abstract: For providing a hysteresis characteristic setting device configured by components smaller in number than those of a logic circuit or a comparator circuit for setting a hysteresis characteristic, the device comprises a resistor voltage dividing circuit including two resistors; and a microcomputer including first and second ports and serving as input ports. When an output signal from a low-pass filter circuit is supplied to the device, the voltage of the signal is divided by the two resistors of the resistor voltage dividing circuit and then given to the second port. The microcomputer performs a process according to a combination of levels Hi and Lo detected in the ports, to set a hysteresis characteristic in which an input voltage level corresponding to a threshold voltage level of the first port is a lower limit, and that corresponding to a threshold voltage level of the second port is an upper limit.

Abstract: An envelope tracking amplification system that includes an envelope tracking power supply (ETPS) amplifies a radio frequency (RF) signal to produce a linearized amplified signal. The envelope tracking amplification system samples the RF signal to produce a sampled RF signal. The ETPS produces a control signal based on an instantaneous magnitude of the sampled RF signal and further based on an average magnitude of the sampled RF signal, produces multiple supply voltages, and, based on the control signal, couples a supply voltage of the multiple supply voltages to an output of the EPTS to produce an output supply voltage. The envelope tracking amplification system then amplifies the RF signal based on the output supply voltage to produce a highly linear amplified signal.

Abstract: A successive approximation routine analog-to-digital converter includes a switched-capacitor circuit that samples an input voltage into a plurality of capacitors without the need for power to be dissipated by the analog-to-digital converter. A comparator, coupled to the switched-capacitor circuit, compares a voltage across the capacitors with another voltage during each of a number of iterations. A common mode voltage of the switched-capacitor circuit is boosted during at least some of the iterations. The boost may be accomplished in many different ways and may be different for each of a single-ended, a quasi-differential and fully differential versions of the analog-to-digital converter.

Abstract: Methods and apparatus of signal processing are described. In a method according to one embodiment, a high-frequency region of a digital signal is detected. In response to the detecting, the high-frequency content of the digitized signal is increased in at least a portion of that region.

Abstract: A charge/discharge current detection circuit includes a detection resistance that converts a charge current and a discharge current to a detection voltage, a level shifter circuit that level-shifts the detection voltage by a predetermined value, and an amplifier circuit that amplifies an output voltage of the level shifter circuit and outputs the amplified output voltage of the level shifter circuit. The level shifter circuit applies to the detection voltage a predetermined divided voltage obtained by resistance-dividing a reference voltage, to thereby level-shift the detection voltage.

Abstract: A polyphase amplitude detector for detecting the amplitude of a polyphase signal. The polyphase amplitude detector includes means for generating differential pair signals. The differential pair signals are buffered and amplified and then AC coupled to the amplitude detector. The amplitude detector detects the amplitude of each phase of the polyphase signal and generates output signals which are used to control the amplitude of the polyphase signal.

Abstract: In a comparing circuit, an input signal switching circuit has a first input terminal, a second input terminal, a first output terminal and a second output terminal. The input signal switching circuit is configured to receive a first input signal inputted to the first input terminal and a second input signal inputted to the second input terminal. The input signal switching circuit is also configured to output the first input signal to switchably one of the first and second output terminals and the second input signal to other thereof in accordance with a switching signal. A comparator has a reverse input terminal and a non-reverse input terminal and configured to receive through the reverse input terminal a first signal outputted from the first output terminal, and receive through the non-reverse input terminal a second signal outputted from the second output terminal.

Abstract: A device which uses a detection circuit to determine whether an output current thereof is source-induced or load-induced, and the method therefor. The device which performs some type of operation based upon the determination as to whether the output current thereof is source-induced or load-induced, and method therefor. The detection circuit determines whether polarities of the output current and an output voltage are the same, and determines the output current to be source-induced if the polarities are the same and load-induced if the polarities are opposite each other. Such a device may have many applications, including use in systems where distinctions between source and load-induced currents are employed in feedback systems to control the system voltage source, systems where the system voltage source is not controlled, but other sources are controlled to influence a summation of voltages and currents at sensing locations, and systems for measurement instrumentation.

Abstract: A device which uses a detection circuit to determine whether an output current thereof is source-induced or load-induced, and the method therefor. The device which performs some type of operation based upon the determination as to whether the output current thereof is source-induced or load-induced, and method therefor. The detection circuit determines whether polarities of the output current and an output voltage are the same, and determines the output current to be source-induced if the polarities are the same and load-induced if the polarities are opposite each other. Such a device may have many applications, including use in systems where distinctions between source and load-induced currents are employed in feedback systems to control the system voltage source, systems where the system voltage source is not controlled, but other sources are controlled to influence a summation of voltages and currents at sensing locations, and systems for measurement instrumentation.

Abstract: A transmission signal which is output from a power amplifier is rectified by a first rectifying circuit and is then input to a first transistor of a voltage-to-current converting circuit, while the reference voltage is output from a second rectifying circuit and is then input to a second transistor of the voltage-to-current converting circuit. The output current of the first transistor is subtracted from the output current of the second transistor via a first current-mirror circuit, and a current that is proportional to the output voltage of the power amplifier is caused to flow to a two-terminal p-n junction electronic device. Then, a voltage that is proportional to the logarithm of the current is output from across the p-n junction electronic device.

Abstract: The invention relates to a transmitting device and a bus system for the serial data transfer of binary data between at least two communication stations, which are coupled to one another via an individual bus line. The transmitting device of a communication station has a circuit for waveform setting. The circuit for waveform setting generates, from a data signal to be transmitted, an output signal having signal edges which are as far as possible in the form of sinusoidal half-waves. In order to generate the signal edges in the form of sine half-waves, an oscillator, a clock counter and a parallel D/A converter are connected in series one after the other. The output signal at the output of the D/A converter has stepped edges. An optimized output signal having signal edges in the form of sine half-waves can be generated by means of suitable dimensioning of the reference elements of the voltage divider of the D/A converter and also by means of a smoothing filter connected downstream of the D/A converter.

Abstract: The inverter functioning as a comparator, dummy inverter having the same electric characteristics as the inverter, and control circuit are provided. Vth detecting input voltage output from the control circuit is input into the dummy inverter, Vth detecting output voltage output from the dummy inverter is input into the control circuit, and the threshold voltage of the dummy inverter is detected. The threshold voltage of the inverter is controlled by controlling the back gate voltages of the MOS transistors of the dummy inverter and the inverter in such a manner that the threshold voltage of the dummy inverter coincide with an external reference voltage.

Abstract: In the circuit for detecting the voltage level of an analog signal, a conversion circuit converts an analog signal to digital signals by comparing the voltage level of the analog signal with a plurality of reference potentials. A filter circuit matches timings of at least either rising edges or falling edges of the digital signals with each other. This prevents malfunction in the voltage level detection.

Abstract: A semiconductor integrated device has a detection cell arranged in a power-supply line in the semiconductor integrated device and detecting a power-supply voltage. Further, a detection circuit detects a voltage drop of the power-supply voltage detected by the detection cell. Connection wiring connects the detection cell and the detection circuit and outputs the power-supply voltage detected by the detection cell to the detection circuit.

Abstract: A signal transmission system has a response time of a signal transmission line which is set approximately equal to or longer than the length of a transmitted symbol. More specifically, terminal resistance is set larger than the characteristic impedance of the signal transmission line, driver output resistance is set to a large value, or a damping resistor is provided in series with the signal transmission line. With this configuration, signal power can be reduced drastically.

Abstract: In a semiconductor switch, a voltage detection circuit is provided so as to be in parallel with a first switching element for turning on/off a power supply to a load, in which a voltage detection portion for detecting a drain voltage of the first switching element by dividing a voltage upon a resistance ratio or the like and a second switching element are connected in series to each other. The second switching element is turned on/off in accordance with ON/OFF of the first switching element. Accordingly, detection of a drain voltage is performed normally when the first switching element is in an ON state. When the first switching element is in an OFF state, a leakage current can be reduced by the second switching element.

Abstract: A impedance-to-voltage converter for converting an impedance of a target to a voltage is described which comprises an operational amplifier (OP), a coaxial cable consisting a signal line and shielding element(s), and an AC signal generator. A feedback impedance circuit is connected between output and inverting terminals of the OP, and whereby a non-inverting terminal and the inverting terminal are an imaginal-short condition. One end of the signal line is connected to the inverting input terminal of the OP and the other end is connected to one electrode of the target and the AC signal generator is connected to the non-inverting input terminal of the OP. The shielding element comprises at least one shielding layer surrounding the signal line and is connected to the non-inverting input terminal of the OP, and thus the signal line and the shielding layer are the same voltage due to the imaginal-short of the input terminals of the OP, resulting in reduction of noise on the signal line.