Abstract: A method and an apparatus for forming a transistor suitable for a high voltage circuit. In one embodiment, the transistor is formed without adding any steps to an existing state-of-the-art CMOS process. A well is implanted into a portion of a substrate such that the well has a higher doping concentration than the substrate. A first diffusion region is then implanted into the substrate such that at least a portion of the first diffusion is disposed within the well. In addition, a second diffusion is implanted into the substrate separated from the well such that the second diffusion region is disposed entirely outside the well. A channel region is disposed between the first and second regions and gate is disposed over the channel region to form the high voltage transistor. Since the second diffusion region is disposed entirely outside the well in the lower doped substrate, a higher junction breakdown voltage is realized.

Abstract: An epitaxial layer is formed on a P type silicon substrate in which a plurality of P+ buried layer regions, a plurality of N+ buried layer regions, and a P+ field layer region occupying most of the substrate surface are diffused. The substrate is loaded in a reactor with a carrier gas. The substrate is pre-baked at a temperature of approximately 850.degree. C. As the substrate is heated to a temperature of 1050.degree. C. N+ dopant gas is injected into the carrier gas to suppress autodoping due to P+ atoms that escape from the P+ buried layer regions. The substrate is subjected to a high temperature bake cycle in the presence of the N+ dopant gas. A first thin intrinsic epitaxial cap layer is deposited on the substrate, which then is subjected to a high temperature gas purge cycle at 1080.degree. C. A second thin intrinsic epitaxial cap layer then is deposited on the first, and a second high temperature gas purge cycle is performed at 1080.degree. C.

Abstract: A method of patterning a layer on sidewalls of a trench in a substrate for integrated circuits includes the steps of forming an insulator layer on sidewalls of a trench in a substrate with a horizontal top surface above the sidewalls, recessing a masking material such as an organic photoresist in the trench below the top surface of the substrate such that a portion of the insulator layer on the sidewalls of the substrate is exposed, and etching the insulator layer with a gaseous hydrogen flouride-ammonia mixture. The masking material and the substrate are composed of a different material than the insulator layer.

Abstract: A method of fabricating a compound semiconductor layer structure including a layer containing nitrogen is provided. In a method of fabricating a device including a compound semiconductor layer structure, a portion of crystal of compound semiconductor, which is to be at least a portion of a function layer of the device, is irradiated with material including at least nitrogen, and element of V group of the irradiated portion is substituted by the nitrogen. In a fabrication method, a thickness of the N-substituted layer does not exceed its critical layer thickness. In a fabrication method, a depth of the N-substituted portion is controlled by using material for oppressing the substitution by nitrogen.

Abstract: Diffusion of ion-implanted dopant is controlled by incorporating electrically inactive impurity in a semiconductor layer by at least one crystal growth technique.

Abstract: A technique for forming a film of material (12) from a donor substrate (10). The technique has a step of forming a stressed region in a selected manner at a selected depth (20) underneath the surface. An energy source such as pressurized fluid is directed to a selected region of the donor substrate to initiate a controlled cleaving action of the substrate (10) at the selected depth (20), whereupon the cleaving action provides an expanding cleave front to free the donor material from a remaining portion of the donor substrate.

Abstract: A method of fabricating a junction-isolated semiconductor device is provided which includes the following steps. Within a first P-type buried region second N-type buried regions are formed. Over the first and second buried regions, an N-type epitaxial layer defining a surface of the device is grown. In the epitaxial layer, P-type isolation regions extending from the surface down to and in electric continuity with the first buried region and defining, with the first buried region, N-type wells incorporating the second buried regions is formed. And, P-type annular border regions in the epitaxial layer and to the side of the isolation regions are formed. The steps of forming isolation regions and annular border regions semiconducting regions being performed in a single step of selectively introducing doping ions.

Abstract: Method is provided for controlling the concentration of a dopant introduced into an epitaxial film during CVD or sublimation growth by controlling the energy of dopant atoms impinging on the film in a supersonic beam. Precursor materials may also be introduced by supersonic beam. Energy of the dopant atoms may be changed by changing flow conditions in the supersonic beam or changing carrier gases. Flow may be continuous or pulsed. Examples of silicon carbide doping are provided.

Abstract: An improved process is provided for amorphizing portions of a silicon substrate and a polysilicon gate electrode surface to be converted to metal silicide by subsequent reaction of the amorphized silicon with a metal layer applied over the silicon substrate and polysilicon gate electrode after the amorphizing step. The improvement comprises implanting the exposed surface of the silicon substrate and the surface of the polysilicon gate electrode with a beam of amorphizing ions at an angle of at least 15.degree. to a line perpendicular to the plane of the surface of the silicon substrate to thereby inhibit channeling of the implanted ions through the gate electrode to the underlying gate oxide and channel of the MOS structure. The implant angle of the beam of amorphizing ions is preferably at least 30.degree., but should not exceed 60.degree., with respect to a line perpendicular to the plane of the surface of the silicon substrate.

Abstract: The present invention proves a method and apparatus for manufacturing a polysilicon TFT without a defective activated area in a channel region below a gate. According to the instant invention, a dopant is implanted into a polysilicon thin film formed on an substrate with a gate having a tapered edge which is used as a mask to form a source and a drain. An energy beam then slantingly irradiates from the side of the edge of the gate to the surface of the substrate. Thus, the source and drain are activated and, at the same time, the energy beam streams into the polysilicon thin film below the edge of the gate to activate the channel region implanted the dopant.

Abstract: A silicon on insulator (SOI) process is disclosed which includes the steps of forming an etch stop layer in a starting wafer, forming an insulating layer on the etch stop layer, bonding this wafer to a handle wafer, thinning the start wafer down to the etch stop and then recovering a device layer from the etch stop layer by outgassing dopants from the etch stop layer.

Abstract: A fabrication method of a semiconductor device with the CMOS structure, which suppresses the sheet resistance of silicide layers of a refractory metal in an n-channel MOSFET at a satisfactorily low level while preventing the junction leakage current in a p-channel MOSFET from increasing. An n-type dopant is selectively ion-implanted into surface areas of a first pair of n-type source/drain regions and a surface area of a first gate electrode in an NMOS region at a first acceleration energy, thereby forming a first plurality of amorphous regions in the NMOS region. The n-type dopant is ion-implanted into surface areas of the second pair of p-type source/drain regions and a surface area of the second gate electrode in a PMOS region at a second acceleration energy lower than the first acceleration energy, thereby forming second plurality of amorphous regions in the PMOS region.

Abstract: Dopant activation in heavily boron doped p.sup.+ --Si is achieved by applying electric current of high density. The p.sup.+ --Si was implanted by a 40 KeV BF.sup.2+ at an ion intensity 5.multidot.10.sup.15 ions per cm.sup.2 and annealed at 900.degree. C. for 30 minutes to obtain a partial boron activation according to conventional processing steps. To obtain additional activation and higher conductivity, current was gradually applied according to the invention to a current density of approximately 5.times.10.sup.6 A/cm.sup.2 was realized. The resistance of the p.sup.+ --Si gradually increases and then decreases with a precipitous drop at a threshold current. The resistance was reduced by factor of 5 to 18 times and was irreversible if an activation current threshold was reached or exceeded. The high-current-density-dopant activation occurs at room temperature.

Abstract: A process for manufacturing a MOS-technology power device chip and package assembly, the MOS-technology power device chip comprises a semiconductor material layer in which a plurality of elementary functional units is integrated, each elementary functional unit contributing a respective fraction to an overall current and including a first doped region of a first conductivity type formed in the semiconductor layer, and a second doped region of a second conductivity type formed inside the first doped region; the package comprises a plurality of pins for the external electrical and mechanical connection; the plurality of elementary functional its is composed of sub-pluralities of elementary functional units, the second doped regions of all the elementary functional units of each sub-plurality being contacted by a same respective metal plate electrically insulated from the metal plates contacting the second doped regions of all the elementary functional units of the other sub-pluralities; each of the metal plates

Abstract: A semiconductor device includes a buffer layer of AlGaAs that contains oxygen with a concentration level in the approximate range of 8.times.10.sup.17 cm.sup.-3 to 6.times.10.sup.19 cm.sup.-3, and carbon with a concentration level in the approximate range of 2.times.10.sup.16 cm.sup.-3 to 2.times.10.sup.17 cm.sup.-3. A lattice constant of the AlGaAs buffer layer is larger than a lattice constant of the GaAs substrate so a lattice misfit of the AlGaAs layer with respect to the GaAs substrate is equal to or varies by no more than 2.times.10.sup.5 from a corresponding lattice misfit between an undoped AlGaAs crystal with respect to the GaAs substrate. Oxygen atoms occupy an interstitial site, creating a deep impurity level that suppresses side gate effect.

Abstract: Active acceptor concentrations of p-doped II-VI and III-V semiconductor compound layer provided by chemical vapor deposition are increased by photo-assisted annealing.