Abstract: Embodiments of an isolation structure and method of forming the same are disclosed, and may include a shallow trench isolation region formed on a semiconductor substrate, and an isolation layer that may include a first oxide layer, a plurality of silicon nitride layers and silicon oxide layers, and a second oxide layer. The first oxide layer may be formed in the shallow trench isolation region by a rapid thermal treatment, the plurality of silicon nitride layers and silicon oxide layers may be laminated on the first oxide layer, and the second oxide layer may be formed on the plurality of silicon nitride layers and silicon oxide layers by a high density plasma process to fill gaps.

Abstract: The present invention provides a method of forming a dual work function metal gate microelectronics device 200. In one aspect, the method includes forming nMOS and pMOS stacked gate structures 315a and 315b. The nMOS and pMOS stacked gate structures 315a and 315b each comprise a gate dielectric 205, a first metal layer, 305 located over the gate dielectric 205 and a sacrificial gate layer 310 located over the first metal layer 305. The method further includes removing the sacrificial gate layer 310 in at least one of the nMOS or pMOS stacked gate structures, thereby forming a gate opening 825 and modifying the first metal layer 305 within the gate opening 825 to form a gate electrode with a desired work function.

Abstract: The invention relates to a method for production of deep p regions in silicon, with the method having the following step: bombardment of an n substrate section, an n epitaxial section or an exposed weakly doped n region of a semiconductor component that is to be produced with high-energy particles, whose energy is chosen such that the previous n region is redoped to form a p region to the desired depth after a specific healing time at a specific healing temperature after the bombardment, and to its use for the production of semiconductor components, for example in order to carry out isolating diffusion.

Abstract: A method to achieve controlled conductivity in microfluidic devices, and a device formed thereby. The method comprises forming a microchannel or a well in an insulating material, and ion implanting at least one region of the insulating material at or adjacent the microchannel or well to increase conductivity of the region.

Abstract: A method is provided for forming a graded junction in a semiconductor material having a first conductivity type. Dopant having a second conductivity type opposite the first conductivity type is introduced into a selected region of the semiconductor material to define a primary dopant region therein. The perimeter of the primary dopant region defines a primary pn junction. While introducing dopant into the selected region of the semiconductor material, dopant is simultaneously introduced into the semiconductor material around the perimeter of the primary dopant region and spaced-apart from the primary pn junction. The dopant in the both the primary dopant region and in the dopant around the perimeter of the primary dopant region is then diffused to provide a graded dopant region.

Abstract: The invention relates to a method for real-time in-situ implantation and measurement incorporating a feedback loop to adjust the implantation dose of a substrate during the manufacturing and testing of semiconductor wafers. During processing, the substrate, such as a silicon wafer, is transported between a measuring device and an implantation device multiple times to ensure that where the beam from the implantation device hits the substrate, the doping concentration falls within the range of desired parameters.

Abstract: A method for stably activating pn-successive layers in a semiconductor element in a short time is disclosed. Pulsed beams, each of which has a pulse shape that is approximately rectangular, are projected from respective laser irradiation devices and successively combined into a pulsed beam equivalent to one pulse, with which the doped layer region is irradiated. By successively projecting the pulsed beams onto the doped layer region in this way, an effect is obtained which is the same as that of irradiating the doped layer region with a single pulsed beam having a long full-width at half maximum. A high activation ratio from a shallow region to a deep region of the doped layer region is enabled. This can stably activate the semiconductor element having the pn-successive layers as the doped layer region in a short time, making possible the manufacture of semiconductor elements having superior device characteristics.

Abstract: The present invention relates to a method for cladding a simple or complex surface, electrically conducting or semiconducting, by means of an organic film from at least one precursor of said organic film, characterized in that the cladding of the surface by the organic film is carried out by electro-initiated grafting of said, at least one, precursor of said surface by applying at least one potential sweep on this surface carried out in such a way that at any point of said surface the maximum potential of each potential sweep, in absolute value and relative to a reference electrode, is greater than or equal to the value of the potential (vbloc) from which the curves of a graph expressing the quantity of electro-grafted precursor on a surface identical to said surface in function of the number of potential sweeps are all superposed and independent of this vbloc potential.

Abstract: A method for implanting gate regions essentially without implanting regions of the semiconductor layer where source/drain regions will be later formed. The method includes the steps of (a) providing (i) a semiconductor layer, (ii) a gate dielectric layer on the semiconductor layer, (iii) a gate region on the gate dielectric layer, wherein the gate region is electrically insulated from the semiconductor layer by the gate dielectric layer; (b) forming a resist layer on the gate dielectric layer and the gate region; (c) removing a cap portion of the resist layer essentially directly above the gate region essentially without removing the remainder of the resist layer; and (d) implanting the gate region essentially without implanting the semiconductor layer.

Abstract: An apparatus and a method for interlocking power to ion implantation equipment. The apparatus may include a positive and a negative power supply which generates a positive voltage and a negative voltage respectively, a comparator which compares the positive voltage and the negative voltage, and a signal generating unit which generates an interlocking signal which interlocks the positive and negative power supplies when a sum of a first relative value of the positive voltage and a second relative value of the negative voltage does not equal zero. The apparatus may further include a switching unit which changes a mode of the positive and negative power supplies from a remote mode to a local mode when the sum of the relative values does not equal zero. The switching unit may be a relay switch. Power output lines may connect the positive and negative power sources to a lens assembly unit.

Abstract: A semiconductor device includes: an n+ type drain region; an n type drift region that connects with the n+ type drain region; a p type body region; a n+ type source region that connects with the p type body region; and a gate electrode that is provided, with being covered by a gate insulation film, in a gate trench that penetrates the p type body region. The semiconductor further includes: a p type silicon region that adjoins the n type drift region; and an n type silicon region provided in a region almost including a carrier passage that connects the n type drift region and the p type body region. Here, the p type silicon region and the p type body region directly connect with each other.

Abstract: To provide a semiconductor device able to be made uniform in diffusion depth of the impurity in a diffusion layer by a single diffusion and to give the desired threshold voltage and improved in yield and a method of producing the same. The device has a channel layer 16 formed on a substrate 12, a diffusion stop layer 17 formed on the top surface of the channel layer 16, a diffusion layer 18 formed on the top surface of the diffusion stop layer, and a doping region 25 formed adjoining the diffusion stop layer 17 at least at part of the diffusion layer 18 and having an impurity diffused in it, the diffusion stop layer 17 having a slower diffusion rate of the impurity than the diffusion rate of the diffusion layer 18 and stopping diffusion of the impurity from the diffusion layer 18.

Abstract: A method of forming semiconductor junctions in a semiconductor material of a workpiece includes ion implanting dopant impurities in selected regions of the semiconductor material, introducing an optical absorber material precursor gas into a chamber containing the workpiece, generating an RF oscillating toroidal plasma current in a reentrant path that includes a process zone overlying the workpiece by applying RF source power, so as to deposit a layer of an optical absorber material on the workpiece, and optically annealing the workpiece so as to activate dopant impurities in the semiconductor material.

Abstract: A method for void free filling with in-situ doped amorphous silicon of a deep trench structure is provided in which a first fill is carried out in at a temperature, pressure and dopant to silane ratio such that film deposition occurs from the bottom of the trench upwards. By way of this first fill, step coverages well in excess 100% are achieved. In the second fill step, deposition is carried out under changed conditions so as to reduce the impact of dopant on deposition rate, whereby trench fill is completed at a deposition rate which exceeds the deposition rate of the first fill. In an application of this method to the formation of deep trench capacitor structures, the intermediate steps further including the capping of the void free filled trench with a thick layer of amorphous silicon, planarization of the wafer thereafter, followed by a thermal anneal to re-distribute the dopant within the filled trench. Thereafter, additional steps can be performed to complete the formation of the capacitor structure.

Abstract: There is provided a new method of obtaining the dopant activation rate of a device accurately and simply in a different way from a method of obtaining a carrier density with use of a Hall measurement or CV measurement, and also provided a production method of a device performed with a proper threshold voltage control, that is, a dose amount control, according to the obtained activation rate. The inventor devised a method in which the activated dopant density (first dopant density) in a semiconductor film is obtained from the threshold voltage and the flat band voltage of a device, then the dopant activation rate is obtained from the ratio of the obtained activated dopant density to the added dopant density (second dopant density) obtained by SIMS analysis. The invention allows easily obtaining the dopant activation rate in the channel region and the impurity region of the device.

Abstract: The present invention relates to the production of thin film epilayers of III–V and other compounds with acceptor doping wherein the acceptor thermally stabilizes the epilayer, stabilize the naturally incorporated native defect population and therewith maintain the epilayer's beneficial properties upon annealing among other advantageous effects. In particular, balanced doping in which the acceptor concentration is similar to (but does not exceed) the antisite defects in the as-grown material is shown to be particularly advantageous in providing thermal stability, high resistivity and ultrashort trapping times. In particular, MBE growth of LT-GaAs epilayers with balanced Be doping is described in detail. The growth conditions greatly enhance the materials reproducibility (that is, the yield in processed devices). Such growth techniques can be transferred to other III–V materials if the growth conditions are accurately reproduced.

Abstract: Methods of manufacturing MOS transistors which are capable of suppressing a short channel effect are disclosed. The short channel effect is suppressed by forming source/drain regions of a shallow junction and sufficiently doping a gate. An illustrated method includes: forming a gate insulating layer and a gate on a semiconductor substrate of a first conductivity type; forming lightly doped drain regions of a second conductivity type within the substrate at opposite sides of the gate; forming spacers on side walls of the gate; forming an insulating buffer layer; exposing a top surface of the gate by performing a planarization process on the insulating buffer layer; doping the gate by implanting impurity ions of the second conductivity type into the top surface of the gate; removing the insulating buffer layer; and forming source/drain regions of the second conductivity type within the substrate at opposite sides of the spacers.

Abstract: In a semiconductor device including active areas where transistors are formed and a field area for isolating the active areas from each other, the field area has a plurality of dummy areas where dummy gates are formed.

Abstract: A method for implanting ions in a surface layer of a workpiece includes placing the workpiece on a workpiece support in a chamber with the surface layer being in facing relationship with a ceiling of the chamber, thereby defining a processing zone between the workpiece and the ceiling, and introducing into the chamber a process gas including the species to be implanted in the surface layer of the workpiece. The method includes generating from the process gas a plasma by capacitively coupling RF source power across the workpiece support and the ceiling or the sidewall from an RF source power generator. The method further includes applying an RF bias from an RF bias generator to the workpiece support.

Abstract: The invention provides a substrate for use in an ion source of a mass spectrometer system. The substrate may be employed independently or in conjunction with an ion source or a mass spectrometry system. A substrate is provided having at least one pattern recognition site and a carbon nanotube adjacent to the pattern recognition site. Methods of making and ionizing samples using the pattern recognition site and carbon nanotube surface are also disclosed.

Abstract: A semiconductor substrate is provided, and at least one first mask is formed above the semiconductor substrate. The first mask has a plurality of thicknesses and blocks at least one semi-insulating region. A second mask is thereafter formed on a surface of the semiconductor substrate. The second mask covers the semi-insulating region. The semi-insulating region is implanted with a high energy beam of particles by utilizing the second mask and the first mask as particle hindering masks. Finally, the second mask is removed.

Abstract: The invention provides a method for manufacturing a semiconductor device with which an impurity introduction region and a positioning mark region can be formed aligned, based on a common insulating film pattern.

Abstract: A surface acoustic wave device includes a piezoelectric substrate, a first interdigital transducer and a second interdigital transducer formed on the substrate so that the first and second interdigital transducers are opposed to each other. The substrate includes a doping region that is doped with a substance in at least one form selected from the group consisting of atoms, molecules and clusters in a surface between the first and second interdigital transducers.

Abstract: Methods for fabricating a contact of a semiconductor device are provided by patterning an interlayer dielectric of the semiconductor device to form a contact hole that exposes a silicon-based region of a first impurity type. The exposed silicon-based region is doped with a gas containing an element of the first impurity type and a contact plug is formed in the contact hole. Contact structure for a semiconductor device are also provided that include an interlayer dielectric of the semiconductor device having a contact hole formed therein that exposes a silicon-based region of a first impurity type. A delta-doped region of the first impurity type is provided in the exposed silicon-based region. A contact plug is provided in the contact hole and on the delta-doped region.

Abstract: Semiconductor processing methods of forming integrated circuitry, and in particular, dynamic random access memory (DRAM) circuitry are described. In one embodiment, a single masking step is utilized to form mask openings over a substrate, and both impurities are provided and material of the substrate is etched through the openings. In one implementation, openings are contemporaneously formed in a photo masking layer over substrate areas where impurities are to be provided, and other areas where etching is to take place. In separate steps, the substrate is doped with impurities, and material of the substrate is etched through the mask openings. In another implementation, two conductive lines are formed over a substrate and a masking layer is formed over the conductive lines. Openings are formed in the masking layer in the same step, with one of the openings being received over one conductive line, and another of the openings being received over the other conductive line.

Abstract: A particle, includes a semiconductor nanocrystal. The nanocrystal is doped.

Abstract: Disclosed is a method of manufacturing a semiconductor device. In ion implantation process for controlling the threshold voltage of the transistor or the semiconductor device such as a flash memory cell, the dose of the impurity capable of securing the uniformity is implanted by minimum. The retained dose of the impurity is controlled by out gassing the implanted impurity by means of a cleaning process. Therefore, a uniform distribution characteristic of the implanted impurity could be obtained. A transistor or a flash memory cell of a low operating voltage could be manufactured.

Abstract: A method for modeling a substrate, which includes obtaining vertically discretized doping profiles in the substrate to facilitate modeling. The method includes employing substrate region names and substrate cross-section names as access keys to permit accessing of the vertically discretized doping profiles. The use of the combination of region names and substrate cross-section names as unique access keys simplifies access to doping profile information for modeling purposes and yields valuable information pertaining to the presence of p-type to n-type material transitions. The information pertaining to transitions may be employed to improve substrate modeling accuracy through the inclusion of junction capacitances with the modeling process.

Abstract: The invention relates to the use of an organic mesomeric compound as organic dopant for doping an organic semiconducting matrix material for varying the electrical properties thereof. In order to be able to handle organic semiconductors more easily in the production process and to be able to produce electronic components with doped organic semiconductors more reproducibly, it is proposed that as mesomeric compound a quinone or quinone derivative or a 1,3,2-dioxaborine or a 1,3,2-dioxaborine derivative may be used, which under like evaporation conditions has a lower volatility than tetrafluorotetracyanoquinonedimethane (F4TCNQ).

Abstract: A strained silicon layer is grown on a layer of silicon germanium and a second layer of silicon germanium is grown on the layer of strained silicon in a single continuous in situ deposition process. Both layers of silicon germanium may be grown in situ with the strained silicon. This construction effectively provides dual substrates at both sides of the strained silicon layer to support the tensile strain of the strained silicon layer and to resist the formation of misfit dislocations that may be induced by temperature changes during processing. Consequently the critical thickness of strained silicon that can be grown on substrates having a given germanium content is effectively doubled. The silicon germanium layer overlying the strained silicon layer may be maintained during MOSFET processing to resist creation of misfit dislocations in the strained silicon layer up to the time of formation of gate insulating material.

Abstract: In one illustrative embodiment, the method comprises forming a gate electrode above an SOI substrate comprised of a bulk substrate, a buried insulation layer and an active layer, the gate electrode having a protective layer formed thereabove, and forming a plurality of dielectric regions in the bulk substrate after the gate electrode is formed, the dielectric regions being self-aligned with respect to the gate electrode, the dielectric regions having a dielectric constant that is less than a dielectric constant of the bulk substrate.

Abstract: The invention relates to the fabrication of a resistance variable material cell or programmable metallization cell. The processes described herein can form a metal-rich metal chalcogenide, such as, for example, silver-rich silver selenide. Advantageously, the processes can form the metal-rich metal chalcogenide without the use of photodoping techniques and without direct deposition of the metal. For example, the process can remove selenium from silver selenide. One embodiment of the process implants oxygen to silver selenide to form selenium oxide. The selenium oxide is then removed by annealing, which results in silver-rich silver selenide. Advantageously, the processes can dope silver into a variety of materials, including non-transparent materials, with relatively high uniformity and with relatively precise control.

Abstract: The invention provides a method of making silicon-on-insulator SOI substrates with nitride buried insulator layer by implantation of molecular deuterated ammonia ions ND3+, instead of implanting nitrogen ions (N+, or N2+) as is done in prior art nitride SOI processes. The resultant structure, after annealing, has a buried insulator with a defect density which is substantially lower than in prior art nitride SOI. The deuterated nitride SOI substrates allow much better heat dissipation than SOI with a silicon dioxide buried insulator. These substrates can be used for manufacturing of high speed and high power dissipation monolithic integrated circuits.

Abstract: Disclosed herein is a method for manufacturing a zinc oxide semiconductor. The method comprises the steps of forming a zinc oxide thin film including a group V element as a dopant on a substrate by using a zinc oxide compound containing a group V element or an oxide thereof, charging the substrate having the zinc oxide thin film formed thereon into a chamber for thermal annealing, and thermal annealing the substrate in the chamber to activate the dopant, thereby changing the zinc oxide thin film exhibiting n-type electrical properties or insulator properties to a zinc oxide thin film exhibiting p-type electrical properties.

Abstract: A buried bit line and a fabrication method thereof, wherein the device includes a substrate, a shallow doped region disposed in the substrate, a deep doped region disposed in the substrate below a part of the shallow doped region, wherein the shallow doped region and the deep dope region together form a bit line of the memory device.

Abstract: A thermal process for activating respective impurities in a polysilicon film to be a gate electrode and a resistance element is performed with the polysilicon film to be the gate electrode and the resistance element being coated with an oxide film, after the respective impurities are implanted into the polysilicon film to be the gate electrode and the resistance element. Here, concentrations of the respective impurities in the polysilicon film to be the gate electrode and the resistance element are adjusted by controlling the thickness of the oxide film. The degree of impurity activation is thereby adjusted.

Abstract: Formation of an interconnect circuit feature having a metal and an electropositive dopant. The interconnect feature may contain an accumulation of the electropositive dopant at interface boundaries of the interconnect feature to reduce electromigration of the metal during operation. In a method the interconnect feature may be heated to drive a portion of the electropositive dopant to the interfaces.

Abstract: The present invention relates generally to compositions, kits and methods of providing improved semiconductor surfaces free of dangling bonds and free of strained bonds. One method provides for preventing interfacial reactions between a semiconductor surface and metal or dielectric comprising the steps of preparing a passivated semiconductor surface using a valence-mending agent and depositing a layer of metal or dielectric on the valence-mended semiconductor surface. As further described, a semiconductor surface free of interfacial reactions between the surface and a second molecular species may include a semiconductor surface with one atomic layer of valence-mending atoms, wherein valence mending occurs after introducing the semiconductor surface to a passivating agent. The present invention also includes a kit for preventing interfacial reactions from occurring on a semiconductor surface comprising a passivating agent and an instructional manual.

Abstract: A method of creating two or more semiconductor elements of different characteristics in one and the same semiconductor substrate. Two antimony-diffused regions are formed in a p-type semiconductor region (of a semiconductor substrate for providing embedded layers for two field-effect transistors of unlike characteristics. Then the substrate is overlaid with a mask bearing two different patterns of windows. Then phosphor is introduced into the substrate through the mask windows to create phosphor-diffused regions in overlying relationship to the antimony-diffused regions. The two window patterns of the mask are such that the two phosphor-diffused regions differ in mean phosphor concentration. The embedded layers for the two FETs are obtained as an n-type epitaxial layer is subsequently formed on the p-type semiconductor region in which have been created the antimony-diffused regions and phosphor-diffused regions.

Abstract: An impurity diffusion layer that structures a source region (15) and a drain electrode (16) of a pMOS 11 is formed extremely shallow, with a depth of approximately 50 nm. The extremely shallow impurity diffusion layer is formed by carrying out annealing process using RLSA plasma, after ion implantation processing at a low energy. In the annealing process, only silicon atoms near the surface of a silicon substrate (12) are selectively excited by the RLSA plasma, and impurity diffusion towards depth direction is suppressed.

Abstract: A method to create a low resistivity P+in-situ doped polysilicon film at low temperature from SiH4 and BCl3 with no anneal required. At conventional dopant concentrations using these source gases, as deposition temperature decreases below about 550 degrees C., deposition rate decreases and sheet resistance increases, making production of a high-quality film impossible. By flowing very high amounts of BCl3, however, such that the concentration of boron atoms in the resultant film is about 7×1020 or higher, the deposition rate and sheet resistance are improved, and a high-quality film is produced.

Abstract: A method of fabricating an integrated circuit in and on a semiconductor substrate with deep implantations by applying a scattered ion capturing layer in the resist mask opening to capture any implanted ions scattered in the resist and deflected out of the resist into the mask opening to prevent these ions from reaching the semiconductor substrate and affecting the concentration of ions at the edge of the mask and thus the performance of the integrated circuit.

Abstract: A method is provided for printing electronic and opto-electronic circuits. The method comprises: (a) providing a substrate; (b) providing a film-forming precursor species; (c) forming a substantially uniform and continuous film of the film-forming precursor species on at least one side of the substrate, the film having a first electrical conductivity; and (d) altering portions of the film with at least one conductivity-altering species to form regions having a second electrical conductivity that is different than the first electrical conductivity, the regions thereby providing circuit elements. The method employs very simple and continuous processes, which make the time to produce a batch of circuits very short and leads to very inexpensive products, such as electronic memories (write once or rewriteable), electronically addressable displays, and generally any circuit for which organic electronics or opto-electronics are acceptable.

Abstract: A method of manufacturing a monolithic ink-jet printhead includes preparing a silicon substrate, forming an ink passage comprising a manifold supplying ink, an ink chamber filled with ink supplied from the manifold, an ink channel connecting the ink chamber to the manifold, and a nozzle through which the ink is ejected from the ink chamber, on the silicon substrate, and reprocessing a wall of the ink passage by passing XeF2 gas through the ink passage and dry etching the wall of the ink passage. In the reprocessing of the wall of the ink passage using XeF2 gas, the wall of the ink passage is smoothed, and a size of the ink passage can be more precisely adjusted to a design dimension, thereby improving a printing performance of the ink-jet printhead.

Abstract: A method of ion implantation is provided. The method comprising: providing a substrate; forming a masking image having a sidewall on the substrate; forming a blocking layer on the substrate and on the masking image; and performing a retrograde ion implant through the blocking layer into the substrate, wherein the blocking layer substantially blocks ions scattered at the sidewall of the masking layer.

Abstract: A method used during the formation of a semiconductor device reduces ion channeling during implantation of the wafer. The method comprises providing a semiconductor wafer and an unetched transistor gate stack assembly over the wafer. The unetched transistor gate stack assembly comprises a gate oxide layer, a control gate layer, a metal layer, and a dielectric capping layer. A patterned photoresist layer is formed over the unetched transistor gate stack assembly, then each of the capping layer, the metal layer, the control gate layer, and the gate oxide layer is etched to form a plurality of laterally-spaced transistor gate stacks. A screening layer is formed overlying the semiconductor wafer between the transistor gate stacks. A dopant is implanted into the semiconductor wafer through the screening layer, then the screening layer is removed.

Abstract: A method of testing ion implantation equipment verifies the level of ion implantation energy. The method includes implanting first conductive ions in an implantation region in a semiconductor substrate, implanting second conductive ions, having valence different from that of the first conductive ions, in the implantation region so as to produce a second well, and subsequently measuring a sheet resistance of the semiconductor substrate. The implanting of the second conductive ions may be carried out while varying the level of the ion implantation energy. By forming a twin well in this way, and then measuring the sheet resistance, the value of the sheet resistance can be precisely correlated to the amount of energy used to form a well.

Abstract: A semiconductor substrate and an impurity solid that comprises of impurity to be introduced to a diode formation region are held in a vacuum chamber. Inert or reactive gas is introduced into the vacuum chamber to generate plasma composed of the inert or reactive gas. A first voltage allowing the impurity solid to serve as a cathode for the plasma is applied to the said impurity solid and the said impurity solid is sputtered by ions in the plasma, thereby mixing the impurity within the said impurity solid into the plasma. A second voltage allowing a semiconductor substrate to serve as a cathode for the plasma is applied to the said semiconductor substrate, thereby directly introducing the impurity within the plasma to the surface portion of the diode formation region of the said semiconductor substrate, generating a impurity layer.

Abstract: We provide a method of doping an Si or SiGe film with carbon or boron. By reducing the silicon precursor pressure, heavily-doped films may be obtained. A single dopant source may be used. The doped Si and SiGe films are of suitable quality for use in a transistor such as an HBT.

Abstract: The invention relates to the fabrication of a resistance variable material cell or programmable metallization cell. The processes described herein can form a metal-rich metal chalcogenide, such as, for example, silver-rich silver selenide. Advantageously, the processes can form the metal-rich metal chalcogenide without the use of photodoping techniques and without direct deposition of the metal. For example, the process can remove selenium from silver selenide. One embodiment of the process implants oxygen to silver selenide to form selenium oxide. The selenium oxide is then removed by annealing, which results in silver-rich silver selenide. Advantageously, the processes can dope silver into a variety of materials, including non-transparent materials, with relatively high uniformity and with relatively precise control.