Abstract: The invention relates to the fabrication of a resistance variable material cell or programmable metallization cell. The processes described herein can form a metal-rich metal chalcogenide, such as, for example, silver-rich silver selenide. Advantageously, the processes can form the metal-rich metal chalcogenide without the use of photodoping techniques and without direct deposition of the metal. For example, the process can remove selenium from silver selenide. One embodiment of the process implants oxygen to silver selenide to form selenium oxide. The selenium oxide is then removed by annealing, which results in silver-rich silver selenide. Advantageously, the processes can dope silver into a variety of materials, including non-transparent materials, with relatively high uniformity and with relatively precise control.

Abstract: A diffusion furnace includes a support member, a process chamber, a sealing member for sealing from the process chamber the outside, and a cooling system for cooling the sealing member. The process chamber is installed on the support member, and the sealing member is inserted between the support member and the chamber. The cooling system has a first fluid passage and a second fluid passage. The first and second fluid passages are formed in the support member. A first fluid flows in the first fluid passage to cool the sealing member, and a second fluid flows in the second fluid passage to cool the sealing member when the supply of the first fluid is interrupted. With the present invention, cooling water and a coolant can be prevented from being mixed together. Therefore, it is possible to prevent the contamination of an apparatus and the waste of expensive cooling water.

Abstract: A plasma is produced in a treatment space by diffusing a plasma gas at atmospheric pressure and subjecting it to an electric field created by two metallic electrodes separated by a dielectric material, a vapor precursor is mixed with the plasma, and a substrate material is coated by vapor deposition of the vaporized substance at atmospheric pressure in the plasma field. The use of vaporized silicon-based materials, fluorine-based materials, chlorine-based materials, and organo-metallic complex materials enables the manufacture of coated substrates with improved properties with regard to moisture-barrier, oxygen-barrier, hardness, scratch- and abrasion-resistance, chemical-resistance, low-friction, hydrophobic and/or oleophobic, hydrophilic, biocide and/or antibacterial, and electrostatic-dissipative/conductive characteristics.

Abstract: The present invention describes a method of forming a thin film on a substrate arranged in a deposition system comprising the step of introducing a pre-determined amount of an impurity in a confined volume in the deposition system. One or more gases are introduced into the deposition system for forming the thin film. The impurity is removed from the confined volume in a gas phase during formation of the thin film. The impurity in the gas phase is incorporated into the thin film.

Abstract: The present invention describes a method of forming a thin film on a substrate arranged in a deposition system comprising the step of introducing a pre-determined amount of an impurity in a confined volume in the deposition system. One or more gases are introduced into the deposition system for forming the thin film. The impurity is removed from the confined volume in a gas phase during formation of the thin film. The impurity in the gas phase is incorporated into the thin film.

Abstract: A scheme for filling plugs through chemical mechanical polishing comprises depositing a malleable conductive layer over a dielectric layer having openings formed therein. The malleable conductive layer is deposited such that a liner is formed within the openings, however the openings are not completely filled. A chemical mechanical polishing process using an alumina based slurry at a neutral or slightly basic pH and no oxidizer is used to smear the malleable conductive layer sufficiently to fill the remainder of the openings in the dielectric layer forming filled or substantially filled plugs.

Abstract: A method for forming a p-channel metal-oxide semiconductor(PMOS) device is suitable for reducing the width of change of a threshold voltage by preventing a deterioration of a uniformity of dopants due to out diffusion and segregation of the dopants implanted into channel regions. The method includes the steps of: forming a channel region below a surface of a semiconductor substrate; activating dopants implanted into the channel region through a first annealing process performed twice by rising temperature velocities different to each other; forming a gate oxidation layer and a gate electrode on the semiconductor substrate subsequently; forming a source/drain regions at both sides of the gate electrode in the semiconductor substrate; and activating dopants implanted into the source/drain regions through a second annealing process performed at the same conditions of the first annealing process.

Abstract: The method for fabricating a semiconductor device comprises the steps of: forming a dummy electrode 22n and a dummy electrode 22p; forming a metal film 32 on the dummy electrode 22p; conducting a thermal treatment at a first temperature to substitute the dummy electrode 22n with an electrode 34a of a material containing the constituent material of the metal film 32; forming a metal film 36 on the dummy electrode 22n; and conducting a thermal treatment at a second temperature, which is lower than the first temperature and at which an interdiffusion of constituent materials between the electrode 34a and the metal film 36 does not take place, to substitute the second dummy electrode with an electrode 34b of a material containing the constituent material of the metal film 36.

Abstract: In the preferred embodiment of this invention a method is described to convert patterned SOI regions into patterned SGOI (silicon-germanium on oxide) by the SiGe/SOI thermal mixing process to further enhance performance of the logic circuit in an embedded DRAM. The SGOI region acts as a template for subsequent Si growth such that the Si is strained, and electron and holes in the Si have higher mobility.

Abstract: Disclosed is a method of manufacturing a semiconductor device. In ion implantation process for controlling the threshold voltage of the transistor or the semiconductor device such as a flash memory cell, the dose of the impurity capable of securing the uniformity is implanted by minimum. The retained dose of the impurity is controlled by out gassing the implanted impurity by means of a cleaning process. Therefore, a uniform distribution characteristic of the implanted impurity could be obtained. A transistor or a flash memory cell of a low operating voltage could be manufactured.

Abstract: As technology in the semiconductor industry advances, semiconductor devices decrease in size to become faster and less expensive per function. Smaller semiconductor devices, particularly MOSFETs, are increasingly sensitive to Electrostatic Discharge (ESD). ESD can either destroy or permanently damage a semiconductor device. Embodiments of the present invention assist in preventing ESD damage to semiconductor devices. An embodiment of the present invention utilizes a diode connected to the substrate terminal of a MOSFET. Under normal operation up to the maximum operating voltage, the diode and MOS devices are open and do not conduct. The diode triggers when an ESD pulse causes the reverse breakdown voltage of the diode to be exceeded. The resultant current switches a connected MOS device, operating in bipolar mode, to dissipate the damaging ESD pulse. The ESD pulse is shunted to ground, thereby avoiding damage to the rest of the device.

Abstract: Semiconductor processing methods of forming integrated circuitry, and in particular, dynamic random access memory (DRAM) circuitry are described. In one embodiment, a single masking step is utilized to form mask openings over a substrate, and both impurities are provided and material of the substrate is etched through the openings. In one implementation, openings are contemporaneously formed in a photo masking layer over substrate areas where impurities are to be provided, and other areas where etching is to take place. In separate steps, the substrate is doped with impurities, and material of the substrate is etched through the mask openings. In another implementation, two conductive lines are formed over a substrate and a masking layer is formed over the conductive lines. Openings are formed in the masking layer in the same step, with one of the openings being received over one conductive line, and another of the openings being received over the other conductive line.

Abstract: There is provided a semiconductor device in which improvement of drive capacity and miniaturization are made. A P-type transistor is composed of a surface channel type transistor so that a channel length is easily reduced. Thus, improvement of drive capacity and miniaturization are promoted. Further, since a gate insulating film is nitrided, reliability of the gate insulating film is improved and passing of boron contained in a p-type polycrystalline silicon gate electrode toward a channel region can be prevented. A step of forming the gate insulating film, a step of nitriding the gate insulating film, a step of performing thermal treatment using an inert gas, a step of forming a gate electrode on the gate insulating film, and a step of introducing a p-type impurity into the gate electrode are performed. Thus, a surface channel P-type transistor and a buried channel N-type transistor are constructed.

Abstract: A Thin Film Transistor (TFT) manufacture method, comprising manufacture of a gate, a gate isolation layer, a channel layer, and a source/drain. Wherein, the manufacture of the channel layer comprises: forming a first a-Si layer by using a low deposition rate (LDR) (Chemical Vapor Deposition, CVD); forming a second a-Si layer by using a high deposition rate (HDR); and forming an N+Mixed a-Si layer. When the first a-Si layer is formed in the present invention, the flux ratio of H2/SiH4 is adjusted to a range from 0.40 to 1.00 to increase the number of defects in the first a-Si layer. When the TFT is irradiated by the light, the photo leakage current generated in the channel layer is trapped in the defects in the first a-Si layer. Therefore, the TFT photo leakage current can be significantly reduced.

Abstract: A semiconductor device isolation structure and a fabricating method therefor are disclosed. The isolation structure includes a trench which is formed on an isolating region to define an active region. First, second, and third insulating layers are deposited in the trench. The second insulating layer has an etch selection ratio different from those of the first and third insulating layers. The edge portions of the third insulating layer which contact the side walls of the trench characteristically do not show any collapse. Therefore, when supplying a subthreshold voltage, a hump phenomenon does not occur. As a result, leakage current is kept from increasing, and the device refresh characteristic can be kept from deteriorating. Further, the third insulating layer covers the top edge portions of the trench. Therefore, the gate insulating layer (which is formed later) has a sufficient thickness. Therefore, yield voltage characteristics can be kept from deteriorating.

Abstract: In a semiconductor device manufacturing method, an ion current density distribution is measured in a plasma processing apparatus. It is then ascertained whether or not the measured distribution is in compliance with an ion current density distribution that becomes a criterion.

Abstract: A top surface of a wafer is provided with an n-type source region, an n-type drain region, and an n-type semiconductor region. Dry etching using a plasma is performed with respect to an interlayer insulating film deposited on the wafer to form openings reaching the respective regions, followed by light etching for removing a damaged layer. In this case, exciting light is supplied intermittently to the n-type semiconductor region. The progression of the removal of the damaged layer and the stage of development of a newly damaged layer are sensed by monitoring the change rate of the intensity of reflected probe light in the presence and absence of the exciting light, resulting in the formation of a semiconductor device having low and equal contact resistance. In-line control using optical evaluation enables the implementation of semiconductor devices with excellent and consistent properties.

Abstract: Structure and method for filling an opening in a semiconductor structure that is less susceptible to the formation of voids. A first layer of a first material is formed over the layer in which the opening is to be formed, and a faceted opening is formed in the first layer. The opening in the underlying layer is subsequently formed, and the material that is to fill the opening is deposited over the faceted opening and into the opening of the underlying layer.

Abstract: One aspect of the invention relates to a method of forming P-N junctions within a semiconductor substrate. The method involves providing a temporary impurity species, such as fluorine, within the semiconductor crystal matrix prior to solid source in-diffusion of the primary dopant, such as boron. The impurity atom is a faster diffusing species relative to silicon atoms. During in-diffusion, the temporary impurity species acts to reduce the depth to which the primary dopant diffuses and thereby facilitates the formation of very shallow junctions.

Abstract: Methods and apparatus for modeling noise present in an integrated circuit substrate are disclosed. A position on a surface of the integrated circuit substrate is obtained. A combination of layers associated with the position and defining a vertical column beneath the position is ascertained. A doping profile associated with the combination of layers is obtained. The doping profile includes a plurality of portions, each of which is associated with a different range of substrate depth. Noise in the integrated circuit substrate is then modeled using the obtained doping profile.

Abstract: The invention provides a method of manufacturing a thin-film transistor whose semiconductor surface is protected. The surface of semiconductor formed on a substrate is exposed to ozone-containing water to form a surface-oxidized layer on the surface. A mask formed for etching or ion implantation is removed with the layer formed at least on an exposed portion of the surface.

Abstract: An N−-type silicon substrate (1) has a bottom surface and an upper surface which are opposed to each other. In the bottom surface of the N−-type silicon substrate (1), a P-type impurity diffusion layer (3) of high concentration is entirely formed by diffusing a P-type impurity. In the upper surface of the N−-type silicon substrate (1), a P-type isolation region (2) is partially formed by diffusing a P-type impurity. The P-type isolation region (2) has a bottom surface reaching an upper surface of the P-type impurity diffusion layer (3). As viewed from the upper surface side of the N−-type silicon substrate (1), the P-type isolation region (2) is formed, surrounding an N− region (1a) which is part of the N−-type silicon substrate (1). The N− region (1a) surrounded by the P-type isolation region (2) is defined as an element formation region of the N−-type silicon substrate (1).

Abstract: The present invention discloses a method for manufacturing an array structure in integrated circuits (IC). The method for manufacturing an array structure in integrated circuits of the present invention is performed by using two masks. First, a first mask having array pattern of holes is used to perform a first exposing step with a partial dose, and a second mask having code patterns is used to perform a second exposing step with a compensating dose for the first exposing step, so that a photoresist covering the regions of the holes desired to be opened obtains a sufficient exposure dose and the holes desired are formed by developing. Therefore, a preferred resolution and a preferred depth of focus (DOF) for exposure are obtained, thereby reducing optical proximity effect (OPE), and it is quite easily to manufacture the masks used in the present invention.

Abstract: An improved method for forming a self-aligned twin well structure for use in a CMOS semiconductor device including providing a substrate for forming a twin well structure therein; forming an implant masking layer over the substrate to include a process surface said masking layer patterned to expose a first portion of the process surface for implanting ions; subjecting the first portion of the process surface to a first ion implantation process to form a first doped region included in the substrate; forming an implant blocking layer including a material that is selectively etchable to the implant masking layer over the first portion of the process surface; removing the implant masking layer to expose a second portion of the process surface; and, subjecting the second portion of the process surface to a second ion implantation process to form a second doped region disposed adjacent to the first doped region.

Abstract: The invention relates to the fabrication of a resistance variable material cell or programmable metallization cell. The processes described herein can form a metal-rich metal chalcogenide, such as, for example, silver-rich silver selenide. Advantageously, the processes can form the metal-rich metal chalcogenide without the use of photodoping techniques and without direct deposition of the metal. For example, the process can remove selenium from silver selenide. One embodiment of the process implants oxygen to silver selenide to form selenium oxide. The selenium oxide is then removed by annealing, which results in silver-rich silver selenide. Advantageously, the processes can dope silver into a variety of materials, including non-transparent materials, with relatively high uniformity and with relatively precise control.

Abstract: A method and apparatus of preventing lateral oxidation through gate dielectrics that are highly permeable to oxygen diffusion, such as high-k gate dielectrics. According to one embodiment of the invention, a gate structure is formed on a substrate, the gate structure having an oxygen-permeable gate dielectric. An oxygen diffusion barrier is then formed on the sidewalls of the gate structure to prevent oxygen from diffusing laterally into the oxygen-permeable gate dielectric, thus preventing oxidation to the substrate underneath the gate dielectric or to the electrically conductive gate electrode overlying the gate dielectric.

Abstract: A technique for forming nanostructures including a definition of a charge pattern on a substrate and introduction of charged molecular scale sized building blocks (MSSBBs) to a region proximate the charge pattern so that the MSSBBs adhere to the charge pattern to form the feature.

Abstract: A method and apparatus of preventing lateral oxidation through gate dielectrics that are highly permeable to oxygen diffusion, such as high-k gate dielectrics. According to one embodiment of the invention, a gate structure is formed on a substrate, the gate structure having an oxygen-permeable gate dielectric. An oxygen diffusion barrier is then formed on the sidewalls of the gate structure to prevent oxygen from diffusing laterally into the oxygen-permeable gate dielectric, thus preventing oxidation to the substrate underneath the gate dielectric or to the electrically conductive gate electrode overlying the gate dielectric.

Abstract: In an ion implantation method using an ion implantation equipment having an extraction electrode and a post accelerator, ion is uniformly implanted into a shallow region from the surface of a sample by setting an applied volt. of the post accelerator higher than an applied volt. of the extraction electrode.

Abstract: A semi-insulating InP substrate in which a Ru-doped semi-insulating semiconductor layer is formed on the surface is provided, wherein the Ru-doped semi-insulating semiconductor layer has a complete semi-insulating property. The semiconductor optical device is fabricated by forming the Ru-doped semi-insulating semiconductor layer on a Fe-doped semi-insulating InP substrate, and forming a semiconductor crystal layer to which a p-type impurity is doped.

Abstract: The invention, called hypercontacting, achieves a very high level of activated doping at an exposed surface region of a compound semiconductor. This enables production of low resistance ohmic contacts by creating a heavily doped region near the contact. Such region lowers the contact's tunneling barrier by decreasing the extent of the depletion region at the contact, thereby reducing resistance.

Abstract: Various methods are provided of forming capacitor electrodes for integrated circuit memory cells in which out-diffusion of dopant from doped silicon layers is controlled by deposition of barrier layers, such as layers of undoped silicon and/or oxide. In one aspect, a method of forming hemispherical grain silicon on a substrate is provided that includes forming a first doped silicon layer on the substrate and a first barrier layer on the doped silicon layer. A hemispherical grain polysilicon source layer is formed on the first barrier layer and a hemispherical grain silicon layer on the hemispherical grain polysilicon source layer. By controlling out-diffusion of dopant, HSG grain size, density and uniformity, as well as DRAM memory cell capacitance, may be enhanced, while at the same time maintaining reactor throughput.

Abstract: The invention consists of an ESD protection discharging NMOS with a special drain dopant region that enables a lower voltage trigger point for Vcc to Vss ESD power protection. To enable this ESD protection, the NMOS source connected to a first voltage bus line, or Vcc, and the drain is connected to a second voltage bus line, or ground. The NMOS device gate is connected to ground through a difflused resistor assuring the device remains in an off state during normal operation. The unique invention special dopant region is located under and around the NMOS drain which lowers the drain to substrate breakdown voltage enabling the ESD protection current discharge to start at a lower voltage than otherwise. This feature reduces voltage stress on the gates of active devices being protected, and enables higher ESD current discharges at the same power level as for devices without the special drain dopant region.

Abstract: Various methods of determining ion implant dosage are disclosed. In one aspect, a method of processing a semiconductor workpiece that has a device region and an inactive region is provided. A first mask is formed on a first portion of the inactive region. A first implant of ions is performed on the device region and the first mask. A secondary ion mass spectrometry analysis of the first portion of the first mask is performed to determine a composition thereof relative to a standard composition. A dose for the first implant is determined based upon the secondary ion mass spectrometry analysis of the first portion of the first mask. The first implant dose is compared with a prescribed dose for the first implant to determine if a second implant is necessary to achieve the prescribed dose, and if so, an appropriate make-up dose for the second implant.

Abstract: A method of fabricating an integrated circuit including a monocrystalline silicon substrate, a layer of polycrystalline silicon on the top surface of the substrate and doped with at least two dopants with different rates of diffusion, in which method annealing is performed at a temperature and for a time such that a first dopant diffuses into a first zone and a second dopant diffuses into a second zone larger than the first zone.

Abstract: A method for manufacturing a semiconductor device includes: forming a trench in a predetermined layer of a semiconductor substrate; heating the substrate having the trench in a non-oxidizing and non-nitridizing atmosphere containing a dopant or a compound that includes the dopant in order to smooth the surfaces defining the trench and to maintain the dopant concentration in the predetermined layer to be a predetermined concentration before the heating is treated; and forming an epitaxially grown film to fill the trench. The conductivity type of the dopant contained in the non-oxidizing and non-nitridizing atmosphere is the same as that of the dopant initially contained in the predetermined layer.

Abstract: Monotomic boron ions for ion implantation are supplied from decaborane vapour. The vapour is fed to a plasma chamber and a plasma produced in the chamber with sufficient energy density to disassociate the decaborane molecules to produce monatomic boron ions in the plasma.

Abstract: A method of ion implantation is provided. The method comprising: providing a substrate; forming a masking image having a sidewall on the substrate; forming a blocking layer on the substrate and on the masking image; and performing a retrograde ion implant through the blocking layer into the substrate, wherein the blocking layer substantially blocks ions scattered at the sidewall of the masking layer.

Abstract: A semiconductor device, such as a CMOS device, having gates with a high work function in PMOS regions and low work functions in NMOS regions and a method of producing the same. Using nitrogen implantation or plasma annealing, a low work function W (or CoSix)/TaSixNy/GOx/Si gate stack is formed in the NMOS regions while a high work function W (or CoSix)/Ta5Si3/GOx/Si gate stack is formed in the PMOS regions. The improved process also eliminates the need for a nitrided GOx which is known to degrade gm (transconductance) performance. The materials of the semiconductor devices exhibit improved adhesion characteristics to adjacent materials and low internal stress.

Abstract: A method for improving a doping profile using gas phase doping is described. In the method, silicon nitride and/or products of decomposition from a silicon nitride deposition are introduced in a process chamber before or during the actual gas phase doping. This allows the doping profile to be significantly improved.

Abstract: Short-channel effects are controlled by forming abrupt, graded halo profiles. Embodiments include sequentially forming deep source/drain regions, ion implanting to form first deep amorphized regions, ion implanting an impurity into the first deep amorphized regions to form first deep halo implants, laser thermal annealing to recrystallize the first deep amorphized regions and activate the deep halo regions, ion implanting to form second shallow amorphized regions within the deep halo regions, ion implanting an impurity into the second shallow amorphous regions to form second shallow halo implants and laser thermal annealing to recrystallize the second shallow amorphous regions and to activate the shallow halo regions. Embodiments further include forming shallow source/drain extensions within the shallow halo implants and laser thermal annealing to activate the shallow source/drain extensions.

Abstract: A solid imaging device comprises a substrate including a semiconductor layer, a middle layer and a support layer, multiple pixels that each have a photoelectric conversion unit that includes a diffusion layer formed on the surface of the semiconductor layer, and insulating areas that are located such that they reach from the surface of the semiconductor layer to the middle layer and work together with the middle layer to electrically separate the pixels from each other.

Abstract: An ion implantation apparatus includes an ion source for extracting ions therefrom at an extraction voltage, an acceleration pipe for accelerating the ions thus extracted at an acceleration voltage of VA and a momentum segregation magnet for selecting the ions having a specific momentum from the ions extracted from the acceleration pipe so that the desired ions are caused to be incident on a target. In the event that MI denotes the mass number of the desired ions, ZI denotes the valence thereof, MC denotes the mass number of noted impurity ions of the impurity ions generated an upstream side of the acceleration pipe, and ZC denotes the valence thereof, if the relationship that the value of MI·(VE+VA)/ZI and that of MC·VA/ZC are equal or approximately equal to each other is satisfied, one of the extraction voltage VE and the acceleration voltage VA is increased and the other thereof is decreased while the value of (VE+VA) is maintained substantially constant.

Abstract: A tunable solid state laser has an optical quality solid material impregnated with a halogen dopant. An optical cavity resonator contains the solid material. An optical excitation source is coupled to the solid material. The doped material has additional applications as a coating to produce white light from blue light emitting diodes.

Abstract: Methods are disclosed for semiconductor device fabrication in which dopants are selectively implanted into transistor gate structures to counteract or compensate for dopant depletion during subsequent fabrication processing. A patterned implant mask is formed over a semiconductor device, which exposes at least a portion of the gate structure and covers the remaining upper surfaces of the device. Thereafter, dopants are selectively implanted into the exposed gate structure.

Abstract: A method for enhancing the equilibrium solid solubility of dopants in silicon, germanium and silicon-germanium alloys. The method involves subjecting silicon-based substrate to biaxial or compression strain. It has been determined that boron solubility was largely enhanced (more than 100%) by a compressive bi-axial strain, based on a size-mismatch theory since the boron atoms are smaller than the silicon atoms. It has been found that the large enhancement or mixing properties of dopants in silicon and germanium substrates is primarily governed by their, and to second order by their size-mismatch with the substrate. Further, it has been determined that the dopant solubility enhancement with strain is most effective when the charge and the size-mismatch of the impurity favor the same type of strain. Thus, the solid solubility of small p-type (e.g., boron) as well as large n-type (e.g.

Abstract: A tunable solid state laser has an optical quality solid material impregnated with a halogen dopant. An optical cavity resonator contains the solid material. An optical excitation source is coupled to the solid material. The doped material has additional applications as a coating to produce white light from blue light emitting diodes.

Abstract: A semiconductor device and method for fabricating a semiconductor device yields improved doping efficiency and increased capacitance. The method includes forming a silicon film on a substrate. HSG having a spherical projection forms on a surface of the silicon film. The surface of the silicon film having the HSG is washed, and a lower electrode forms by a doping process. A dielectric film and an upper electrode are sequentially formed on the silicon film without washing.

Abstract: The present invention discloses an electro-optical device support on a substrate. The electro-optical device includes a sacrificial layer disposed on the substrate having a chamber-wall region surrounding and defining an optical chamber. The electro-optical device further includes a membrane layer disposed on top of the sacrificial layer having a chamber-removal opening surrounding and defining an electric tunable membrane for transmitting an optical signal therethrough. The electrically tunable membrane disposed on top of the optical chamber surrounded by the chamber wall regions. The chamber-wall region is doped with ion-dopants for maintaining the chamber-wall region for removal-resistance under a chamber-forming process performed through the chamber-removal opening. In a preferred embodiment, the chamber-wall region is a doped silicon dioxide region with carbon or nitrogen. In another preferred embodiment, the chamber-wall region is a nitrogen ion-doped SiNxOy region.

Abstract: A method of ion implantation is provided. The method comprising: providing a substrate; forming a masking image having a sidewall on the substrate; forming a blocking layer on the substrate and on the masking image; and performing a retrograde ion implant through the blocking layer into the substrate, wherein the blocking layer substantially blocks ions scattered at the sidewall of the masking layer.