Abstract: An edge termination is produced that is capable of handling high voltages. The edge termination is produced in a base material wafer that is produced in accordance with the principle of lateral charge compensation. The edge termination is formed in the base material wafer by implanting a rapidly diffusing dopant. Preferred dopants are selenium and sulfur. The high-voltage withstand strength is effected by a resulting doping profile which increases towards the edge termination.

Abstract: A surface treatment method includes: a plasma conversion step of using plasma to convert a substance into the form of plasma, thereby generating a first plasma substance and a second plasma substance; a step of beginning introduction of the first plasma substance, which is generated by using the plasma, into a substratum; a step of ending introduction of the first plasma substance into the substratum; a step of observing the state of the second plasma substance, which is generated by using the plasma, prior to the ending step; and a step of controlling a plasma process time, which represents a time interval from the beginning step to the ending step, based on the observation result obtained at the observation step, such that a total dosage of the first plasma substance, which represents a total quantity of the first plasma substance introduced into the substratum, becomes equal to a desired total dosage.

Abstract: An improved MOS-gated power device 300 with a substrate 101 having an upper layer 101a of doped monocrystalline silicon of a first conduction type that includes a doped well region 107 of a second conduction type. The substrate further includes at least one heavily doped source region 111 of the first conduction type disposed in a well region 107 at an upper surface of the upper layer, a gate region 106 having a conductive material 105 electrically insulated from the source region by a dielectric material, a patterned interlevel dielectric layer 112 on the upper surface overlying the gate and source regions 114, and a heavily doped drain region of the first conduction type 115. The improvement includes body regions 301 containing heavily doped polysilicon of the second conduction type disposed in a well region 107 at the upper surface of the monocrystalline substrate.

Abstract: The invention includes an array of devices and a charge pump supported by a semiconductive material substrate. A damage region is under the array, and extends less than or equal to 50% of a distance between the array and the charge pump. The invention also includes a method in which a mask is formed over a monocrystalline silicon substrate. A neutral-conductivity-type dopant is implanted through an opening in the mask and into a section of the substrate to produce a damage region. A first boundary extends around the damage region. The masking layer is removed, and epitaxial silicon is formed over the substrate. An array of devices is formed to be supported by the epitaxial silicon. The array is bounded by a second boundary. The first boundary extends less than or equal to 100 microns beyond the second boundary.

Abstract: A zener diode is formed in a bipolar or BiCMOS fabrication process by modifying the existing masks that are used in the bipolar or BiCMOS fabrication process, thereby eliminating the need for a separate doping step. In addition, the reverse breakdown voltage of the zener diode is set to a desired value within a range of values by modifying the area of a new opening in one of existing masks.

Abstract: A method of manufacturing a flash memory cell in which an ion implantation process is performed before a cleaning process for etching a protrusion of a trench insulating film to a nipple shape. As a result, the etch rate at a portion except for portions in which a moat will occur along the trench insulating film is increased. Therefore, generation of the moat in the trench insulating film can be prevented and spacing of the floating gate can be optimized.

Abstract: A semiconductor memory has a buried bit line structure. One end of the bit line and one end of the diffused impurity layer are connected by being overlapped with each other, and the surface of the source/drain of the selection transistor and the surface of the diffused impurity layer including the connecting portion are silicidized by using metals having high melting points, Ti and Si in this case, thereby forming the titanium silicide layer thereon. This invention not only solves the various problems arising from the buried bit line structure but also realizes sure formation of the silicide, low resistance, greater fineness and high speed operation.

Abstract: A method of manufacturing a semiconductor device that eliminates the n+ contact implant by using double diffused implants under the core cell contacts by forming core, n-channel and p-channel transistors in a semiconductor substrate, simultaneously forming source and drain DDI implants for the core transistors, forming source and drain Mdd implants for the core transistors, forming source and drain Pldd implants for the p-channel transistors, forming source and drain Nldd implants for the n-channel transistors, forming sidewall spacers on the core, n-channel and p-channel transistors, forming N+ implants for the n-channel transistors, forming P+ implants for the p-channel transistors and forming P+ contact implants for the p-channel transistors.

Abstract: A method of manufacturing a monolithic ink-jet printhead includes preparing a silicon substrate, forming an ink passage comprising a manifold supplying ink, an ink chamber filled with ink supplied from the manifold, an ink channel connecting the ink chamber to the manifold, and a nozzle through which the ink is ejected from the ink chamber, on the silicon substrate, and reprocessing a wall of the ink passage by passing XeF2 gas through the ink passage and dry etching the wall of the ink passage. In the reprocessing of the wall of the ink passage using XeF2 gas, the wall of the ink passage is smoothed, and a size of the ink passage can be more precisely adjusted to a design dimension, thereby improving a printing performance of the ink-jet printhead.

Abstract: A method of reducing leakage current of a photodiode on a semiconductor wafer. The semiconductor wafer has a p-type substrate, a photosensing area, and at least one shallow trench surrounding the photosensing area. First, a doped polysilicon layer containing p-type dopants is formed in the shallow trench. Then, the p-type dopant in the doped polysilicon layer is caused to diffuse into the p-type substrate to form a p-type doped region surrounding a bottom of the shallow trench and walls of the shallow trench. After that, the doped polysilicon layer is removed and an insulator material is filled into the shallow trench to form a shallow trench isolation (STI) structure. Finally, an n-type doped region is implanted to form a photosensor. Here, the p-type doped region in the photosensing area is used to decrease the electric field surrounding the photosensing area and decrease the leakage current.

Abstract: A method is provided for making ultra-shallow diffused junctions using an elemental dopant. A semiconductor wafer is cleaned for providing a clean reaction surface. The cleaned wafer in loaded onto a stage located in a doping system. A quantity of elemental dopant atoms are placed in a partially enclosed elemental dopant source which is within a secondary vacuum enclosure. A quantity of the elemental dopant atoms having thermal velocities are deposited onto a surface of the wafer, and the wafer is heated for diffusing the elemental dopant into the wafer. In one embodiment, the heating is conducted by heating the wafer in ultra-high vacuum for diffusing the portion of the doping atoms into the wafer, and the deposition and heating occur simultaneously. In another embodiment, the surface of the wafer is hydrogen terminated, the wafer is removed from the UHV system, and the heating of the wafer is conducted outside of the UHV system by heating the wafer in a furnace.

Abstract: A semiconductor device having an alternating conductivity type layer improves the tradeoff between the on-resistance and the breakdown voltage and facilitates increasing the current capacity by reducing the on-resistance while maintaining a high breakdown voltage. The semiconductor device includes a semiconductive substrate region, through which a current flows in the ON-state of the device and that is depleted in the OFF-state. The semiconductive substrate region includes a plurality of vertical alignments of n-type buried regions 32 and a plurality of vertical alignments of p-type buried regions. The vertically aligned n-type buried regions and the vertically aligned p-type buried regions are alternately arranged horizontally. The n-type buried regions and p-type buried regions are formed by diffusing respective impurities into highly resistive n-type layers 32a laminated one by one epitaxially.

Abstract: A method for forming a desired junction profile in a semiconductor device. At least one dopant is introduced into a semiconductor substrate. The at least one dopant is diffused in the semiconductor substrate through annealing the semiconductor substrate and the at least one dopant while simultaneously exposing the semiconductor substrate to an electric field.

Abstract: Methods of forming metal-doped chalcogenide layers and devices containing such doped chalcogenide layers include using a plasma to induce diffusion of metal into a chalcogenide layer concurrently with metal deposition. The plasma contains at least one noble gas of low atomic weight, such as neon or helium. The plasma has a sputter yield sufficient to sputter a metal target and a UV component of its emitted spectrum sufficient to induce diffusion of the sputtered metal into the chalcogenide layer. Using such methods, a conductive layer can be formed on the doped chalcogenide layer in situ. In integrated circuit devices, such as non-volatile chalcogenide memory devices, doping of the chalcogenide layer concurrently with metal deposition and formation of a conductive layer in situ with the doping of the chalcogenide layer reduces contamination concerns and physical damage resulting from moving the device substrate from tool to tool, thus facilitating improved device reliability.

Abstract: Methods of forming metal-doped chalcogenide layers and devices containing such doped chalcogenide layers include using a plasma to induce diffusion of metal into a chalcogenide layer concurrently with metal deposition. The plasma contains at least one noble gas of low atomic weight, such as neon or helium. The plasma has a sputter yield sufficient to sputter a metal target and a UV component of its emitted spectrum sufficient to induce diffusion of the sputtered metal into the chalcogenide layer. Using such methods, a conductive layer can be formed on the doped chalcogenide layer in situ. In integrated circuit devices, such as non-volatile chalcogenide memory devices, doping of the chalcogenide layer concurrently with metal deposition and formation of a conductive layer in situ with the doping of the chalcogenide layer reduces contamination concerns and physical damage resulting from moving the device substrate from tool to tool, thus facilitating improved device reliability.

Abstract: For particularly simple and targeted formations of a diffusion region, an interfacial region of a semiconductor substrate is subjected to a thermal transformation process and thereby carry out the thermally activated diffusion of a dopant in a substantially directed form, in particular in substantially a preferential direction, by interaction of a provided dopant with a transforming interfacial region.

Abstract: A process used to retard out diffusion of P type dopants from P type LDD regions, resulting in unwanted LDD series resistance increases, has been developed. The process features the formation of a nitrogen containing layer, placed between the P type LDD region and overlying silicon oxide regions, retarding the diffusion of boron from the LDD regions to the overlying silicon oxide regions, during subsequent high temperature anneals. The nitrogen containing layer, such as a thin silicon nitride layer, or a silicon oxynitride layer, formed during or after reoxidation of a P type polysilicon gate structure, is also formed in a region that also retards the out diffusion of P type dopants from the P type polysilicon gate structure.

Abstract: A method for reducing optical loss in opto-electronic devices includes passivating P-type dopant impurities formed within various cladding and contact layer films. The passivating species is atomic hydrogen produced by a hydrogen containing plasma. The atomic hydrogen complexes with P-type dopant impurities to form electrically neutral pairs which are void of free carriers. Absorption, and loss, of the optical wave is therefore suppressed as it propagates through the P-doped layers because of the reduced free carrier concentration in the P-doped layers.

Abstract: A method for fabricating a low temperature polysilicon thin film transistor incorporating a channel passivation step is described. The method achieves dopant ion activation in a polysilicon gate by using laser irradiation, however, with an additional insulating material layer such as SiOx or SixNy overlying and protecting the channel portion of the polysilicon gate. Any possible contamination by residual photoresist material after a photoresist removal step on the channel portion of the polysilicon gate can thus be avoided. Furthermore, deficiencies such as dopant ions out-diffusion and lateral diffusion can be avoided. The leakage current of the thin film transistors formed by the present invention method is significantly reduced when compared to those formed by a conventional method.

Abstract: A method of forming an image sensor is disclosed. A partially processed semiconductor wafer is provide, containing p-type and/or n-type regions which are bounded by isolation regions and with gate oxide layers grown on the surfaces upon which gate electrode structures are disposed, some of said gate electrode structures will serve as gate electrodes of image sensor transistors. Ions are implanted to form source/drain structures about the said gate electrode structures. To form photodiodes ions are implanted in two steps overlapping a source/drain region. A deeper implant provides a low charge carrier density region and a shallow implant provides a high charge carrier density region near the surface. A blanket transparent insulating layer is deposited.

Abstract: An improved dopant application system and method for the manufacture of microelectronic devices accurately places dopant on and within a dielectric or semiconductor surface. Diffusing and activating p-type and n-type dopants in dielectric or semiconductor substrates is achieved by means of electron beam irradiation.

Abstract: A method of metal doping a chalcogenide material includes forming a metal over a substrate. A chalcogenide material is formed on the metal. Irradiating is conducted through the chalcogenide material to the metal effective to break a chalcogenide bond of the chalcogenide material at an interface of the metal and chalcogenide material and diffuse at least some of the metal outwardly into the chalcogenide material. A method of metal doping a chalcogenide material includes surrounding exposed outer surfaces of a projecting metal mass with chalcogenide material. Irradiating is conducted through the chalcogenide material to the projecting metal mass effective to break a chalcogenide bond of the chalcogenide material at an interface of the projecting metal, mass outer surfaces and diffuse at least some of the projecting metal, mass outwardly into the chalcogenide material. In certain aspects, the above implementations are incorporated in methods of forming non-volatile resistance variable devices.

Abstract: Semiconductor processing methods of forming integrated circuitry, and in particular, dynamic random access memory (DRAM) circuitry are described. In one embodiment, a single masking step is utilized to form mask openings over a substrate, and both impurities are provided and material of the substrate is etched through the openings. In one implementation, openings are contemporaneously formed in a photo masking layer over substrate areas where impurities are to be provided, and other areas where etching is to take place. In separate steps, the substrate is doped with impurities, and material of the substrate is etched through the mask openings. In another implementation, two conductive lines are formed over a substrate and a masking layer is formed over the conductive lines. Openings are formed in the masking layer in the same step, with one of the openings being received over one conductive line, and another of the openings being received over the other conductive line.

Abstract: An enhanced n+ silicon material for epitaxial substrates and a method for producing it are described. The enhanced material leads to improved gettering characteristics of n/n+ epitaxial wafers based on these substrates. The method for preparing such n+ silicon material includes applying a co-doping of carbon to the usual n dopant in the silicon melt, before growing respective CZ crystals. This improves yield of enhanced n+ silicon material in crystal growing and ultimately leads to device yield stabilization or improvement when such n/n+ epitaxial wafers are applied in device manufacturing.

Abstract: Self-aligned floating gates are formed to have precisely defined lengths and positions. The floating gates are formed by first forming a number of shallow trench isolation regions that have substantially planar top surfaces that lie above the top surface of the semiconductor material. A layer of dielectric is formed on the semiconductor material, followed by the formation of a first layer of polysilicon. The first layer of polysilicon is then planarized so that the first layer of polysilicon is removed from the isolation regions. In subsequent steps, the polysilicon is again etched to form the floating gates. As a result of the planarization, the lengths of the floating gates are defined by the spacing between isolation regions, and the positions of the floating gates are precisely defined.

Abstract: A method for extracting the capacitance value associated with a PN junction along the well-substrate interface for use in modeling the substrate. The method includes receiving the 2-D or 1-D mesh doping profile. The method includes finding a junction curve or transition region that represents the transition between the well and the substrate bulk. The method further includes finding a set of parameters &agr;,&bgr; and &ggr; to characterize the junction at a point or a vertical discretization along the transition. During modeling, the set of parameters &agr;, &bgr; and &ggr; is then employed, along with the input bias voltage value, to calculate the thickness of the depletion region, which is in turn employed to calculate the capacitance for the well-substrate junction. The capacitance calculated is then employed to more accurately model the junction, which leads to a more accurate model for the substrate.

Abstract: There is a method of manufacturing a semiconductor element with a variety of types and at low cost.

Abstract: We provide a method of doping an Si or SiGe film with carbon or boron. By reducing the silicon precursor pressure, heavily-doped films may be obtained. A single dopant source may be used. The doped Si and SiGe films are of suitable quality for use in a transistor such as an HBT.

Abstract: To form an impurity diffusion layer on only one side of a semiconductor substrate at least one semiconductor substrate and at least one diffusion protecting plate are put close to each other and a first impurity diffusion is perfomed on them, or at least one semiconductor substrate and at least one diffusion protecting plate are put close to each other and a first impurity diffusion is performed on them and then the semiconductor substrate and the diffusion protecting plate are arranged such that those sides on which the impurity diffusion has been performed face each other and a second impurity diffusion is performed. The diffusion protecting plate may be replaced by a semiconductor substrate. The first and second impurity diffusions may be performed using an impurity of the same conductivity type.

Abstract: Both P type and N type impurities are implanted from a plurality of directions. The tilt angle &thgr; of the implantation direction against the normal of the main surface of a semiconductor substrate is fixed to 10°, and the deflection angle &phgr; is set to such four directions (X, X+90°, X+180°, and X+270°, where X is an arbitrary angle) that projecting components of a vector indicating the implantation direction are opposed to each other on two lines that cross each other at right angles along the main surface of the semiconductor substrate. Thereby, the dependency of the breakdown voltage of element isolation on the direction of a well boundary is suppressed to realize a high breakdown voltage of element isolation in all directions.

Abstract: A method of manufacturing an integrated circuit utilizes solid phase epitaxy to form a channel region. The method includes providing an amorphous semiconductor material including germanium, crystallizing the amorphous semiconductor material via solid phase epitaxy, and doping to form a source location and a drain location. The semiconductor material containing germanium can increase the charge mobility associated with the transistor.

Abstract: Within both a method for operating a multi-chamber fabrication tool and a system for operating the multi-chamber fabrication tool, there is first provided a multi-chamber fabrication tool comprising a series of chambers. There is also defined for each chamber within the series of chambers a minimum of one fabrication process to provide a series of fabrication processes corresponding with the series of chambers, wherein at least one fabrication process may be undertaken within more than one chamber and at least one chamber has defined therein more than one fabrication process including the at least one fabrication process which may be undertaken within more than one chamber.

Abstract: A semiconductor component includes a semiconductor layer (110) having a trench (326). The trench has first and second sides. A portion (713) of the semiconductor layer has a conductivity type and a charge density. The semiconductor component also includes a control electrode (540, 1240) in the trench. The semiconductor component further includes a channel region (120) in the semiconductor layer and adjacent to the trench. The semiconductor component still further includes a region (755) in the semiconductor layer. The region has a conductivity type different from that of the portion of the semiconductor layer. The region also has a charge density balancing the charge density of the portion of the semiconductor layer.

Abstract: A method of driving-in antimony into a wafer, including the following steps. A wafer is loaded into an annealing furnace/tool. The wafer having an area of implanted antimony ions. The wafer is annealed a first time at a first temperature in the presence of only a first nitrogen gas flow rate. The wafer is ramped-down from the first temperature to a second temperature in the presence of only an oxygen gas flow rate. The wafer is maintained in the presence of the of oxygen gas flow rate at the second temperature. The wafer is ramped-up from the second temperature to a third temperature in the presence of only the oxygen gas flow rate. The wafer is annealed a second time at the third temperature in the presence of only a second nitrogen gas flow rate to drive-in the antimony ions within the area of implanted antimony.

Abstract: The high current capabilities of a lateral npn transistor for application as a protection device against degradation due to electrostatic discharge (ESD) events are improved by adjusting the electrical resistivity of the material through which the collector current flows from the avalanching pn-junction to the wafer backside contact. As expressed in terms of the second threshold current improvements by a factor of 4 are reported. Two implant sequences are described which apply local masking and standard implant conditions to achieve the improvements without adding to the total number of process steps. The principle of p-well engineering is extended to ESD protection devices employing SCR-type devices.

Abstract: First of all, a junction protecting layer are formed on the semiconductor substrate. The junction protecting layer is then etched to expose a partial surface of the semiconductor substrate as an opening. Next, a semiconductor layer is formed over the junction protecting layer to fill the opening. After forming a gate on the semiconductor layer, implanting the LDD in the semiconductor layer. Afterward, a spacer layer is conformed along the surfaces of the gate and the LDD. Subsequently, performing an etching process to etch through the spacer layer, the semiconductor layer, and the junction protecting layer until exposing the partial surfaces of the semiconductor substrate, so as to form the etched regions and a spacer beside each sidewall of the gate. Finally, the source/drain region is formed respectively in each etched region, after the etched regions are filled with the material the same with the substrate.

Abstract: A method is described for safe gas phase doping a semiconductor with arsenic. The substrate including a semiconductor structure is exposed to arsine at elevated temperatures within a reaction chamber. Thereafter, prior to opening the reaction chamber, a sealant layer is formed over the semiconductor structure. The sealant layer inhibits outdiffusion of arsenic when the substrate is unloaded from the reaction chamber, enabling safe unloading at relatively high temperatures. In the illustrated embodiments, the sealant layer can be formed by oxidation, nitridation or chemical vapor deposition. Forming the sealant layer can be conducted prior to, during or after cooling the substrate to an unloading temperature. Preferably, a gettering step is conducted after gas phase doping and prior to forming the sealant layer, such as by exposing the substrate to HCl vapor.

Abstract: A structure for doping of III-V compounds is provided. The structure is a multi-layered structure in which layers of dopant are alternated with layers of initially undoped III-V compound. Dopant diffuses from the layers of dopant into the layers of III-V compound. The structure does not facilitate the introduction of impurities into the III-V compound during the diffusion of the dopant.

Abstract: In an ion implantation method using an ion implantation equipment having an extraction electrode and a post accelerator, ion is uniformly implanted into a shallow region from the surface of a sample by setting an applied volt. of the post accelerator higher than an applied volt. of the extraction electrode.

Abstract: Various methods of fabricating circuit devices are provided. In one aspect, a method of fabricating a circuit device on a substrate is provided. The method includes forming a doped silicon structure on the substrate and forming a hemispherical grain silicon film on the silicon structure. The substrate is heated from a first temperature to a second temperature while undergoing exposure to a dopant gas to add a dopant to the hemispherical grain silicon film. The method provides for improved capacitor electrode fabrication via concurrent gas exposure and substrate temperature ramp-up. In this way, dopant gas is introduced before the doped silicon structure transitions from an amorphous state to a polycrystalline state.

Abstract: We have discovered that, contrary to conventional wisdom about forming DP defects, electrical saturation in highly doped 2D layers of Si does not occur. In accordance with one aspect of our invention, free-carrier concentrations in excess of about 7×1020 cm−3 can be attained in single crystal Si layers &dgr;-doped with a Group V element. In one embodiment, free-carrier concentrations in excess of about 2×1021 cm−3 are realized in single crystal Si that is &dgr;-doped with Sb. In another embodiment, the &dgr;-doped layer is formed as an integral part of an FET.

Abstract: A method of forming a diffusion region in a silicon substrate having low-resistance, acceptable defect density, reliability and process control comprising the steps of: (a) subjecting a silicon substrate to a first ion implantation step, said first ion implantation step being conducted under conditions such that a region of amorphized Si is formed in said silicon substrate; (b) subjecting said silicon substrate containing said region of amorphized Si to a second ion implantation step, said second ion implantation step being carried out by implanting a dopant ion into said silicon substrate under conditions such that the peak of implant of said dopant ion is within the region of amorphized Si; and (c) annealing said silicon substrate under conditions such that said region of amorphized Si is re-crystallized thereby forming a diffusion region in said silicon substrate is provided.

Abstract: A method of increasing the selectivity of silicon nitride deposition. A substrate is provided. A silicon oxide layer is formed over a portion of the substrate. Ammonia NH3 is passed over the silicon oxide layer and the substrate surface for a definite period to perform a surface treatment. Silicon nitride is subsequently deposited over the substrate and the silicon oxide layer.

Abstract: A semiconductor material and a method for forming the same, said semiconductor material having produced by a process comprising melting a noncrystal semiconductor film containing therein carbon, nitrogen, and oxygen each at a concentration of 5×1019 atoms·cm−3 or lower, preferably 1×1019 atoms·cm−3 or lower, by irradiating a laser beam or a high intensity light equivalent to a laser beam to said noncrystal semiconductor film, and then recrystallizing the thus molten amorphous silicon film. The present invention provides thin film semiconductors having high mobility at an excellent reproducibility, said semiconductor materials being useful for fabricating thin film semiconductor devices such as thin film transistors improved in device characteristics.

Abstract: A process for fabricating a memory cell, the process includes forming an ONO layer overlying a semiconductor substrate, depositing a masking layer overlying the ONO layer, patterning the masking layer into a resist mask, implanting the semiconductor substrate with a p-type dopant to create a p-type region, and laterally diffusing the p-type region. In one preferred embodiment, the lateral diffusing of the p-type region includes exposing the semiconductor substrate to a thermal cycle. Preferably, the thermal cycle is a rapid thermal anneal or a furnace anneal.

Abstract: A method of fabricating an integrated circuit (IC) with source and drain extension regions. Advantageously, the source and drain extension regions are formed without damage related to integrated circuit implant techniques. Damage is avoided by using solid phase doping to form extension regions. Generally, a doped material is provided adjacent to a transistor gate structure and the IC is annealed. During the annealing process, dopants from the doped material diffuse into the semiconductor substrate to form the source and drain extension regions. The process can be utilized for P-channel or N-channel metal oxide field semiconductor effect transistors (MOSFETs).

Abstract: Extremely high dopant concentrations are uniformly introduced into a semiconductor material by laser annealing aided by an anti-reflective coating (ARC). A spin-on-glass (SOG) film containing dopant is formed on top of the semiconductor material. An ARC is then formed over the doped SOG layer. Application of radiation from an excimer laser to the ARC heats and melts the doped SOG film and the underlying semiconductor material. During this melting process, dopant from the SOG film diffuses uniformly within the semiconductor material. Upon removal of the laser radiation, the semiconductor material cools and crystallizes, evenly incorporating the diffused dopant within its lattice structure. The ARC suppresses reflection of the laser by the doped material, promoting efficient transfer of energy from the laser to heat and melt the underlying doped layer and semiconductor material.

Abstract: Methods of making hardmask assemblies or other layered structures, and other masks, include providing an annular seal member between a first surface of layered structure, preferably a hardmask assembly, and a first clamp element, the hardmask assembly comprising at least a hardmask layer; and applying a force between the first clamp element and a second clamp element to hold the hardmask assembly between the annular seal member and the second clamp element. In addition, there are provided methods further comprising etching the first surface of the hardmask assembly within the bounds of an interior space defined by the annular seal member. Methods further comprise etching the substrate layer through the hardmask layer and/or removing the hardmask layer after etching the substrate layer.

Abstract: A method for forming a semiconductor device is provided. A base layer is provided. A first epitaxial layer having a first dopant at a first concentration is formed above the base layer. A second epitaxial layer having a second dopant at a second concentration is formed above the first epitaxial layer. The second concentration is greater than the first concentration. A third epitaxial layer having a third dopant at a third concentration is formed above the second epitaxial layer. The third concentration is less than the second concentration. Ions are implanted in the third epitaxial layer to form an implant region. The implant region is in contact with the second epitaxial layer. A semiconductor device comprises a base layer, first, second, and third epitaxial layers, and an implant region. The first epitaxial layer has a first dopant at a first concentration disposed above the base layer. The second epitaxial layer has a second dopant at a second concentration disposed above the first epitaxial layer.

Abstract: A method for forming a thin film transistor with lightly doped drain structure comprising the steps of forming a gate insulating layer and a gate electrode on a polysilicon layer; forming a photoresist layer on the gate electrode and on a portion of the polysilicon layer; and implanting first conductive type impurities into the polysilicon layer so as to form a first ion-implant region and a second ion-implant region, wherein the doping concentration of the second ion-implant region is higher than that of the first ion-implant region.