Abstract: A method of forming an isolation trench structure is disclosed, the method includes forming an isolation trench in a semiconductor body associated with an isolation region, and implanting a non-dopant atom into the isolation trench, thereby forming a region to modify the halo profile in the semiconductor body. Subsequently, the isolation trench is filled with a dielectric material.

Abstract: An RTA method has a limitation on miniaturization. The RTA method needs a heating time of several seconds, and has a risk that impurities are diffused into a deep portion, since a semiconductor substrate is heated at a high temperature. Thus, the RTA method has a difficulty in responding miniaturization which is expected in the future. According to the present invention, a fundamental wave is used without putting laser light into a non-linear optical device, and laser annealing is conducted by irradiating an impurity diffusion layer with pulsed laser light having high intensity and a high repetition rate, so as to electrically activate the impurities. By the present invention, a thin layer on the surface of a silicon substrate can be partially melted to conduct activation. Further, the width of the region activated by laser-scanning once can be increased, and thus the productivity can be enhanced dramatically.

Abstract: An absorption modulator is provided. The absorption modulator includes a substrate, an insulation layer disposed on the substrate, and a waveguide having a P-I-N diode structure on the insulation layer. Absorptance of an intrinsic region in the P-I-N diode structure is varied when modulating light inputted to the waveguide. The absorption modulator obtains the improved characteristics, such as high speed, low power consumption, and small size, because it greatly reduces the cross-sectional area of the P-I-N diode structure.

Abstract: An image sensor and a method of manufacturing the same are provided. A metal wiring layer is formed on a semiconductor substrate including a circuit region, and first conductive layers are formed on the metal layer separated by a pixel isolation layer. An intrinsic layer is formed on the first conductive layers, and a second conductive layer is formed on the intrinsic layer.

Abstract: This invention discloses a bottom-anode Schottky (BAS) diode that includes an anode electrode disposed on a bottom surface of a semiconductor substrate. The bottom-anode Schottky diode further includes a sinker dopant region disposed at a depth in the semiconductor substrate extending substantially to the anode electrode disposed on the bottom surface of the semiconductor and the sinker dopant region covered by a buried Schottky barrier metal functioning as a Schottky anode.

Abstract: Provided are methods of forming a semiconductor device, the method including: forming an insulation region on a substrate region, and an active region on the insulation region; patterning the active region to form an active line pattern; forming a gate pattern to surround an upper portion and lateral portions of the active line pattern; separating the gate pattern into a plurality of sub-gate regions, and separating the active line pattern into a plurality of sub-active regions, in order to form a plurality of memory cells that are each formed of the sub-active region and the sub-gate region and that are separated from one another; and forming first and second impurity doping regions along both edges of the sub-active regions included in each of the plurality of the memory cells, wherein the forming of the first and second impurity doping regions comprises doping lateral portions of the sub-active regions via a space between the memory cells.

Abstract: To provide a method of controlling a conductivity of a Ga2O3 system single crystal with which a conductive property of a ?-Ga2O3 system single crystal can be efficiently controlled. The light emitting element includes an n-type ?-Ga2O3 substrate, and an n-type ?-AlGaO3 cladding layer, an active layer, a p-type ?-AlGaO3 cladding layer and a p-type ?-Ga2O3 contact layer which are formed in order on the n-type ?-Ga2O3 substrate. A resistivity is controlled to fall within the range of 2.0×10?3 to 8×102 ?cm and a carrier concentration is controlled to fall within the range of 5.5×1015 to 2.0×1019/cm3 by changing a Si concentration within the range of 1×10?5 to 1 mol %.

Abstract: A ZnO layer is provided which can obtain emission at a wavelength longer than blue (e.g., 420 nm) and has a novel structure. A transition energy narrower by 0.6 eV or larger than a band gap of ZnO can be obtained by doping S into a ZnO layer.

Abstract: A bipolar semiconductor device and manufacturing method. One embodiment provides a diode structure including a structured emitter coupled to a first metallization is provided. The structured emitter includes a first weakly doped semiconductor region of a first conductivity type which forms a pn-load junction with a weakly doped second semiconductor region of the diode structure. The structured emitter includes at least a highly doped first semiconductor island of the first conductivity type which at least partially surrounds a highly doped second semiconductor island of the second conductivity type.

Abstract: A micro-electromechanical resonator includes a resonator body having a semiconductor region therein doped with boron to a level greater than about 1×1018 cm?3 and even greater than about 1×1019 cm?3, in order to obtain reductions in the temperature coefficient of frequency (TCF) of the resonator over a relatively large temperature range. Still further improvements in TCF can be achieved by degenerately doping the resonator body with boron and/or by boron-assisted aluminum doping of the resonator body.

Abstract: An organic light emitting diode (OLED) display panel and a method of forming a polysilicon channel layer thereof are provided. In the method, firstly, a substrate having a polysilicon layer disposed thereon is provided. Then, a dopant atom not selected from the IIIA group and the VA group is doped inside the polysilicon layer to form a polysilicon channel layer.

Abstract: In a calibration method, the relation between dopant concentrations of ?-doping layers in a multilayered semiconductor structure and process parameters is determined S1 based on multiple bulk specimens of the material in which the ?-doping layers are located. A desired dopant concentration is selected S2, and the semiconductor structure with predetermined doping levels can be generated S3 based on the relation between the process parameters and the predetermined doping concentrations.

Abstract: The present invention generally relates to a method for improving inversion layer mobility and providing low defect density in a semiconductor device based upon a silicon carbide (SiC) substrate. More specifically, the present invention provides a method for the manufacture of a semiconductor device based upon a silicon carbide substrate and comprising an oxide layer comprising incorporating at least one additive into the atomic structure of the oxide layer. Semiconductor devices, such as MOSFETS, based upon a substrate treated according to the present method are expected to have inversion layer mobilities of at least about 60 cm2/Vs.

Abstract: A semiconductor method includes thermally treating at least a portion of a substrate so as to generate a plurality of vacancies in a region at a depth substantially near to a surface of the substrate. The substrate is then quenched so as to substantially maintain the vacancies in the region substantially near to the surface of the substrate.

Abstract: A method for manufacturing a semiconductor device including a first conductive type impurity region formed by introducing a first conductive type impurities in a first region of a semiconductor region and heating the first region, a second conductive type impurity region formed by introducing a second conductive type impurities in a second region of the semiconductor region and heating the second region, the method including covering the second region with a mask and then introducing the first conductive type impurities in a surface of the first region, removing the mask by a process using gas including oxygen while forming an oxide film on the surface of the first region by the processing using the gas including the oxygen, and introducing the second conductive type impurities in a surface of the second region by using the oxide film as a mask.

Abstract: A method for manufacturing a semiconductor device includes forming an impurity diffusion layer in a surface of a semiconductor substrate, wherein the forming the impurity diffusion layer comprises irradiating material including M1x M2y (y/x?1.2, where x is a ratio of M1, y is a ratio of M2, M1 is material which serves as acceptor or donor in the semiconductor device, M2 is material which does not serve as neither donor nor acceptor in the semiconductor device (except semiconductor of the semiconductor substrate)) onto the semiconductor substrate, and heating the semiconductor substrate by light.

Abstract: A memory element having a resistance variable material and methods for forming the same are provided. The method includes forming a plurality of first electrodes over a substrate and forming a blanket material stack over the first electrodes. The stack includes a plurality of layers, at least one layer of the stack includes a resistance variable material. The method also includes forming a first conductive layer on the stack and etching the conductive layer and at least one of the layers of the stack to form a first pattern of material stacks. The etched first conductive layer forming a plurality of second electrodes with a portion of the resistance variable material located between each of the first and second electrodes.

Abstract: A cascode amplifier (CA) (60) is described having a bottom transistor (T1new) with a relatively thin gate dielectric (67) and higher ratio (RB) of channel length (Lch1new) to width (W1new) and a series coupled top transistor (T2new) with a relatively thick gate dielectric (68) and a lower ratio (RT) of channel length (Lch2new) to width (W2new). An improved cascode current mirror (CCM) (74) is formed using a coupled pair of CAs (60, 60?), one (60) forming the reference current (RC) side (601) and the other (60?) forming the mirror current side (602) of the CCM (74). The gates (65, 65?) of the bottom transistors (T1new, T3new) are tied together and to the common node (21) between the series coupled bottom (T1new) and top (T2new) transistors of the RC side (601), and the gates (66?, 66?) of the top transistors (T2new, T4new) are coupled together and to the top drain node (64) of the RC side (601).

Abstract: A method for fabricating a three-dimensional photonic crystal comprises the steps of: forming a dielectric thin film; injecting ions selectively into the dielectric thin film by using a focus ion beam to form a mask on the dielectric thin film; forming a pattern by selectively removing an exposed part of the dielectric thin film at which the mask is not formed on the dielectric thin film; forming a sacrificial layer on the dielectric thin film having the pattern formed therein; and flattening the sacrificial layer formed on the dielectric thin film until the pattern comes to the surface.

Abstract: A far subcollector, or a buried doped semiconductor layer located at a depth that exceeds the range of conventional ion implantation, is formed by ion implantation of dopants into a region of an initial semiconductor substrate followed by an epitaxial growth of semiconductor material. A reachthrough region to the far subcollector is formed by outdiffusing a dopant from a doped material layer deposited in the at least one deep trench that adjoins the far subcollector. The reachthrough region may be formed surrounding the at least one deep trench or only on one side of the at least one deep trench. If the inside of the at least one trench is electrically connected to the reachthrough region, a metal contact may be formed on the doped fill material within the at least one trench. If not, a metal contact is formed on a secondary reachthrough region that contacts the reachthrough region.

Abstract: Low dielectric constant group II-VI compounds, such as zinc oxide, and fabrication methods are disclosed. Low dielectric constant insulator materials are fabricated by doping zinc oxide with at least one mole % p-type dopant ion. Low dielectric constant zinc oxide insulator materials are fabricated by doping zinc oxide with silicon having a concentration of at least 1017 atoms/cm3. Low dielectric zinc oxide insulator materials are fabricated by doping zinc oxide with a dopant ion having a concentration of at least about 1018 atoms/cm3, followed by heating to a temperature which converts the zinc oxide to an insulator. The temperature varies depending upon the choice of dopant. For arsenic, the temperature is at least about 450° C.; for antimony, the temperature is at least about 650° C. The dielectric constant of zinc oxide semiconductor is lowered by doping zinc oxide with a dopant ion at a concentration at least about 1018 to about 1019 atoms/cm3.

Abstract: A method to provide a dopant profile adjustment solution in plasma doping systems for meeting both concentration and junction depth requirements. Bias ramping and bias ramp rate adjusting may be performed to achieve a desired dopant profile so that surface peak dopant profiles and retrograde dopant profiles are realized. The method may include an amorphization step in one embodiment.

Abstract: Methods of making Si-containing films that contain relatively high levels of Group III or Group V dopants involve chemical vapor deposition using trisilane and a dopant precursor. Extremely high levels of substitutional incorporation may be obtained, including crystalline silicon films that contain at least about 3×1020 atoms cm?3 of an electrically active dopant. Substitutionally doped Si-containing films may be selectively deposited onto the crystalline surfaces of mixed substrates by introducing an etchant gas during deposition.

Abstract: A semiconductor structure comprises a drift region of a first conductivity type in a semiconductor region. A well region of a second conductivity type is over the drift region. A source region of the first conductivity type is in an upper portion of the well region. A heavy body region of the second conductivity type extends in the well region. The heavy body region has a higher doping concentration than the well region. A first diffusion barrier region at least partially surrounds the heavy body region. A gate electrode is insulated from the semiconductor region by a gate dielectric.

Abstract: Disclosed is an improved construction of an ultrasonic transducer, wherein a charge is not easily injected into an insulating film even when the bottom of a membrane comes in contact with a lower electrode, and a manufacturing method thereof without using the wafer laminating technique. The ultrasonic transducer includes a lower electrode; a cavity layer formed on the first electrode; an insulating film covering the cavity layer; and an upper electrode formed on the insulating film, wherein, the cavity layer includes projections formed into an insulating film protruded from the cavity layer. In addition, an opening is formed into the upper electrode, and this upper electrode having the opening formed therein is deposited at a position not being superposed with the projections of the insulating film when seen from the top.

Abstract: A process for realizing TFT devices on a substrate comprises the steps of: forming on the substrate, in cascade, an amorphous silicon layer and a heavily doped amorphous silicon layer, forming a photolithographic mask on the heavily doped amorphous silicon layer provided with an opening, removing the heavily doped amorphous silicon layer through the opening for realizing opposite portions of the heavily doped amorphous silicon layer whose cross dimensions decrease as long as they depart from the amorphous silicon layer, removing the photolithographic mask, carrying out a diffusion and activation step of the dopant contained in the portions of the heavily doped amorphous silicon layer inside the amorphous silicon layer, for realizing source/drain regions of said TFT device.

Abstract: An electromegasonic wafer cleaning system is disclosed that is extremely important, if not essential, in the fabrication of advanced microelectronic devices having a line width or feature size of from 0.05 to 0.10 micron. A unique synergistic combination is provided wherein piezoelectric transducer means are operated at a tolerable power level, such as from 1 to 2 watts per square centimeter, to minimize the risk of harm to the extremely delicate microcircuits and wherein the face of each wafer is negatively charged to a temperate voltage, such as from 5 to 20 volts, sufficient to cause effective removal of colloidal or sub 0.4-micron contaminant particles. This unique wafer cleaning system supersedes and replaces the standard megasonic-assisted RCA-type wet wafer cleaning systems which have never been able to eliminate or provide efficient purging of harmful sub 0.1-micron particles.

Abstract: A method for fabricating a component is disclosed. The method includes: providing a member having an effective work function of an initial value, disposing a sacrificial layer on a surface of the member, disposing a first agent within the member to obtain a predetermined concentration of the agent at said surface of the member, annealing the member, and removing the sacrificial layer to expose said surface of the member, wherein said surface has a post-process effective work function that is different from the initial value.

Abstract: A method that suppresses etching damage without increasing a chip area of a semiconductor device. An integrated circuit including a MOS transistor is formed in a device area, and a discharge diffusion region is formed in a device area, and a discharge diffusion region is formed in a grid area. The discharge diffusion region is connected to a metal wiring of the integrated circuit via a contact hole. Therefore, when the metal wiring is formed by a dry etching method, an electric charge stored in the metal wiring is discharged to a semiconductor substrate through the discharge diffusion region. Thus, etching damage of the MOS transistor is reduced. Since the discharge diffusion region and the contact hole are formed within the grid area, they are cut off by a dicing process, thus causing no increase in chip area of the semiconductor device.

Abstract: A method is provided for controlling a dose amount of dopant to be doped into an object to be processed in plasma doping. According to the method, the doping control is formed of the following processes: determining the temperature of the object, the amount of ions having dopant in plasma that collide with the object, and types of gases in plasma during doping; calculating a dose amount by neutral gas according to the temperature of the object, and a dose amount by ions from the determined amount of ions containing dopant that collide with the object; and carrying out doping so that the sum of the dose amount by neutral gas and the dose amount by ions equal to a predetermined dose amount.

Abstract: Indium oxide nanowires are used for determining information about different chemicals or Biologics. Chemicals are absorbed to the surface of the nanowires, and cause the semiconducting characteristics of the Nanowires to change. These changed characteristics are sensed, and used to determine either the presence of the materials and/or the concentration of the materials. The nanowires may be between 10 and 30 nm in diameter, formed using a comparable size particle of catalyst material. The nanowires may then be used as part of the channel of a field effect transistor, and the field effect transistor is itself characterized.

Abstract: A manufacturing method includes sequentially forming first and second material layers having different etch selectivities in a laminated fashion, patterning the second material layer, to form an etch mask, etching the first material layer using the etch mask, to form a via hole in the first material layer, forming a photo mask over the etch mask such that a region larger than the via hole is exposed through the photo mask, etching the etch mask using the photo mask, removing the photo mask, and forming a metal material over the first material layer, to fill the via hole. Accordingly, it is possible to prevent formation of a side wall undercut in a deep via etching process, and thus to ease subsequent processes for forming an oxide barrier film, a barrier metal film, and a metal layer.

Abstract: In deposited silicon, n-type dopants such as phosphorus and arsenic tend to seek the surface of the silicon, rising as the layer is deposited. When a second undoped or p-doped silicon layer is deposited on n-doped silicon with no n-type dopant provided, a first thickness of this second silicon layer nonetheless tends to include unwanted n-type dopant which has diffused up from lower levels. This surface-seeking behavior diminishes when germanium is alloyed with the silicon. In some devices, it may not be advantageous for the second layer to have significant germanium content. In the present invention, a first heavily n-doped semiconductor layer (preferably at least 10 at % germanium) is deposited, followed by a silicon-germanium capping layer with little or no n-type dopant, followed by a layer with little or no n-type dopant and less than 10 at % germanium. The germanium in the first layer and the capping layer minimizes diffusion of n-type dopant into the germanium-poor layer above.

Abstract: A method of forming a semiconductor device having an active area and a termination area surrounding the active area comprises providing a semiconductor substrate, providing a semiconductor layer of a first conductivity type over the semiconductor substrate and forming a mask layer over the semiconductor layer. The mask layer outlines at least two portions of a surface of the semiconductor layer: a first outlined portion outlining a floating region in the active area and a second outlined portion outlining a termination region in the termination area. Semiconductor material of a second conductivity type is provided to the first and second outlined portions so as to provide a floating region of the second conductivity type buried in the semiconductor layer in the active area and a first termination region of the second conductivity type buried in the semiconductor layer in the termination area of the semiconductor device.

Abstract: A process for conformally doping through the vertical and horizontal surfaces of a 3-dimensional vertical transistor in a semiconductor-on-insulator structure employs an RF oscillating torroidal plasma current to perform either conformal ion implantation, or conformal deposition of a dopant-containing film which can then be heated to drive the dopants into the transistor. Some embodiments employ both conformal ion implantation and conformal deposition of dopant containing films, and in those embodiments in which the dopant containing film is a pure dopant, the ion implantation and film deposition can be performed simultaneously.

Abstract: Impurity ions are implanted into a semiconductor wafer of which a capacitor insulting film is formed on a principal face. In this impurity ion implantation step, the impurity ions are implanted into the semiconductor wafer in the form of a pulsed beam that repeats ON-OFF operation intermittently.

Abstract: In a dopant-injecting method for injecting a volatile dopant into a semiconductor melt, a doping device having an accommodating portion for accommodating a solid dopant and a cylindrical portion into which a gas ejected from the accommodating portion is introduced, a lower end surface of the cylindrical portion being opened to guide the gas to the melt, is used. The sublimation rate of the dopant in the accommodating portion is set in a range from 10 g/min to 50 g/min. Since a flow volume of the volatilized dopant gas is controlled by setting the sublimation rate of the dopant gas in the accommodating portion in the range from 10 g/min to 50 g/min, the melt is not blown off when the gas is blown onto the melt.

Abstract: A semiconductor device includes an SCR ESD device region disposed within a semiconductor body, and a plurality of first device regions of the first conductivity type disposed on a second device region of the second conductivity type, where the second conductivity type is opposite the first conductivity type. Also included is a plurality of third device regions having a sub-region of the first conductivity type and a sub-region of the second conductivity type disposed on the second device region. The first regions and second regions are distributed such that the third regions are not directly adjacent to each other. A fourth device region of the first conductivity type adjacent to the second device region and a fifth device region of the second conductivity type disposed within the fourth device region are also included.

Abstract: A CMOS image sensor and a manufacturing method are disclosed. The gates of the transistors are formed in the active region of the unit pixel, and a diffusion region for the photo diode is defined by an ion implantation of impurities to the semiconductor substrate. The patterns of the photoresist that are the masking layer against ion implantation are formed on the semiconductor substrate in such a manner that they have the boundary portion of the isolation layer so as not to make the boundary of the defined photo diode contact with the boundary of the isolation layer. Damages by an ion implantation of impurities at the boundary portion between the diffusion region for the photo diode and the isolation layer are prevented, which reduces dark current of the COMS image sensor.

Abstract: The semiconductor substrate includes a high-ohmic semiconductor material with a conduction band edge and a valence band edge, separated by a bandgap, wherein the semiconductor material includes acceptor or donor impurity atoms or crystal defects, whose energy levels are located at least 120 meV from the conduction band edge, as well as from the valence band edge in the bandgap; and wherein the concentration of the impurity atoms or crystal defects is larger than 1×1012 cm?3.

Abstract: A method for fabricating a semiconductor device is presented. The method includes providing a substrate and forming a gate stack over the substrate. A first laser processing to form vacancy rich regions within the substrate on opposing sides of the gate stack is performed. The vacancy rich regions have a first depth from a surface of the substrate. A first implant causing end of range defect regions to be formed on opposing sides of the gate stack at a second depth from the surface of the substrate is also carried out, wherein the first depth is proximate to the second depth.

Abstract: A method for manufacturing an SOI substrate superior in film thickness uniformity and resistivity uniformity in a substrate surface of a silicon layer having a film thickness reduced by an etch-back method is provided. After B ions is implanted into a front surface of a single-crystal Si substrate 10 to form a high-concentration boron added p layer 11 having a depth L in the outermost front surface, the single-crystal Si substrate 10 is appressed against a quartz substrate 20 to be bonded at a room temperature. Chemical etching is performed with respect to the single-crystal Si substrate 10 from a back surface thereof to set its thickness to L or below. A heat treatment is carried out with respect to an SOI substrate in a hydrogen containing atmosphere to outwardly diffuse B from the high-concentration boron added p layer 11, thereby acquiring a boron added p layer 12 having a desired resistance value.

Abstract: One embodiment of the invention provides a semiconductor diode device including a first conductivity type region, a second conductivity type region, where the second conductivity type is different from the first conductivity type, an intrinsic region located between the first conductivity type region and the second conductivity type region; a first halo region of the first conductivity type located between the second conductivity type region and the intrinsic region, and optionally a second halo region of the second conductivity type located between the first conductivity type region and the intrinsic region.

Abstract: A method of forming a vertical MOSFET device includes forming a trench within a drift layer substrate, the drift layer comprising a first polarity type, the trench generally defining a well region of a second polarity type opposite the first polarity type. An ohmic contact layer is formed within a bottom surface of the trench, the ohmic contact layer comprising a material of the second polarity type. A layer of the second polarity type is epitaxially grown over the drift layer, sidewall surfaces of the trench, and the ohmic contact layer. A layer of the first polarity type is epitaxially grown over the epitaxially grown layer of the second polarity type so as to refill the trench, and the epitaxially grown layers of the first and second polarity type are planarized so as to expose an upper surface of the drift layer substrate.

Abstract: In a semiconductor device using a SiC substrate, a Junction Termination Edge (JTE) layer is hardly affected by fixed charge so that a stable dielectric strength is obtained. A semiconductor device according to a first aspect of the present invention includes a SiC epi-layer having n type conductivity, an impurity region in a surface of the SiC epi-layer and having p type conductivity, and JTE layers adjacent to the impurity region, having p type conductivity, and having a lower impurity concentration than the impurity region. The JTE layers are spaced by a distance from an upper surface of the SiC epi-layer, and SiC regions having n type conductivity are present on the JTE layers.

Abstract: An integrated circuit including an array of low resistive vertical diodes and method. One embodiment provides an array of diodes at least partially formed in a substrate for selecting one of a plurality of memory cells. A diode is coupled to a word line. The word line includes a straight-lined portion and protrusions. The diode includes an active area located between two adjacent protrusions.

Abstract: A method for forming a diffused, doped backside layer on a device wafer oxide bonded to a handle wafer in an integrated circuit is provided. The method comprises forming a thermal bond oxide layer on a backside surface of the device wafer of the integrated circuit. Implanting the bond oxide with a diffusing dopant. Diffusing dopant from the bond oxide into the backside surface of the device wafer. Depositing an oxide layer on the bond oxide and bonding the deposited oxide layer to the handle wafer of the integrated circuit.

Abstract: A nonvolatile semiconductor memory device is provided in such a manner that a semiconductor layer is formed over a substrate, a charge accumulating layer is formed over the semiconductor layer with a first insulating layer interposed therebetween, and a gate electrode is provided over the charge accumulating layer with a second insulating layer interposed therebetween. The semiconductor layer includes a channel formation region provided in a region overlapping with the gate electrode, a first impurity region for forming a source region or drain region, which is provided to be adjacent to the channel formation region, and a second impurity region provided to be adjacent to the channel formation region and the first impurity region. A conductivity type of the first impurity region is different from that of the second impurity region.

Abstract: A MOS transistor, and a method for producing the same, is provided with a source region, a gate-region, a drain region, and a drift region in an SOI wafer. The SOI-wafer has a carrier layer, which carries an insulating intermediate layer, and whereby the insulating intermediate layer carries an active semiconductor layer, in which laterally different doping material concentrations define the source region, the drift region, and the drain region. Whereby, the active semiconductor layer, at least in a portion of the drift region, is thicker than in the source region. The MOS transistor is characterized in that the active semiconductor layer, in a vertical direction, is completely separated by the insulating intermediate layer from the carrier layer.

Abstract: To achieve a further reduction in the size of a finished product by reducing the number of externally embedded parts, the embedding of a Schottky barrier diode which is relatively large in the amount of current in a semiconductor integrated circuit device has been pursued. In such a case, it is general practice to densely arrange a large number of contact electrodes in a matrix over a Schottky junction region. It has been widely performed to perform a sputter etching process with respect to the surface of a silicide layer at the bottom of each contact hole before a barrier metal layer is deposited. However, in a structure in which electrodes are thus arranged over a Schottky junction region, a reverse leakage current in a Schottky barrier diode is varied by variations in the amount of sputter etching. The present invention is a semiconductor integrated circuit device having a Schottky barrier diode in which contact electrodes are arranged over a guard ring in contact with a peripheral isolation region.