Abstract: A photodetector includes a semiconductor substrate having first and second main surfaces opposite to each other. The photodetector includes at least one trench formed in the first main surface and a first anode/cathode region having a first conductivity formed proximate the first main surface and sidewalls of the at least one trench. The photodetector includes a second anode/cathode region proximate the second main surface. The second anode/cathode region has a second conductivity opposite the first conductivity. The at least one trench extends to the second main surface of the semiconductor substrate.

Abstract: In a calibration method, the relation between dopant concentrations of ?-doping layers in a multilayered semiconductor structure and process parameters is determined S1 based on multiple bulk specimens of the material in which the ?-doping layers are located. A desired dopant concentration is selected S2, and the semiconductor structure with predetermined doping levels can be generated S3 based on the relation between the process parameters and the predetermined doping concentrations.

Abstract: To provide an impurity introducing method which can repeatedly carry out such a process that plasma irradiation for realization of amorphous and plasma doping were combined, in such a situation that steps are simple and through-put is high, without destroying an apparatus. At the time of switching over plasmas which are used in plasma irradiation for realization of amorphous and plasma doping, electric discharge is stopped, and an initial condition of a matching point of a high frequency power supply and a peripheral circuit is reset so as to adapt to plasma which is used in each step, or at the time of switching, a load, which is applied to the high frequency power supply etc., is reduced by increasing pressure and decreasing a bias voltage.

Abstract: An structure for electrically isolating a semiconductor device is formed by implanting dopant into a semiconductor substrate that does not include an epitaxial layer. Following the implant the structure is exposed to a very limited thermal budget so that dopant does not diffuse significantly. As a result, the dimensions of the isolation structure are limited and defined, thereby allowing a higher packing density than obtainable using conventional processes which include the growth of an epitaxial layer and diffusion of the dopants. In one group of embodiments, the isolation structure includes a deep layer and a sidewall and which together form a cup-shaped structure surrounding an enclosed region in which the isolated semiconductor device may be formed. The sidewalls may be formed by a series of pulsed implants at different energies, thereby creating a stack of overlapping implanted regions.

Abstract: Methods of manufacturing a semiconductor device including a high-voltage device region and a low-voltage device region are provided. An illustrated method includes forming, on a substrate, a gate pattern for a high-voltage device and a low-voltage device; implanting ions into opposite sides of the gate pattern, to form a lightly doped drain structure while implanting ions into a portion of the high-voltage device region under the same conditions as the low-voltage device region to form an electrostatic discharge protecting device region; forming a spacer at the side surface of the gate pattern; forming a source region and a drain source at field regions disposed at the opposite sides of the gate pattern, respectively; and forming a metal layer on the front surface of the substrate including the gate pattern.

Abstract: A power device includes a gate electrode, a source electrode, and a drain electrode provided within an active region of a semiconductor substrate of first conductivity type. A vertical diffusion region of second conductivity is provided at a periphery the active region. The vertical diffusion region extends continuously from a top surface of the substrate to a bottom surface of the substrate. The vertical diffusion region includes an upper portion having a first depth and a lower portion having a second depth that is substantially greater than the first depth.

Abstract: A method for manufacturing a semiconductor device that comprises implanting a first dopant type in a well region of a substrate to form implanted sub-regions that are separated by non-implanted areas of the well region. The method also comprises forming an oxide layer over the well region, such that an oxide-converted first thickness of the implanted sub-regions is greater than an oxide-converted second thickness of the non-implanted areas. The method further comprises removing the oxide layer to form a topography feature on the well region. The topography feature comprises a surface pattern of higher and lower portions. The higher portions correspond to locations of the non-implanted areas and the lower portions correspond to the implanted sub-regions.

Abstract: A method for performing a bit line implant is disclosed. The method includes forming a group of structures on an oxide-nitride-oxide stack of a semiconductor device. Each structure of the group of structures includes a polysilicon portion and a hard mask portion. A first structure of the group of structures is separated from a second structure of the group of structures by less than 100 nanometers. The method further includes using the first structure and the second structure to isolate a portion of the semiconductor device for the bit line implant.

Abstract: A combination of a dry oxidizing, wet etching, and wet cleaning processes are used to remove particle defects from a wafer after ion implantation, as part of a wafer bonding process to fabricate a SOI wafer. The particle defects on the topside and the backside of the wafer are oxidized, in a dry strip chamber, with an energized gas. In a wet clean chamber, the backside of the wafer is treated with an etchant solution to remove completely or partially a thermal silicon oxide layer, followed by exposure of the topside and the backside to a cleaning solution. The cleaning solution contains ammonium hydroxide, hydrogen peroxide, DI water, and optionally a chelating agent, and a surfactant. The wet clean chamber is integrated with the dry strip chamber and contained in a single wafer processing system.

Abstract: A barrier implanted region of a first conductivity type formed in lieu of an isolation region of a pixel sensor cell that provides physical and electrical isolation of photosensitive elements of adjacent pixel sensor cells of a CMOS imager. The barrier implanted region comprises a first region having a first width and a second region having a second width greater than the first width, the second region being located below the first region. The first region is laterally spaced from doped regions of a second conductivity type of adjacent photodiodes of pixel sensor cells of a CMOS imager.

Abstract: By removing an outer spacer of a transistor element, used for the formation of highly complex lateral dopant profiles, prior to the formation of metal silicide, employing a wet chemical etch process, it is possible to position a stressed contact liner layer more closely to the channel region, thereby allowing a highly efficient stress transfer mechanism for creating a corresponding strain in the channel region, without affecting circuit elements in the P-type regions.

Abstract: A method of multi-step plasma doping a substrate includes igniting a plasma from a process gas. A first plasma condition is established for performing a first plasma doping step. The substrate is biased so that ions in the plasma having the first plasma condition impact a surface of the substrate thereby exposing the substrate to a first dose. The first plasma condition transitions to a second plasma condition. The substrate is biased so that ions in the plasma having the second plasma condition impact the surface of the substrate thereby exposing the substrate to a second dose. The first and second plasma conditions are chosen so that the first and second doses combine to achieve a predetermined distribution of dose across at least a portion of the substrate.

Abstract: Method of forming one or more doped regions in a semiconductor substrate and semiconductor junctions formed thereby, using gas cluster ion beams.

Abstract: An N-channel device (40, 60) is described having a lightly doped substrate (42, 42?) in which adjacent or spaced-apart P (46, 46?) and N (44) wells are provided. A lateral isolation wall (76) surrounds at least a portion of the substrate (42, 42?) and is spaced apart from the wells (46, 46?, 44). A first gate (G1) (56) overlies the P (46) well or the substrate (42?) between the wells (46?, 44) or partly both. A second gate (G2) (66), spaced apart from G1 (56), overlies the N-well (44). A body contact (74) to the substrate (42, 42?) is spaced apart from the isolation wall (76) by a first distance (745) within the space charge region of the substrate (42, 42?) to isolation wall (76) PN junction. When the body contact (74) is connected to G2 (66), a predetermined static bias Vg2 is provided to G2 (66) depending upon the isolation wall bias (Vbias) and the first distance (745). The resulting device (40, 60) operates at higher voltage with lower Rdson and less HCI.

Abstract: The present invention is to carry out stable doping and to prevent the drastic pressure change in a treatment chamber by reducing degasification of resist during adding impurities. In the present invention, the stability of the impurity ion injection can be ensured by reducing degasification of resist by reducing the area (resist area proportion, that is, the ratio of the area of resist to the whole area of a substrate) of resist pattern which is used depending on the conditions such as acceleration voltage or current density of a doping process.

Abstract: Methods of forming a strained Si-containing hybrid substrate are provided as well as the strained Si-containing hybrid substrate formed by the methods. In the methods of the present invention, a strained Si layer is formed overlying a regrown semiconductor material, a second semiconducting layer, or both. In accordance with the present invention, the strained Si layer has the same crystallographic orientation as either the regrown semiconductor layer or the second semiconducting layer. The methods provide a hybrid substrate in which at least one of the device layers includes strained Si.

Abstract: A process for manufacturing an interaction system of a microelectromechanical type for a storage medium, the interaction system provided with a supporting element and an interaction element carried by the supporting element, envisages the steps of: providing a wafer of semiconductor material having a substrate with a first type of conductivity (P) and a top surface; forming a first interaction region having a second type of conductivity (N), opposite to the first type of conductivity (P), in a surface portion of the substrate in the proximity of the top surface; and carrying out an electrochemical etch of the substrate starting from the top surface, the etching being selective with respect to the second type of conductivity (N), so as to remove the surface portion of the substrate and separate the first interaction region from the substrate, thus forming the supporting element.

Abstract: A technique for boron implantation is disclosed. In one particular exemplary embodiment, the technique may be realized by an apparatus for boron implantation. The apparatus may comprise a reaction chamber. The apparatus may also comprise a source of pentaborane coupled to the reaction chamber, wherein the source is capable of supplying a substantially pure form of pentaborane into the reaction chamber. The apparatus may further comprise a power supply that is configured to energize the pentaborane in the reaction chamber sufficiently to produce a plasma discharge having boron-bearing ions.

Abstract: A method that allows for uniform, simultaneous epitaxial growth of a semiconductor material on dissimilarly doped semiconductor surfaces (n-type and p-type) that does not impart substrate thinning via a novel surface preparation scheme, as well as a structure that results from the implementation of this scheme into the process integration flow for integrated circuitry are provided. The method of the present invention can by used for the selective or nonselective epitaxial growth of semiconductor material from the dissimilar surfaces.

Abstract: Techniques for reducing contamination during ion implantation is disclosed. In one particular exemplary embodiment, the techniques may be realized by an apparatus for reducing contamination during ion implantation. The apparatus may comprise a platen to hold a workpiece for ion implantation by an ion beam. The apparatus may also comprise a mask, located in front of the platen, to block the ion beam and at least a portion of contamination ions from reaching a first portion of the workpiece during ion implantation of a second portion of the workpiece. The apparatus may further comprise a control mechanism, coupled to the platen, to reposition the workpiece to expose the first portion of the workpiece for ion implantation.

Abstract: One aspect is a semiconductor component including a terminal zone; a drift zone of a first conduction type, which is doped more weakly than the terminal zone; a component junction between the drift zone and a further component zone; and a charge carrier compensation zone of the first conduction type, which is arranged between the drift zone and the terminal zone and whose doping concentration is lower than that of the terminal zone, and whose doping concentration increases at least in sections in the direction of the terminal zone from a minimum doping concentration to a maximum doping concentration, the minimum doping concentration being more than 1016 cm?3.

Abstract: A vertical TVS (VTVS) circuit includes a semiconductor substrate for supporting the VTVS device thereon having a heavily doped layer extending to the bottom of substrate. Deep trenches are provided for isolation between multi-channel VTVS. Trench gates are also provided for increasing the capacitance of VTVS with integrated EMI filter.

Abstract: Methods and apparatus are provided for semiconductor device (60, 95, 100, 106). The semiconductor device (60, 95, 100, 106), comprises a first region (64, 70) of a first conductivity type extending to a first surface (80), a second region (66) of a second, opposite, conductivity type forming with the first region (70) a first PN junction (65) extending to the first surface (80), a contact region (68) of the second conductivity type in the second region (66) at the first surface (80) and spaced apart from the first PN junction (65) by a first distance (LDS), and a third region (82, 96-98, 108) of the first conductivity type and of a second length (LBR), underlying the second region (66) and forming a second PN junction (63) therewith spaced apart from the first surface (80) and located closer to the first PN junction (65) than to the contact region (68). The breakdown voltage is enhanced without degrading other useful properties of the device (60, 95, 100, 106).

Abstract: The present invention provides a method for manufacturing a transistor device, and a method for manufacturing an integrated circuit including the same. The method for manufacturing the transistor device, among other elements, includes forming a gate structure over a substrate, implanting an atom selected from the group consisting of fluorine, silicon, or germanium into the substrate proximate the gate structure to cause at least a portion of the substrate to be in a sub-amorphous state, and implanting a dopant into the substrate having the implanted atom therein, thereby forming source/drain regions in the substrate, wherein the transistor device does not have a halo/pocket implant.

Abstract: A method for activating the P-type semiconductor layer of a semiconductor device is disclosed in this present invention. The above-mentioned method can activate the impurities in the P-type semiconductor layer of a semiconductor device by plasma. The plasma comprises a gas source including a VI Group compound element. The performance of the semiconductor device activated by plasma according to this invention is similar to the performance of the semiconductor device activated by heat in the prior art. Therefore, this invention can provide a method, other then heat, for activating the P-type semiconductor layer of a semiconductor device. Moreover, in this invention, during the activating process by plasma, the layers other than P-type semiconductor layer will not be affected by plasma. That is, the activating process according to this invention will not cause any side-reactions in the layers other than the P-type semiconductor layer of a semiconductor device.

Abstract: Certain aspects of a method for reducing noise disturbing at least one signal in an electronic device may comprise shielding a first layer doped with a first dopant from a signaling layer employing a second layer doped with a second dopant. A first signaling component of the signaling layer may be coupled to the second layer and a second signaling component of the signaling layer may be coupled to the second layer. The second layer may be coupled to the first layer, and this reduces the signal disturbing noise in the electronic device. Shielding the first layer from the signaling layer may comprise disposing the second layer between the first layer and the signaling layer. Shielding the first layer from the signaling layer may comprise disposing a deep N-well between the first layer and the signaling layer.

Abstract: A plasma doping method, even though a plasma doping treatment is repeated, can make a dose from a film to a silicon substrate uniform for each time. The method includes preparing a vacuum chamber having a film containing an impurity formed on an inner wall thereof such that, when the film is attacked by ions in plasma, the amount of an impurity to be doped into the surface of a sample by sputtering is not changed even though the plasma containing the impurity ions is repeatedly generated in the vacuum chamber; placing the sample on the sample electrode; and irradiating the plasma containing the impurity ions so as to implant the impurity ions into the sample, and doping the impurity into the sample by sputtering from the film containing the impurity fixed to the inner wall of the vacuum chamber.

Abstract: This invention is generally concerned with power semiconductors such as power MOS transistors, insulated gate by bipolar transistors (IGBTs), high voltage diodes and the like, and method for their fabrication. A power semiconductor, the semiconductor comprising a power device, said power device having first and second electrical contact regions and a drift region extending therebetween; and a semiconductor substrate mounting said device; and wherein said power semiconductor includes an electrically insulating layer between said semiconductor substrate and said power device, said electrically insulating layer having a thickness of at least 5 ?m.

Abstract: By removing an outer spacer, used for the formation of highly complex lateral dopant profiles, prior to the formation of metal silicide, a high degree of process compatibility with conventional processes is obtained, while at the same time a contact liner layer may be positioned more closely to the channel region, thereby allowing a highly efficient stress transfer mechanism for creating a corresponding strain in the channel region.

Abstract: A plasma enhanced physical vapor deposition process deposits an amorphous carbon layer on an ion-implanted wafer for use in dynamic surface annealing of the wafer with an intense line beam of a laser wavelength. The deposition process is carried out at a wafer temperature below the dopant clustering threshold temperature, and includes introducing the wafer into a chamber and furnishing a hydrocarbon process gas into the chamber, preferably propylene (C3H6) or toluene (C7H8) or acetylene (C2H2) or a mixture of acetylene and methane (C2H4). The process further includes inductively coupling RF plasma source power into the chamber while and applying RF plasma bias power to the wafer. The wafer bias voltage is set to a level at which the amorphous carbon layer that is deposited has a desired stress (compressive or tensile). We have discovered that at a wafer temperature less than or equal to 475 degrees C.

Abstract: A semiconductor device having small electrical contacts to impurity doped regions and a method for fabrication of such a device are provided. In accordance with one embodiment of the invention the semiconductor device comprises a semiconductor substrate having a doped region formed therein. The doped region has a nucleating layer comprising nickel on its surface, and a nanowire structure comprising silicon and carbon electrically contacts the nucleating layer.

Abstract: A method for producing a semiconductor structure by conducting controlled co-implanting of at least first and second different atomic species into a donor substrate to create an embrittlement zone which defines a thin layer of donor material to be transferred. Implantation energies are selected so that the first and second species are respectively distributed in the donor wafer according to a repartition profile that presents a spreading zone in which each species is mainly distributed at a maximum concentration peak. The implantation doses and energies of the first and second species are selected such that the second species is implanted deeper in the embrittlement zone than the first species spreading zone. The donor substrate is detached at the embrittlement zone to transfer the thin layer to the support substrate while minimizing blister formation in and surface roughness of the transferred layer.

Abstract: Consistent with an example embodiment, a method of manufacturing a semiconductor device comprises MOS transistors having gate electrodes formed in a number of metal layers deposited upon one another. Active silicon regions having a layer of a gate dielectric and field-isolation regions insulating these regions from each other are formed in a silicon body. Then, a layer of a first metal is deposited in which locally, in a part of the active regions, nitrogen is introduced. On the layer of the first metal, a layer of a second metal is then deposited, after which the gate electrodes are etched in the metal layers. Before nitrogen is introduced into the first metal layer, an auxiliary layer of a third metal permeable to nitrogen is deposited an the first metal layer. Thus, the first metal layer can be nitrided locally without the risk of damaging the underlying gate dielectric.

Abstract: A method for manufacturing a semiconductor device includes the consecutive steps of selectively implanting first-conductivity-type impurities into a silicon substrate in a memory cell array area to form first source/drain regions, heat treating to diffuse the impurities in the first source/din regions; selectively implanting impurities into the silicon substrate in a peripheral circuit area to form second source/drain regions in the peripheral circuit area.

Abstract: A method of manufacturing a semiconductor device includes forming a trench having sidewalls on a semiconductor substrate, the sidewalls of the trench defining a side surface of the substrate. A first impurity implanting process is performed on the trench to define a first impurity region of the substrate, the first impurity region extending a first depth into the substrate from the side surface of the substrate. An oxide layer is formed on the trench, the oxide layer covering the side surface of the substrate. A second impurity implanting process is performed on the trench via the oxide layer to define a second impurity region of the substrate that extends a second depth into the substrate from the side surface of the substrate. The trench is filled to form an isolation structure therein to define an active region. The first impurity region extends further into the substrate than the second impurity region.

Abstract: In a method for producing a semiconductor structure a semiconductor a substrate with a top surface is provided. A gate dielectric layer is provided on the top surface and on the gate dielectric layer is provided a memory cell array region with a first plurality of gate stacks and a peripheral element region with a second plurality of gate stacks. A dielectric layer is provided over the memory cell array region and the peripheral element region. A first source/drain implantation over the memory cell array region and the peripheral element region is carried out, a blocking mask over the memory cell array region is formed, the dielectric layer is removed using the blocking mask, and a second source/drain implantation over the memory cell array region and the peripheral element region is carried out, wherein the memory cell array region is protected by a mask.

Abstract: A method for reducing the effective thickness of a gate oxide using nitrogen implantation and anneal subsequent to dopant implantation and activation is provided. More particularly, the present invention provides a method for fabricating semiconductor devices, for example, transistors, which include a hardened gate oxide and which may be characterized by a relatively large nitrogen concentration at the polysilicon/gate oxide interface and a relatively small nitrogen concentration within the gate oxide and at the gate oxide/substrate interface. Additionally, the present invention provides a method for fabricating a semiconductor device having a metal gate strap (e.g., a metal silicide layer) disposed over the polysilicon layer thereof, which device includes a hardened gate oxide and which may be characterized by a relatively large nitrogen concentration at the silicide/polysilicon interface to substantially prevent cross-diffusion.

Abstract: A semiconductor structure and method that is capable of generating a local mechanical gate stress for channel mobility modification are provided. The semiconductor structure includes at least one NFET and at least one PFET on a surface of a semiconductor substrate. The at least one NFET has a gate stack structure comprising a gate dielectric, a first gate electrode layer, a barrier layer, a Si-containing second gate electrode layer and a compressive metal, and the at least one PFET has a gate stack structure comprising a gate dielectric, a first gate electrode layer, a barrier layer and a tensile metal or a silicide.

Abstract: A method of depositing a carbon layer on a workpiece includes placing the workpiece in a reactor chamber, introducing a carbon-containing process gas into the chamber, generating a reentrant toroidal RF plasma current in a reentrant path that includes a process zone overlying the workpiece by coupling plasma RF source power to an external portion of the reentrant path, and coupling RF plasma bias power or bias voltage to the workpiece.

Abstract: An improved layout pattern for electrostatic discharge protection is disclosed. A first heavily doped region of a first type is formed in a well of said first type. A second heavily doped region of a second type is formed in a well of said second type. A battlement layout pattern of said first heavily doped region is formed along the boundary of said first heavily doped region and said second heavily doped region. A battlement layout pattern of said second heavily doped region is formed along the boundary of said first heavily doped region and said second heavily doped region. By adjusting a distance between the battlement layout pattern of a heavily doped region and a edge of well of said second type, i.e. n-well, a first distance will be shorter than what is typically required by the layout rules of internal circuit; and a second distance will be longer than the first distance to ensure that the I/O device have a better ESD protection capability.

Abstract: The present invention pertains to a high-voltage MOS device. The high-voltage MOS device includes a substrate, a first well, a first field oxide layer enclosing a drain region, a second field oxide enclosing a source region, and a third field oxide layer encompassing the first and second field layers with a device isolation region in between. A channel region is situated between the first and second field oxide layers. A gate oxide layer is provided on the channel region. A gate is stacked on the gate oxide layer. A device isolation diffusion layer is provided in the device isolation region.

Abstract: A method and system for integrated circuit (IC) processing combines an ion implantation tool and a laser anneal tool in a single unit with a shared precision X-Y scanner. A semiconductor wafer is loaded onto a the X-Y table of the scanner. Data defining the desired ion implantation is used to first customize circuit areas on the semiconductor wafer by gating ON and OFF the ion beam while semiconductor wafer is scanned. Any inadvertent ion beam interruptions are noted by storing the locations of the interruptions. The wafer is then reprocessed to correct faults caused by the interruptions. The laser anneal tool positions the laser beam over the semiconductor wafer it is then scanned while gating the laser beam ON and OFF to custom anneal the wafer devices. Again, any inadvertent laser beam interruptions are detected and the locations of the interruptions are stored for reprocessing to correct faults.

Abstract: A method of ion implanting a species in a workpiece to a selected ion implantation profile depth includes placing a workpiece having a semiconductor material on an electrostatic chuck in or near a processing region of a plasma reactor chamber and applying a chucking voltage to the electrostatic chuck. The method further includes introducing into the chamber a precursor gas including a species to be ion implanted in the workpiece and applying an RF bias to the electrostatic chuck, the RF bias having a bias level corresponding to the ion implantation profile depth.

Abstract: A bolt includes a main body and a spring pin. The main body includes a head and a shaft. The spring pin includes a base portion and an end portion. The shaft includes a portion of external thread and a hollow portion. The head includes a top surface and a hole opened in the top surface. The hole is connected to the hollow portion. The base portion is arranged in the hollow potion to move along an axis of the main body. The end portion is arranged in the hole to move along the axis. The spring pin is energized toward a side of the head such that the end portion protrudes beyond the top surface. The end portion is electrically connected to the portion of external thread.

Abstract: An structure for electrically isolating a semiconductor device is formed by implanting dopant into a semiconductor substrate that does not include an epitaxial layer. Following the implant the structure is exposed to a very limited thermal budget so that dopant does not diffuse significantly. As a result, the dimensions of the isolation structure are limited and defined, thereby allowing a higher packing density than obtainable using conventional processes which include the growth of an epitaxial layer and diffusion of the dopants. In one group of embodiments, the isolation structure includes a deep layer and a sidewall which together form a cup-shaped structure surrounding an enclosed region in which the isolated semiconductor device may be formed. The sidewalls may be formed by a series of pulsed implants at different energies, thereby creating a stack of overlapping implanted regions.

Abstract: A programmable dopant fiber includes a plurality of quantum structures formed on a fiber-shaped substrate, wherein the substrate includes one or more energy-carrying control paths, which pass energy to quantum structures. Quantum structures may include quantum dot particles on the surface of the fiber or electrodes on top of barrier layers and a transport layer, which form quantum dot devices. The energy passing through the control paths drives charge carriers into the quantum dots, leading to the formation of “artificial atoms” with real-time, tunable properties. These artificial atoms then serve as programmable dopants, which alter the behavior of surrounding materials. The fiber can be used as a programmable dopant inside bulk materials, as a building block for new materials with unique properties, or as a substitute for quantum dots or quantum wires in certain applications.

Abstract: A method of implanting a zinc (Zn)-ion into a nitride-based semiconductor substrate, the method includes: providing a homogeneous substrate on which a gallium nitride layer is grown; placing the homogeneous substrate in a crucible in which gallium nitride powders are coated; placing the crucible into a furnace; and performing a heat treatment process, so that a Zn-ion implantation is performed under an ammoniacal atmosphere in the furnace. The method of implanting a Zn-ion into a nitride-based semiconductor substrate, which can minimize a decomposition of a gallium nitride layer during a heat treatment process at a high temperature, easily produce a p-type, and reduce contact resistance between a semiconductor and a metal electrode, is provided.

Abstract: The present invention is directed to systems and methods for nanowire growth and harvesting. In an embodiment, methods for nanowire growth and doping are provided, including methods for epitaxial oriented nanowire growth using a combination of silicon precursors. In a further aspect of the invention, methods to improve nanowire quality through the use of sacrifical growth layers are provided. In another aspect of the invention, methods for transferring nanowires from one substrate to another substrate are provided.

Abstract: A method for fabricating a semiconductor device improves off-state leakage current and junction capacitance characteristics in a pMOS transistor. The method includes forming a device isolation layer defining an active area in a semiconductor substrate; and forming a channel ion implantation layer by an implantation of arsenic ions in a predetermined region of the active area of the semiconductor substrate at a predetermined density, the channel ion implantation layer having a predetermined doping profile according to the predetermined density of arsenic ion implantation. The implantation may be a low-density implantation of 1.0×1012˜1.5×1013atoms/cm2 performed at an energy level of 10˜100keV.

Abstract: A method of manufacturing a microelectronic device including forming an opening in a dielectric layer located over a substrate, forming a semi-conductive layer substantially conforming to the opening, and forming a conductive layer substantially conforming to the semi-conductive layer. At least a portion of the semi-conductive layer is doped by implanting through the conductive layer. The semi-conductive layer and the conductive layer may then be annealed.