Abstract: A method includes forming through vias in a substrate of an array. Nubs of the through vias are exposed from a backside surface of the substrate. A backside passivation layer is applied to enclose the nubs. Laser-ablated artifacts are formed in the backside passivation layer to expose the nubs. Circuit features are formed within the laser-ablated artifacts. By forming the circuit features within the laser-ablated artifacts in the backside passivation layer, the cost of fabricating the array is minimized. More particularly, the number of operations to form the embedded circuit features is minimized thus minimizing fabrication cost of the array.

Abstract: A method of forming openings to a layer of a semiconductor device comprises forming a dielectric layer over the layer of the semiconductor device, and forming a mask over the dielectric layer. The mask comprises a plurality of mask openings arranged in a regular pattern extending over the dielectric layer and the plurality of mask openings include a plurality of first mask openings and a plurality of second mask openings, each of the plurality of first mask openings being greater in size than each of the plurality of second mask openings. The method further comprises reducing the size of the plurality of second mask openings such that each of the second mask openings is substantially closed and removing portions of the dielectric layer through the plurality of first mask openings to provide openings extending through the dielectric layer to the layer.

Abstract: Nanostructure array optoelectronic devices are disclosed. The optoelectronic device may be a multi junction solar cell. The optoelectronic device may have a bi-layer electrical interconnect that is physically and electrically connected to sidewalls of the array of nanostructures. The optoelectronic device may be operated as a multi junction solar cell, wherein each junction is associated with one portion of the device. The bi-layer electrical interconnect allows current to pass from one portion to the next. Thus, the bi-layer electrical interconnect may serve as a replacement for a tunnel junction, which is used in some conventional multi junction solar cells.

Abstract: At least one metal adhesion layer is formed on at least a Cu surface of a first device wafer. A second device wafer having another Cu surface is positioned atop the Cu surface of the first device wafer and on the at least one metal adhesion layer. The first and second device wafers are then bonded together. The bonding includes heating the devices wafers to a temperature of less than 400° C., with or without, application of an external applied pressure. During the heating, the two Cu surfaces are bonded together and the at least one metal adhesion layer gets oxygen atoms from the two Cu surfaces and forms at least one metal oxide bonding layer between the Cu surfaces.

Abstract: A semiconductor memory device having a cell pattern formed on an interconnection and capable of reducing an interconnection resistance and a fabrication method thereof are provided. The semiconductor device includes a semiconductor substrate in which a cell area, a core area, and a peripheral area are defined and a bottom structure is formed, a conductive line formed on an entire structure of the semiconductor substrate, a memory cell pattern formed on the conductive line in the cell area, and a dummy conductive pattern formed on any one of the conductive line in the core area and the peripheral area.

Abstract: Composite films comprising two-dimensional hole arrays, and related methods of preparing hole arrays.

Abstract: There are provided a semiconductor package and a method of manufacturing the same. The semiconductor package includes: a substrate having a ground electrode formed on one surface thereof; at least one electronic component mounted on one surface of the substrate; an insulation layer including an exposed part exposing the ground electrode and a cover part covering the electronic component; and a shielding layer electrically connected to the ground electrode and covering the insulation layer.

Abstract: Some embodiments include methods of forming diodes. A stack may be formed over a first conductive material. The stack may include, in ascending order, a sacrificial material, at least one dielectric material, and a second conductive material. Spacers may be formed along opposing sidewalls of the stack, and then an entirety of the sacrificial material may be removed to leave a gap between the first conductive material and the at least one dielectric material. In some embodiments of forming diodes, a layer may be formed over a first conductive material, with the layer containing supports interspersed in sacrificial material. At least one dielectric material may be formed over the layer, and a second conductive material may be formed over the at least one dielectric material. An entirety of the sacrificial material may then be removed.

Abstract: A semiconductor nanocrystal composite comprising a semiconductor nanocrystal composition dispersed in an inorganic matrix material and a method of making same are provided. The method includes providing a semiconductor nanocrystal composition having a semiconductor nanocrystal core, providing a surfactant formed on the outer surface of the composition, and replacing the surfactant with an inorganic matrix material. The semiconductor nanocrystal composite emits light having wavelengths between about 1 and about 10 microns.

Abstract: A mold having an open interior volume is used to define patterns. The mold has a ceiling, floor and sidewalls that define the interior volume and inhibit deposition. One end of the mold is open and an opposite end has a sidewall that acts as a seed sidewall. A first material is deposited on the seed sidewall. A second material is deposited on the deposited first material. The deposition of the first and second materials is alternated, thereby forming alternating rows of the first and second materials in the interior volume. The mold and seed layer are subsequently selectively removed. In addition, one of the first or second materials is selectively removed, thereby forming a pattern including free-standing rows of the remaining material. The free-standing rows can be utilized as structures in a final product, e.g., an integrated circuit, or can be used as hard mask structures to pattern an underlying substrate. The mold and rows of material can be formed on multiple levels.

Abstract: An integrated circuit is disclosed having symmetric and asymmetric MOS transistors of the same polarity, oriented perpendicularly to each other, formed by concurrent halo ion, LDD ion and/or S/D ion implant processes using angled, rotated sub-implants which vary the tilt angle, dose and/or energy between rotations. Implanted halo, LDD and/or S/D source and drain regions formed by angled subimplants may have different extents of overlap with, or lateral separation from, gates of the two types of transistors, producing transistors with two different sets of electrical properties. A process for concurrently fabricating the two types of transistors is also disclosed. Specific embodiments of processes for concurrently forming symmetric and asymmetric transistors are disclosed.

Abstract: A method of manufacturing a filling of a gap region. The method includes the steps of: applying a carrier fluid and filler particles in a gap region between a first surface and a second surface; exposing the filler particles to a force field for driving the filler particles towards a preferred direction; and withholding the filler particles in a gap region by using a barrier element for forming a path of attached filler particles between the first surface and the second surface.

Abstract: In high frequency circuits, the switching speed of devices is often limited by the series resistance and capacitance across the input terminals. To reduce the resistance and capacitance, the cross-section of input electrodes is made into a T-shape or inverted L-shape through lithography. The prior art method for the formation of cavities for T-gate or inverted L-gate is achieved through several steps using multiple photomasks. Often, two or even three different photoresists with different sensitivity are required. In one embodiment of the present invention, an optical lithography method for the formation of T-gate or inverted L-gate structures using only one photomask is disclosed. In another embodiment, the structure for the T-gate or inverted L-gate is formed using the same type of photoresist material.

Abstract: A method of forming a layer of amorphous silicon oxide positioned between a layer of rare earth oxide and a silicon substrate. The method includes providing a crystalline silicon substrate and depositing a layer of rare earth metal on the silicon substrate in an oxygen deficient ambient at a temperature above approximately 500° C. The rare earth metal forms a layer of rare earth silicide on the substrate. A first layer of rare earth oxide is deposited on the layer of rare earth silicide with a structure and lattice constant substantially similar to the substrate. The structure is annealed in an oxygen ambience to transform the layer of rare earth silicide to a layer of amorphous silicon and an intermediate layer of rare earth oxide between the substrate and the first layer of rare earth oxide.

Abstract: A semiconductor device and fabrication methods are disclosed. The device includes a plurality of gate electrodes formed in trenches located in an active region of a semiconductor substrate. A first gate runner is formed in the substrate and electrically connected to the gate electrodes, wherein the first gate runner surrounds the active region. A second gate runner is connected to the first gate runner and located between the active region and a termination region. A termination structure surrounds the first and second gate runners and the active region. The termination structure includes a conductive material in an insulator-lined trench in the substrate, wherein the termination structure is electrically shorted to a source or body layer of the substrate thereby forming a channel stop for the device.

Abstract: This invention uses surface tension to align a z-axis MEMS sensing device that is mounted onto a substrate or lead frame oriented in an xy-plane. According to the teachings of the present invention, the height of the z-axis sensing device is less than or substantially equal to its width (y-dimension) while the length of the device in the longitudinal direction (x-dimension) is greater than either of the y- or z-dimensions. As a result, instead of being thin and tall like a wall, which configuration is extremely difficult to align vertically, the elongate z-axis sensing device is mounted on a short z-axis, making it easier to align vertically.

Abstract: Example embodiments provide triple-gate semiconductor devices isolated by reverse shallow trench isolation (STI) structures and methods for their manufacture. In an example process, stacked layers including a form layer over a dielectric layer can be formed over a semiconductor substrate. One or more trenches can be formed by etching through the stacked layers. The one or more trenches can be filled by an active area material to form one or more active areas, which can be isolated by remaining portions of the dielectric layer. Bodies of the active area material can be exposed by removing the form layer. One or more triple-gate devices can then be formed on the exposed active area material. The example triple-gate semiconductor devices can control the dimensions for the active areas and provide less isolation spacing between the active areas, which optimizes manufacturing efficiency and device integration quality.

Abstract: A transistor includes: a control electrode; an active layer facing the control electrode; a first electrode and a second electrode electrically connected to the active layer; and an insulating layer provided between the control electrode and the active layer, the insulating layer containing diallyl isophthalate resin.

Abstract: A thermal interface material for use in manufacturing a semiconductor component and a method for manufacturing the semiconductor component. The thermal interface material includes a metallic element in combination with either antimony or tin. Suitable metallic elements include gallium or indium. The concentration of antimony or tin is about 2 percent or less by weight of the thermal interface material. A semiconductor chip is mounted to a support substrate and the thermal interface material is disposed on the semiconductor chip. A lid or a heatsink is coupled to the semiconductor chip via the thermal interface material.

Abstract: Methods of forming multi-tiered semiconductor devices are described, along with apparatuses that include them. In one such method, a silicide is formed in a tier of silicon, the silicide is removed, and a device is formed at least partially in a void that was occupied by the silicide. One such apparatus includes a tier of silicon with a void between tiers of dielectric material. Residual silicide is on the tier of silicon and/or on the tiers of dielectric material and a device is formed at least partially in the void. Additional embodiments are also described.

Abstract: Provided is a method of planarizing a semiconductor device. The method includes providing a substrate. The method includes forming a first layer over the substrate. The method includes forming a second layer over the first layer. The first and second layers have different material compositions. The method includes forming a third layer over the second layer. The method includes performing a polishing process on the third layer until the third layer is substantially removed. The method includes performing an etch back process to remove the second layer and a portion of the first layer. Wherein an etching selectivity of the etch back process with respect to the first and second layers is approximately 1:1.

Abstract: A method for depositing graphene is provided. The method includes depositing a layer of non-conducting amorphous carbon over a surface of a substrate and depositing a transition metal in a pattern over the amorphous carbon. The substrate is annealed at a temperature below 500° C., where the annealing converts the non-conducting amorphous carbon disposed under the transition metal to conducting amorphous carbon. A portion of the pattern of the transition metal is removed from the surface of the substrate to expose the conducting amorphous carbon.

Abstract: The present invention is directed to a flexible backplane for direct drive display devices and methods for its manufacture. The flexible backplane has many advantages. Because there is no need for a polyimide layer and only one layer of metal foil is used, the backplanes may be manufactured at a relatively low cost.

Abstract: A method of processing a microfeature workpiece generally includes depositing a first conducting layer, at least partially reducing oxides on the first conducting layer to provide a reduced first conducting layer, and exposing the reduced first conducting layer to a substantially oxygen-free environment to provide a passivated first conducting layer. A microfeature workpiece generally includes a first conducting layer, a monolayer directly on the first conducting layer, and a second conducting layer.

Abstract: A method is disclosed for forming a patterned thick metallization atop a semiconductor chip wafer. The method includes fabricating a nearly complete semiconductor chip wafer ready for metallization; depositing a bottom metal layer of sub-thickness TK1 together with its built-in alignment mark using a hot metal process; depositing a top metal layer of sub-thickness TK2 using a cold metal process thus forming a stacked thick metallization of total thickness TK=TK1+TK2; then, use the built-in alignment mark as reference, patterning the stacked thick metallization. A patterned thick metallization is thus formed with the advantages of better metal step coverage owing to the superior step coverage nature of the hot metal process as compared to the cold metal process; and lower alignment error rate owing to the lower alignment signal noise nature of the cold metal process as compared to the hot metal process.

Abstract: An alignment mark with a sheet or a layer of copper, which is compatible with a copper process, is provided herein. In one embodiment, a whole sheet of copper (Cu) is used as a background of the alignment mark, by which the color of the background of the alignment mark is stable and reliable. By such arrangement, the contrast between colors of a main pattern and the background of the alignment mark can be significantly improved, without considering a problem the homogeneity of manufacturing process. If the alignment mark is applied for manufacturing of a display, a recognition successful rate of alignment to attach an integrated circuit (IC) to a panel of the display is increased.

Abstract: Embodiments of the invention are directed to a method of printing lines. The method may include depositing material on a substrate from a plurality of nozzles to form a multi-layered line of a desired cross section area or a desired height by dispensing the material in at least two layers in a single scan. Each layer may be printed by different nozzles and the number of layers in the line is determined based on the desired cross section area or height.

Abstract: A method for encapsulating a micro component positioned on and/or in a substrate, including: depositing at least one sacrificial material covering the micro component, making a cap covering the sacrificial material, removing the sacrificial material via at least one opening formed through the cap and forming a cavity in which the micro component is positioned, depositing, at least on the cap, at least one layer of plugging material that plugs the at least one opening, and performing a localized deposition of at least one portion of mechanically reinforcing material of the cap, covering at least the cap, wherein the mechanically reinforcing material is not subsequently etched.

Abstract: Systems and methods for applying a thin layer of a liquid to the surface of a wafer with topography formed therein. The systems and methods include spreading a deposit of the liquid into a thin film on a wafer support, lowering the wafer onto the film, removing the wafer with an adhering layer of the film, positioning the wafer over a device wafer with the liquid film disposed between the wafers, curing the thin layer. The thin layer may be a UV adhesive which bonds the wafers upon exposure to UV light.

Abstract: In a manufacturing method of a semiconductor structure, a substrate having a front surface and a back surface is provided. The front surface has a device layer thereon and conductive plugs electrically connected to the device layer. A thinning process is performed on the back surface of the substrate, such that the back surface of the substrate and surfaces of the conductive plugs have a distance therebetween. Holes are formed in the substrate from the back surface to the conductive plugs, so as to form a porous film. An oxidization process is performed, such that the porous film correspondingly is reacted to form an oxide material layer. A polishing process is performed on the oxide material layer to expose the surfaces of the conductive plugs.

Abstract: Methods of forming ruthenium or ruthenium dioxide are provided. The methods may include using ruthenium tetraoxide (RuO4) as a ruthenium precursor. In some embodiments for forming ruthenium, methods include forming a seed layer, and forming a ruthenium layer on the seed layer, using RuO4. In other embodiments, methods include performing atomic layer deposition cycles, which include using RuO4 and another ruthenium-containing co-precursor. In yet other embodiments, methods include adsorbing a reducing agent over a substrate, and supplying RuO4 to be reduced to ruthenium by the adsorbed reducing agent. In other embodiments for forming ruthenium dioxide, methods may include providing an initial seed layer formed of, for example, an organic compound, and supplying RuO4 over the seed layer.

Abstract: A cap layer for a copper interconnect structure formed in a first dielectric layer is provided. In an embodiment, a conductive layer is located within a dielectric layer and a top surface of the conductive layer has either a recess, a convex surface, or is planar. An alloy layer overlies the conductive layer and is a silicide alloy having a first material from the conductive layer and a second material of germanium, arsenic, tungsten, or gallium.

Abstract: A semiconductor chip (1) is provided having an adhesion-promoting-layer-free three-layer metallization (2). The three-layer metallization (2) has an aluminum layer (4) applied directly on the semiconductor chip (1), a diffusion barrier layer (5) applied directly on the aluminum layer (4), and a solder layer (6) applied directly on the diffusion barrier layer (5). Ti, Ni, Pt or Cr is provided as the diffusion barrier layer (5) and a diffusion solder layer is provided as the solder layer (6). All three layers are applied by sputtering in a process sequence.

Abstract: When using a liquid droplet ejection method, a conventional photomask is not required, however, it is required instead that a moving path of a nozzle or a substrate is controlled with accuracy at least in ejecting liquid droplets. According to the characteristics of compositions to be ejected or their pattern, such ejection conditions are desirably set as the moving rate of a nozzle or a substrate, ejection quantity, ejection distance and ejection rate of compositions, atmosphere of the space that the compositions are ejected, the temperature and moisture of the space, and heating temperature of the substrate.

Abstract: An array of nanowires and method thereof. The array of nanowires includes a plurality of nanowires. The plurality of nanowires includes a plurality of first ends and a plurality of second ends respectively. For each of the plurality of nanowires, a corresponding first end selected from the plurality of first ends and a corresponding second end selected from the plurality of second ends are separated by a distance of at least 200 ?m. All nanowires of the plurality of nanowires are substantially parallel to each other.

Abstract: A method of fabricating a power semiconductor component having a semiconductor body having at least two main surfaces includes applying a layer of a metallization on at least one of the main surfaces. The layer has a thickness of at least 15 ?m and serves as a heat sink. The method also includes producing a field stop zone in the semiconductor body by implantation of protons or helium through the layer.

Abstract: A method of designing a standard cell includes determining a minimum fin pitch of semiconductor fins in the standard cell, wherein the semiconductor fins are portions of FinFETs; and determining a minimum metal pitch of metal lines in a bottom metal layer over the standard cell, wherein the minimum metal pitch is greater than the minimum fin pitch. The standard cell is placed in an integrated circuit and implemented on a semiconductor wafer.

Abstract: A substrate processing apparatus includes a plurality of evacuable treatment chambers connected to one another via an evacuable common chamber, and the common chamber is provided with means for transporting a substrate between each treatment chamber. More specifically, a substrate processing apparatus includes a plurality of evacuable treatment chambers, at least one of said treatment chambers having a film formation function through a vapor phase reaction therein, at least one of said treatment chambers having an annealing function with light irradiation and at least one of said treatment chambers having a heating function therein. The apparatus also has a common chamber through which said plurality of evacuable treatment chambers are connected to one another, and a transportation means provided in said common chamber for transporting a substrate between each treatment chamber.

Abstract: This disclosure relates to a method of forming a gate pattern and a semiconductor device. The gate pattern comprises a plurality of parallel gate bars, and each gate bar is broken up by gaps. The method comprises: making an etching characteristic of a gate material layer at least at positions where the gaps are to be formed different from that at remaining positions; forming a plurality of parallel openings in a second resist layer; performing a first etching process on the gate material layer with the second resist layer as a mask, wherein portions of the gate material layer at least at the positions where the gaps are to be formed are selectively left; and performing a second etching process on the gate material layer so as to selectively remove the portions. This method can more accurately control the shape and size of the gate pattern.

Abstract: Methods for fabricating components with precise dimension control are described. One such method includes providing a workpiece including a top layer and a bottom layer of silicon separated by a layer of SiOx, where each of the three layers has about the same length and width, removing edge portions of the top layer, thereby exposing portions of the SiOx layer, etching the exposed portions of the SiOx layer and portions of the SiOx layer disposed between the top layer and bottom layer, thereby forming undercut sections between the top layer and bottom layer, growing a second layer of SiOx having a preselected thickness on the workpiece, depositing metal on the workpiece such that the metal deposited on the top layer is not continuous with the metal deposited on the bottom layer, and removing the bottom layer and a portion of the SiOx layer having a preselected thickness.

Abstract: A method for manufacturing a wafer level package including: forming a redistribution line connected to a top surface of a die pad on a wafer with the die pad; additionally preparing a carrier film including a metal post with a concave central portion on one surface; bonding the metal post to a top surface of the redistribution line; molding a space between the metal posts with a molding resin; and removing the carrier film.

Abstract: In one exemplary embodiment, a program storage device readable by a machine, tangibly embodying a program of instructions executable by the machine for performing operations, said operations including: depositing a first layer having a first metal on a surface of a semiconductor structure, where depositing the first layer creates a first intermix region at an interface of the first layer and the semiconductor structure; removing a portion of the deposited first layer to expose the first intermix region; depositing a second layer having a second metal on the first intermix region, where depositing the second layer creates a second intermix region at an interface of the second layer and the first intermix region; removing a portion of the deposited second layer to expose the second intermix region; and performing at least one anneal on the semiconductor structure.

Abstract: In a modern 0.15 ?m power MOSFET, aluminum voids (voids formed in an aluminum-type electrode) are generated frequently in trench portions (source contact trenches) caused by the reduction of a cell pitch for refinement. It is considered to be attributable to the defects which are generated mainly due to a sudden increase of the aspect ratio from 0.84 in the previous generation to 2.8 in the current generation. Accordingly, concave portions of repetitive trenches having a high aspect ratio are filled with an aluminum-type metal by ionized sputtering throughout the processing, from the formation to the filling of an aluminum-type metal seed film.

Abstract: A semiconductor die package is disclosed. It includes a leadframe structure comprising a first die attach pad and a second die attach pad. A plurality of leads extend from the first and second die attach pads. The plurality of leads includes at least a first control lead and a second control lead. A first semiconductor die including a first device is mounted on the first die attach pad, and a second semiconductor die has a second device is mounted on the second die attach pad. A housing is provided in the semiconductor die package and protects the first and second dies. The housing may have an exterior surface and at least partially covers the first semiconductor die and the second semiconductor die. The first control lead and the second control lead are at opposite sides of the semiconductor die package.

Abstract: A high-quality epitaxial silicon thin layer is formed on an upgraded metallurgical grade silicon (UMG-Si) substrate. A thin film interface is fabricated between the UMG-Si substrate and the epitaxial silicon thin layer. The interface is capable of internal light reflection and impurities isolation. With the interface, photoelectrical conversion efficiency is improved. Thus, the present invention is fit to be applied for making solar cell having epitaxial silicon thin layer.

Abstract: According to one embodiment, a high electron mobility transistor (HEMT) comprises an insulator layer comprising a first group III-V intrinsic layer doped with a rare earth additive. The HEMT also comprises a second group III-V intrinsic layer formed over the insulator layer, and a group III-V semiconductor layer formed over the second group III-V intrinsic layer. In one embodiment, a method for fabricating a HEMT comprises forming a first group III-V intrinsic layer and doping the first group III-V intrinsic layer with a rare earth additive to produce an insulator layer. The method also comprises forming a second group III-V intrinsic layer over the insulator layer, and further forming a group III-V semiconductor layer over the second group III-V intrinsic layer. A two-dimensional electron gas (2DEG) is formed at a heterojunction interface of the group III-V semiconductor layer and the second group III-V intrinsic layer.

Abstract: A method for making a micro structure (100) is proposed. The method starts with the step of providing a silicon substrate (102), which has a main surface. A porous silicon layer (103)—extending into the silicon substrate from the main surface—is then formed. The method continues by etching the porous silicon layer selectively to obtain a set of projecting microelements of porous silicon (112); each projecting microelement projects from a remaining portion of the silicon substrate (106), thereby exposing a corresponding external surface. The projecting microelements are then treated to obtain a set of corresponding conductive (115) or insulating (115?) microelements; each conductive or insulating microelement is obtained by converting at least a prevalent portion of the porous silicon (extending into the corresponding projecting element from the external surface) into porous metal or ceramics, respectively.

Abstract: An organic light emitting device having a high light extraction efficiency and being excellent in an light emitting efficiency and durability is provided. The organic light emitting device includes an anode and a cathode, and a layer formed of an organic compound interposed between the anode and the cathode. The layer formed of the organic compound includes a light emitting layer, and the light emitting layer is formed of at least one organic light emitting material and an aliphatic compound, and a refractive index of the light emitting layer is 1.40 or more to 1.60 or less.

Abstract: A method for thinning a wafer is provided. In one embodiment, a wafer is provided having a plurality of semiconductor chips, the wafer having a first side and a second side opposite the first side, wherein each of the chips includes a set of through silicon vias (TSVs), each of the TSVs substantially sealed by a liner layer and a barrier layer. A wafer carrier is provided for attaching to the second side of the wafer. The first side of the wafer is thinned and thereafer recessed to partially expose portions of the liner layers, barrier layers and the TSVs protruding from the wafer. An isolation layer is deposited over the first side of the wafer and the top portions of the liner layers, barrier layers and the TSVs. Thereafter, an insulation layer is deposited over the isolation layer. The insulation layer is then planarized to expose top portions of the TSVs. A dielectric layer is deposited over the planarized first side of the wafer.

Abstract: A method of printing an ink on a wafer surface configured with a set of non-rounded peaks and a set of non-rounded valleys is disclosed. The method includes exposing the wafer including at least some non-rounded peaks and at least some of the non-rounded valleys in a region to an etchant. The method further includes depositing the ink on the region, wherein a set of rounded peaks and a set of rounded valleys are formed.