Abstract: An integrated circuit contains a transistor with a stress enhancement region on the source side only. In a DeMOS transistor, forming the stress enhancement region on the source side only and not forming a stress enhancement region in the drain extension increases the resistance of the drain extension region enabling formation of a DeMOS transistor with reduced area. In a MOS transistor, by forming the stress enhancement region on the source side only and eliminating the stress enhancement region from the drain side, transistor leakage is reduced and CHC reliability improved.

Abstract: An embodiment of the invention provides a chip package which includes: a semiconductor substrate having a first surface and an opposite second surface; a drain region located in the semiconductor substrate; a source region located in the semiconductor substrate; a gate located on the semiconductor substrate or at least partially buried in the semiconductor substrate, wherein a gate dielectric layer is between the gate and the semiconductor substrate; a drain conducting structure disposed on the first surface of the semiconductor substrate and electrically connected to the drain region; a source conducting structure disposed on the second surface of the semiconductor substrate and electrically connected to the source region; and a gate conducting structure disposed on the first surface of the semiconductor substrate and electrically connected to the gate.

Abstract: Disclosed are a semiconductor device and a method of manufacturing the same. In the semiconductor device according to an exemplary embodiment of the present disclosure, at the time of forming a source electrode, a drain electrode, a field plate electrode, and a gate electrode on a substrate having a heterojunction structure such as AlGaN/GaN, the field plate electrode made of the same metal as the gate electrode is formed on the side surface of a second support part positioned below a head part of the gate electrode so as to prevent the gate electrode from collapsing and improve high-frequency and high-voltage characteristic of the semiconductor device.

Abstract: A SiC semiconductor device includes a SiC semiconductor layer having a first-conductivity-type impurity, a field insulation film formed on a front surface of the SiC semiconductor layer and provided with an opening for exposing therethrough the front surface of the SiC semiconductor layer, an electrode connected to the SiC semiconductor layer through the opening of the field insulation film, and a guard ring having a second-conductivity-type impurity and being formed in a surface layer portion of the SiC semiconductor layer to make contact with a terminal end portion of the electrode connected to the SiC semiconductor layer. A second-conductivity-type impurity concentration in a surface layer portion of the guard ring making contact with the electrode is smaller than a first-conductivity-type impurity concentration in the SiC semiconductor layer.

Abstract: Embodiments of the invention provide a relatively uniform width fin in a Fin Field Effect Transistors (FinFETs) and apparatus and methods for forming the same. A fin structure may be formed such that the surface of a sidewall portion of the fin structure is normal to a first crystallographic direction. Tapered regions at the end of the fin structure may be normal to a second crystal direction. A crystallographic dependent etch may be performed on the fin structure. The crystallographic dependent etch may remove material from portions of the fin normal to the second crystal direction relatively faster, thereby resulting in a relatively uniform width fin structure.

Abstract: The present invention relates to a cell-based transparent sensor capable of the real-time optical observation of cell behavior, to a method for manufacturing same, and to a multi-detection sensor chip using same. More particularly, the present invention relates to a cell-based transparent sensor capable of the real-time optical observation of cell behavior, to a method for manufacturing same, and to a multi-detection sensor chip using same, wherein the sensor can sense the ionic concentration of an electrolyte in accordance with the variation in the metabolic activity of cells using an ion-selective field effect transistor (ISFET) sensor and an electrochemical sensor, and the sensor is made of a transparent material which enables real-time observations of optical phenomenon for measurement of cell behavior.

Abstract: A method of forming a semiconductor device is provided that includes forming a replacement gate structure on portion a substrate, wherein source regions and drain regions are formed on opposing sides of the portion of the substrate that the replacement gate structure is formed on. An intralevel dielectric is formed on the substrate having an upper surface that is coplanar with an upper surface of the replacement gate structure. The replacement gate structure is removed to provide an opening to an exposed portion of the substrate. A high-k dielectric spacer is formed on sidewalls of the opening, and a gate dielectric is formed on the exposed portion of the substrate. Contacts are formed through the intralevel dielectric layer to at least one of the source region and the drain region, wherein the etch that provides the opening for the contacts is selective to the high-k dielectric spacer and the high-k dielectric capping layer.

Abstract: An interposer includes a substrate includes a plurality of penetrating electrodes, and a wiring portion formed on the substrate, in which the wiring portion includes a wiring layer electrically connected to the penetrating electrodes and an insulating layer covering the wiring layer. The interposer includes a plurality of first UBM structures provided at a side opposite the substrate of the wiring portion, in which the first UBM structures are electrically connected to the wiring layer. The interposer includes a plurality of bumps provided at the side opposite the wiring portion of the substrate, in which the plurality of bumps is electrically connected to each of the penetrating electrodes via a plurality of second UBM structures.

Abstract: The present application discloses a MOSFET and a method for manufacturing the same. The MOSFET comprises an SOI chip comprising a semiconductor substrate, a buried insulating layer on the semiconductor substrate, and a semiconductor layer on the buried insulating layer; source/drain regions formed in the semiconductor layer; a channel region formed in the semiconductor layer and located between the source/drain regions; and a gate stack comprising a gate dielectric layer on the semiconductor layer, and a gate conductor on the gate dielectric layer, wherein the MOSFET further comprises a backgate formed in a portion of the semiconductor substrate below the channel region, and the backgate has a non-uniform doping profile, and wherein the buried insulating layer serves as a gate dielectric layer of the backgate. The MOSFET has an adjustable threshold voltage by changing the type of dopant and/or the doping profile in the backgate, and reduces a leakage current of the semiconductor device.

Abstract: A conductive top surface of a replacement gate stack is recessed relative to a top surface of a planarization dielectric layer by at least one etch. A dielectric capping layer is deposited over the planarization dielectric layer and the top surface of the replacement gate stack so that the top surface of a portion of the dielectric capping layer over the replacement gate stack is vertically recessed relative to another portion of the dielectric layer above the planarization dielectric layer. The vertical offset of the dielectric capping layer can be employed in conjunction with selective via etch processes to form a self-aligned contact structure.

Abstract: Semiconductors devices and methods of making semiconductor devices are provided. According to one embodiment, a semiconductor device, having more than two types of threshold voltages, can be employed in a logic integrated circuit with an embedded SRAM. The semiconductor device can include at least two transistors. The two transistors can be the same conductivity type (e.g., n-type or p-type). In addition, the two transistors can have disparate voltage thresholds.

Abstract: The present application discloses a MOSFET and a method for manufacturing the same.

Abstract: An ion sensitive sensor having an EIS structure, including: a semiconductor substrate, on which a layer of a substrate oxides is produced; an adapting or matching layer, which is prepared on the substrate oxide; a chemically stable, intermediate insulator, which is deposited on the adapting or matching layer; and an ion sensitive, sensor layer, which is applied on the intermediate insulator. The adapting or matching layer differs from the intermediate insulator and the substrate oxide in its chemical composition and/or structure. The adapting or matching layer and the ion sensitive, sensor layer each have an electrical conductivity greater than that of the intermediate insulator. There is an electrically conductive connection between the adapting or matching layer and the ion sensitive, sensor layer.

Abstract: A low-temperature metal gate stack for a field-effect transistor that is electrically activated at temperatures below 1000° C. The metal gate stack is composed of low melting materials that can be deposited by physical vapor deposition (PVD) onto a substrate.

Abstract: A through silicon via structure and a method of fabricating the through silicon via. The method includes: (a) forming a trench in a silicon substrate, the trench open to a top surface of the substrate; (b) forming a silicon dioxide layer on sidewalls of the trench, the silicon dioxide layer not filling the trench; (c) filling remaining space in the trench with polysilicon; after (c), (d) fabricating at least a portion of a CMOS device in the substrate; (e) removing the polysilicon from the trench, the dielectric layer remaining on the sidewalls of the trench; (f) re-filling the trench with an electrically conductive core; and after (f), (g) forming one or more wiring layers over the top surface of the substrate, a wire of a wiring level of the one or more wiring levels closet to the substrate contacting a top surface of the conductive core.

Abstract: Disclosed herein is a nano device, including: a carbon layer including one-layered graphene having a honeycombed planar structure in which carbon atoms are connected with each other and two or more-layered monocrystalline graphite; and one or more vertically-grown nanostructures formed on the carbon layer. This nano device can be used to manufacture an integrated circuit in which various devices including a graphene electronic device and a photonic device are connected with each other, and is a high-purity and high-quality nano device having a small amount of impurities because a metal catalyst is not used.

Abstract: The present application discloses a semiconductor structure and a method for manufacturing the same. A semiconductor structure according to the present invention can adjust the threshold voltage by capacitive coupling between a backgate region either and a source region or a drain region with a common contact, i.e. a source contact or a drain contact, which leads to a simple manufacturing process, a higher integration level, and a lower manufacture cost. Moreover, the asymmetric design of the backgate structure, together with the doping of the backgate region which can be varied as required in an actual device design, can further enhance the effects of adjusting the threshold voltage and improve the performances of the device.

Abstract: A semiconductor device includes a semiconductor substrate with a first surface and a second surface. The semiconductor substrate has an element region including an IGBT region and a diode region located adjacent to the IGBT region. An IGBT element is formed in the IGBT region. A diode element is formed in the diode region. A heavily doped region of first conductivity type is located on the first surface side around the element region. An absorption region of first conductivity type is located on the second surface side around the element region. A third semiconductor region of second conductivity type is located on the second surface side around the element region.

Abstract: A thin film transistor structure of a pixel is provided. In the present invention, a first metal layer serves as a gate electrode, and the gate electrode includes an extending gate electrode portion. A second metal layer includes a drain electrode partially and respectively overlapping the gate electrode and the gate electrode portion with the amorphous silicon layer interposed therebetween so as to form a first parasitic capacitor and a second parasitic capacitor. The total capacitance of the first parasitic capacitor and the second parasitic capacitor is invariable to withstand deviation caused by vibration of the machine in the photolithographic process, so that undesired effects in the liquid crystal display panel such as mura and flicker can be reduced.

Abstract: The present disclosure describes a semiconductor device including a semiconductor substrate and a gate stack disposed on the semiconductor substrate. A first spacer element is disposed on the substrate abutting the first gate stack. In an embodiment, the first spacer element includes silicon nitride. A second spacer element is adjacent the first spacer element. In an embodiment, the second spacer element includes silicon oxide. A raised source and a first raised drain is provided laterally contacting sidewalls of the second spacer element. In an embodiment, a contact directly interfaces with the second spacer element.

Abstract: A method of forming a semiconductor device having a substrate, an active region and an inactive region includes: forming a hardmask layer over the substrate; transferring a first pattern into the hardmask layer in the active region of the semiconductor device; forming one or more fills in the inactive region; forming a cut-away hole within, covering, or partially covering, the one or more fills to expose a portion of the hardmask layer, the exposed portion being within the one or more fills; and exposing the hardmask layer to an etchant to divide the first pattern into a second pattern including at least two separate elements.

Abstract: A semiconductor device in which a metal silicide layer is formed by a salicide process is improved in reliability. By a salicide process according to a partial reaction method, metal silicide layers are formed over respective surfaces of gate electrodes, n+-type semiconductor regions, and p+-type semiconductor regions. In a first heat treatment when the metal silicide layers are formed, a heat-conduction type anneal apparatus is used for the heat treatment of a semiconductor wafer. In a second heat treatment, a microwave anneal apparatus is used for the heat treatment of the semiconductor wafer, thereby reducing the temperature of the second heat treatment and preventing abnormal growth of the metal silicide layers. Thus, a junction leakage current in the metal silicide layers is reduced.

Abstract: A compound semiconductor device includes a group-III nitride semiconductor layer; an insulation film located on the group-III nitride semiconductor layer; a drain electrode located in a position which is a first distance away from an upper surface of the group-III nitride semiconductor layer; a source electrode located in a position which is the first distance away from the upper surface of the group-III nitride semiconductor layer; a gate electrode located between the drain electrode and the source electrode; and a field plate electrode located between the drain electrode and the gate electrode at a position which is a second distance away from the upper surface of the group-III nitride semiconductor layer, the second distance is shorter than the first distance.

Abstract: A method of forming an integrated circuit includes forming a gate structure over a substrate. Portions of the substrate are removed to form recesses adjacent to the gate structure. A silicon-containing material structure is formed in each of the recesses.

Abstract: Provided is a method of manufacturing a semiconductor device, that buried gate electrodes are formed in a pair of trenches in a substrate, so as to be recessed from the level of the top end of the trenches, a base region is formed between a predetermined region located between the pair of trenches, and a source region is formed over the base region.

Abstract: Field effect transistors and method for forming filed effect transistors. The field effect transistors including: a gate dielectric on a channel region in a semiconductor substrate; a gate electrode on the gate dielectric; respective source/drains in the substrate on opposite sides of the channel region; sidewall spacers on opposite sides of the gate electrode proximate to the source/drains; and wherein the sidewall spacers comprise a material having a dielectric constant lower than that of silicon dioxide and capable of absorbing laser radiation.

Abstract: An MOS transistor includes a doping profile that selectively increases the dopant concentration of the body region. The doping profile has a shallow portion that increases the dopant concentration of the body region just under the surface of the transistor under the gate, and a deep portion that increases the dopant concentration of the body region under the source and drain regions. The doping profile may be formed by implanting dopants through the gate, source region, and drain region. The dopants may be implanted in a high energy ion implant step through openings of a mask that is also used to perform another implant step. The dopants may also be implanted through openings of a dedicated mask.

Abstract: A ferro-electric random access memory (FRAM) chip, including a substrate; a first dielectric layer over the substrate; a gate over the first dielectric layer; a first aluminum oxide layer over the first dielectric layer and the gate; a second dielectric layer over the first aluminum oxide layer; a trench through the second dielectric layer and the first aluminum oxide layer to the gate; a hydrogen barrier liner over the second dielectric layer and lining the trench, and contacting the gate; and a silicon dioxide plug over the hydrogen barrier liner substantially filling the trench.

Abstract: There is provided a technology capable of providing desirable operation characteristics in a field effect transistor formed in an active region surrounded by a trench type element isolation part. An element isolation part includes trench type element isolation films, diffusion preventive films each including a silicon film or a silicon oxide film, and having a thickness of 10 to 20 nm formed over the top surfaces of the trench type element isolation films, and silicon oxide films each with a thickness of 0.5 to 2 nm formed over the top surfaces of the diffusion preventive films. The composition of the diffusion preventive film is SiOx (0?x<2). Each composition of the trench type element isolation films and the silicon oxide films is set to be SiO2.

Abstract: Improved semiconductor devices including metal gate electrodes are formed with reduced performance variability by reducing the initial high dopant concentration at the top portion of the silicon layer overlying the metal layer. Embodiments include reducing the dopant concentration in the upper portion of the silicon layer, by implanting a counter-dopant into the upper portion of the silicon layer, removing the high dopant concentration portion and replacing it with undoped or lightly doped silicon, and applying a gettering agent to the upper surface of the silicon layer to form a thin layer with the gettered dopant, which layer can be removed or retained.

Abstract: An optical electrical system that converts a photo image pattern to a conductance pattern comprises a photoconductive layer for receiving light image patterns and a conversion layer for converting an electrostatic voltage into a conductance pathway for a current flow. The light image pattern can be generated into a page sized area and generated from a light source comprising an array of projectors coupled together.

Abstract: A dielectric liner is formed on sidewalls of a gate stack and a lower contact-level dielectric material layer is deposited on the dielectric liner and planarized. The dielectric liner is recessed relative to the top surface of the lower contact-level dielectric material layer and the top surface of the gate stack. A dielectric metal oxide layer is deposited and planarized to form a dielectric metal oxide spacer that surrounds an upper portion of the gate stack. The dielectric metal oxide layer has a top surface that is coplanar with a top surface of the planarized lower contact-level dielectric material layer. Optionally, the conductive material in the gate stack may be replaced. After deposition of at least one upper contact-level dielectric material layer, at least one via hole extending to a semiconductor substrate is formed employing the dielectric metal oxide spacer as a self-aligning structure.

Abstract: The invention provides semiconductor materials including a gallium nitride material layer formed on a silicon substrate and methods to form the semiconductor materials. The semiconductor materials include a transition layer formed between the silicon substrate and the gallium nitride material layer. The transition layer is compositionally-graded to lower stresses in the gallium nitride material layer which can result from differences in thermal expansion rates between the gallium nitride material and the substrate. The lowering of stresses in the gallium nitride material layer reduces the tendency of cracks to form. Thus, the invention enables the production of semiconductor materials including gallium nitride material layers having few or no cracks. The semiconductor materials may be used in a number of microelectronic and optical applications.

Abstract: A method for contacting an FET device is disclosed. The method includes vertically recessing the device isolation, which exposes a sidewall surface on both the source and the drain. Next, silicidation is performed, resulting in a silicide layer covering both the top surface and the sidewall surface of the source and the drain. Next, metallic contacts are applied in such manner that they engage the silicide layer on both its top and on its sidewall surface. A device characterized as being an FET device structure with enlarged contact areas is also disclosed. The device has a vertically recessed isolation, thereby having an exposed sidewall surface on both the source and the drain. A silicide layer is covering both the top surface and the sidewall surface of both the source and the drain. Metallic contacts to the device engage the silicide on its top surface and on its sidewall surface.

Abstract: A method for fabricating a semiconductor device employs the way of first performing thermal annealing to the source/drain regions and then forming an ion-implanted region, such as a retrograde well. The method comprises the steps of: removing said dummy gate so as to expose said dummy gate dielectric layer and form an opening; performing ion implantation on the substrate from the opening to form an ion-implanted region; removing the dummy gate dielectric layer; performing thermal annealing to activate the dopants of the ion-implanted region; and depositing a new gate dielectric layer and a new metal gate in the opening in sequence, wherein the formed new gate dielectric layer covers the substrate and the inner walls of the sidewall spacers.

Abstract: A memory element includes a MOS transistor having a drain, a source and a body region covered by an insulated gate, wherein the thickness of the body region is divided into two distinct regions separated by a portion of an insulating layer extending parallel to the plane of the gate.

Abstract: A semiconductor device includes the following elements. A semiconductor substrate has a device formation region. The device formation region is defined by first and second device isolation regions which extend in first and second directions, respectively. The device formation region has a first gate groove which extends in the second direction. A first gate insulating film is disposed in a lower portion of the first gate groove. A first gate electrode is disposed on the first gate insulating film. The first gate electrode is disposed in the lower portion of the first gate groove. A buried insulating film is disposed over the first gate electrode. The buried insulating film is disposed in an upper portion of the first gate groove.

Abstract: An embedded, strained epitaxial semiconductor material, i.e., an embedded stressor element, is formed at the footprint of at least one pre-fabricated field effect transistor that includes at least a patterned gate stack, a source region and a drain region. As a result, the metastability of the embedded, strained epitaxial semiconductor material is preserved and implant and anneal based relaxation mechanisms are avoided since the implants and anneals are performed prior to forming the embedded, strained epitaxial semiconductor material.

Abstract: The present invention provides a method for manufacturing a semiconductor structure, which lies in covering a first dielectric layer with a second dielectric layer, forming a first contact hole with a small inner diameter within the second dielectric layer first, then etching the first dielectric layer to form a second contact hole with a much great inner diameter, and finally filling a conductive material into the first contact hole and the second contact hole to form contact plugs. Accordingly, the present invention further provides a semiconductor structure favorable for reducing contact resistance.

Abstract: The present application discloses a semiconductor structure and a method for manufacturing the same. The semiconductor structure according to the present invention adjusts a threshold voltage with a common contact, which has a portion outside the source or drain region extending to the back-gate region and provides an electrical contact of the source or drain region and the back-gate region, which leads to a simple manufacturing process, an increased integration level and a lowered manufacture cost. Moreover, the asymmetric design of the back-gate structure further increases the threshold voltage and improves the performance of the device.

Abstract: The invention provides a semiconductor device comprising: a substrate; a gate, which is formed on the substrate; a source and a drain, which are located on opposite sides of the gate, respectively; a contact, which contacts with the source and/or the drain, wherein the contact has an enlarged end at an end which is in contact with the source and/or the drain. In the present invention, since the contact area of the contact is increased on the interface in contact with the source/the drain, the contact resistance can be reduced, and thus the performances of the semiconductor device can be guaranteed/improved. The present invention further provides a method of fabricating the semiconductor device (especially the contact therein) as previously described.

Abstract: A semiconductor device includes: a first conductivity type transistor and a second conductivity type transistor, wherein each of the first conductivity type transistor and the second conductivity type includes a gate insulating film formed on a base, a metal gate electrode formed on the gate insulating film, and side wall spacers formed at side walls of the metal gate electrode, wherein the gate insulating film is made of a high dielectric constant material, and wherein offset spacers are formed between the side walls of the metal gate electrode and the inner walls of the side wall spacers in any one of the first conductivity type transistor and the second conductivity type transistor, or offset spacers having different thicknesses are formed in the first conductivity type transistor and the second conductivity type transistor.

Abstract: The present invention relates to a transistor and the method for forming the same. The transistor of the present invention comprises a semiconductor substrate; a gate dielectric layer formed on the semiconductor substrate; a gate formed on the gate dielectric layer; a source region and a drain region located in the semiconductor substrate and on respective sides of the gate, wherein at least one of the source region and the drain region comprises at least one dislocation; an epitaxial semiconductor layer containing silicon located on the source region and the drain region; and a metal silicide layer on the epitaxial semiconductor layer.

Abstract: A semiconductor device and a method of manufacturing the same are disclosed. The method includes forming ion impurity regions of a first conductivity type by forming a trench in a semiconductor substrate and implanting impurity ions into a lower portion of the trench at different depths; forming an oxide region in the substrate adjacent to one end of the trench; forming a device isolation film filling the trench; forming a high voltage well in the substrate and a second conductivity type body in the high voltage well; forming a gate on the semiconductor substrate partially overlapping the device isolation film; forming second well in the semiconductor substrate at one side of the device isolation film overlapping the ion diffusion regions and the oxide region; and forming source regions in the body and a drain region in the second well.

Abstract: A semiconductor device of the present invention has a (110)-plane-orientation silicon substrate and a p channel type field effect transistor formed in a pMIS region. The p channel type field effect transistor includes a gate electrode disposed via a gate insulation film, and source/drain regions disposed inside a trench disposed in the silicon substrate on the opposite sides of the gate electrode, and including SiGe larger in lattice constant than Si. The trench has a (100)-plane-orientation first inclined surface, and a (100)-plane-orientation second inclined surface crossing the first inclined surface at a sidewall part situated on the gate electrode side. With the configuration, the angle formed between the surface (110) plane and the (100) plane of the substrate is 45°, so that the first inclined surface is formed at a relatively acute angle. This can effectively apply a compressive strain to a channel region of the p channel type MISFET.

Abstract: A zero temperature coefficient (ZTC) capacitor including a silicon dioxide dielectric layer with a phosphorus density between 1.7×1020 atoms/cm3 and 2.3×1020 atoms/cm3. An integrated circuit containing a ZTC capacitor including a silicon dioxide dielectric layer with a phosphorus density between 1.7×1020 atoms/cm3 and 2.3×1020 atoms/cm3. A process of forming an integrated circuit containing a ZTC capacitor including a silicon dioxide dielectric layer with a phosphorus density between 1.7×1020 atoms/cm3 and 2.3×1020 atoms/cm3.

Abstract: A method for manufacturing a semiconductor device comprises forming a first spacer layer at sidewalls of one or more gate electrodes, forming a trench by etching an isolation insulating layer exposed between the gate electrodes, forming a second spacer layer on sidewalls of the gate electrodes and an inner surface of the trench and forming an interlayer insulating layer between the gate electrodes.

Abstract: A semiconductor structure including a p-channel field effect transistor (pFET) device located on a surface of a silicon germanium (SiGe) channel is provided in which the junction profile of the source region and the drain region is abrupt. The abrupt source/drain junctions for pFET devices are provided in this disclosure by forming an N- or C-doped Si layer directly beneath a SiGe channel layer which is located above a Si substrate. A structure is thus provided in which the N- or C-doped Si layer (sandwiched between the SiGe channel layer and the Si substrate) has approximately the same diffusion rate for a p-type dopant as the overlying SiGe channel layer. Since the N- or C-doped Si layer and the overlying SiGe channel layer have substantially the same diffusivity for a p-type dopant and because the N- or C-doped Si layer retards diffusion of the p-type dopant into the underlying Si substrate, abrupt source/drain junctions can be formed.

Abstract: Semiconductor devices are provided including a substrate having a first surface and a second surface recessed from opposite sides of the first surface, a gate pattern formed on the first surface and having a gate insulating layer and a gate electrode, a carbon-doped silicon buffer layer formed on the second surface, and source and drain regions doped with an n-type dopant or p-type dopant, epitaxially grown on the silicon buffer layer to be elevated from a top surface of the gate insulating layer.

Abstract: A semiconductor device includes a first semiconductor layer formed over a substrate, a second semiconductor layer formed over the first semiconductor layer, a source electrode and a drain electrode formed over the second semiconductor layer, an insulating film formed over the second semiconductor layer, a gate electrode formed over the insulating film, and a protection film covering the insulating film, the protection film being formed by thermal CVD, thermal ALD, or vacuum vapor deposition.