Abstract: A semiconductor device includes: a substrate; a lower wiring on the substrate; an inter-layer insulating film covering the lower wiring; first and second upper wirings on the inter-layer insulating film and separated from each other; and a semi-insulating protective film covering the first and second upper wirings, wherein the protective film is not provided in a region right above the lower wiring and between the first upper wiring and the second upper wiring.

Abstract: Provided are electrical connection structures and methods of fabricating the same. The structures may include a substrate including a bonding pad region provided with a bonding pad and a fuse region provided with a fuse, an insulating layer provided on the substrate and including a bonding pad opening exposing the bonding pad and a fuse opening exposing the fuse region, a connection terminal provided in the bonding pad region and electrically connected to the bonding pad, and a protection layer provided on the insulating layer including a first protection layer provided within the bonding pad region and a second protection layer in the fuse opening.

Abstract: A chip pad structure of an integrated circuit (IC) and the method of forming are disclosed. The chip pad comprises a main pad portion and a ring pad portion. During a charging process involved in forming the chip pad structure, electrical connections from the gate electrodes of MOS transistors in the IC substrate generally are made only to the ring pad portion that has an antenna-to-gate area ratio substantially below a predetermined antenna design rule ratio, and thus is resistant or immune to antenna effect. The main pad portion and the ring pad portion are coupled together through metal bridges formed in an upper interconnect metal layer or in the top conductive pad layer. The chip pad may be used as probe pads on a parametric testline or bonding pads on an IC.

Abstract: In a manufacturing method of a semiconductor device incorporating a semiconductor element in a multilayered wiring structure including a plurality of wiring layers and insulating layers, a semiconductor element is mounted on a silicon support body whose thickness is reduced to a desired thickness and which are equipped with a plurality of through-vias running through in the thickness direction; an insulating layer is formed to embed the semiconductor element; then, a plurality of wiring layers is formed on the opposite surfaces of the silicon support body in connection with the semiconductor element. Thus, it is possible to reduce warping which occurs in proximity to the semiconductor element in manufacturing, thus improving a warping profile in the entirety of a semiconductor device. Additionally, it is possible to prevent semiconductor elements from becoming useless, improve a yield rate, and produce a thin-type semiconductor device with high-density packaging property.

Abstract: A method of manufacturing a wiring board unit, the wiring board unit including a semiconductor package that includes a memory chip, a wiring board on which the semiconductor package is mounted, and an insertion base inserted between the wiring board and the semiconductor package, the method includes: forming a plurality of connection portion groups in a base material, the connection portion groups each including a plurality of connection portions that each electrically connect a board-side pad of the wiring board and an external terminal of the semiconductor package to each other; forming the insertion base such that resistances of the connection portions included in the connection portion groups are adjusted in accordance with types of target memory chips; and connecting the external terminals and the board-side pads to one another by using the connection portion group selected in accordance with the type of the memory chip.

Abstract: A semiconductor device includes a semiconductor chip and a first material including molecules that are configured to absorb thermal energy by reversibly changing a spatial molecular structure of the molecules.

Abstract: Provided are a light-emitting device and a photovoltaic cell having excellent characteristics. A light-emitting device (10) includes a cathode (34), an anode (32), a light-emitting layer (50) interposed between the cathode (34) and the anode (32), and an electron injection layer (44) provided between the cathode (34) and the light-emitting layer (50) and connected to the cathode (34), in which at least one of the anode (32) and the cathode (34) contains a conductive material having an aspect ratio of 1.5 or more, and the electron injection layer (44) contains an organic compound having at least one of an ionic group and a polar group.

Abstract: A semiconductor device includes: a lead frame; a semiconductor element held by the lead frame; a frame body which is formed on the lead frame to surround the semiconductor element, cover a side surface of the lead frame, and expose a bottom surface of the lead frame; and a protective resin filling a region surrounded by the frame body. The lead frame includes an uneven part formed in a section which is part of an upper surface of the lead frame, and is covered with the frame body.

Abstract: In accordance with an embodiment of the present invention, a semiconductor package includes a substrate having a first major surface and an opposite second major surface. A first chip is disposed in the substrate. The first chip includes a plurality of contact pads at the first major surface. A via bar is disposed in the substrate. An antenna structure is disposed within the via bar.

Abstract: Various embodiments provide a chip. The chip may include a body having two main surfaces and a plurality of side surfaces; a first power electrode extending over at least one main surface and at least one side surface of the body; and a second power electrode extending over at least one main surface and at least one side surface of the body.

Abstract: A semiconductor device includes a storage node contact plug, a bit line in communication with to the storage node contact plug, and an expansion unit formed on a sidewall of the bit line. Thermal expansion of the expansion unit serves to increase capacitance by ensuring a distance between the bit line and the storage node contact plug, thereby improving a sensing margin. A cell characteristic such as a record recovery time (tWR) may be enhanced.

Abstract: A multifunction semiconductor package structure includes a substrate unit, a circuit unit, a support unit, a semiconductor unit, a package unit and an electrode unit. The substrate unit includes a substrate body and a first electronic element having a plurality of conductive contact portions. The circuit unit includes a plurality of first conductive layers disposed on the substrate body. The semiconductor unit includes a plurality of second electronic elements. Each second electronic element is electrically connected between two corresponding first conductive layers. The package unit includes a package body disposed on the substrate body to enclose the second electronic elements. The electrode unit includes a plurality of top electrodes, a plurality of bottom electrodes, and a plurality of lateral electrodes electrically connected between the top electrodes and the bottom electrodes.

Abstract: A interconnect structure includes a conductive layer formed in a dielectric layer. An adhesion layer is formed between the dielectric layer and a substrate. The adhesion layer has a carbon content ratio greater than a carbon content ratio of the dielectric layer.

Abstract: A method for manufacturing the semiconductor apparatus includes an anchor process of forming a barrier metal film and carrying out physical etching making use of sputter gas. The anchor process is carried out at the same time on a wire connected to the lower portion of a first aperture serving as a penetration connection hole and a wire connected to the lower portion of a second aperture serving as a connection hole having an aspect ratio different from the aspect ratio of the penetration connection hole. The first and second apertures are apertures created on a semiconductor substrate obtained by bonding first and second semiconductor substrates to each other. The present technology can be applied to the semiconductor apparatus such as a solid-state imaging apparatus.

Abstract: Provided is a display unit that includes: a laminated structure including two first wirings, a first insulating layer, and a concave part, in which the first wirings are adjacent to each other, the first insulating layer is provided on the first wirings and is made of an organic material, and the concave part penetrates, between the first wirings, from the first insulating layer to the first wirings in a laminated direction; and a second insulating layer provided in the concave part and on the laminated structure.

Abstract: A semiconductor device and a method of manufacturing the same are provided. The device includes first and second line pattern units configured to extend substantially parallel to one another in a first direction and alternately disposed such that end portions of the first and second line pattern units are arranged in a diagonal direction, third and fourth pattern units configured to respectively extend from the end portions of the first and second line pattern units in a second direction crossing the first direction, first contact pad units respectively formed in the third line pattern units disposed a first distance from the end portions of the first line pattern units, and fourth contact pad units respectively formed in the fourth line pattern units disposed a second distance from the end portions of the second line pattern units. Here, the second distance is different from the first distance.

Abstract: A rectifier diode includes a substrate defining an even number of through holes, one or a number of bare chip diodes placed on the top surface of the substrate with even number of conducting grooves thereof respectively kept in alignment with respective through holes of the substrate, and a conducting unit including a metal interface layer coated on exposed surfaces of each bare chip diode and the substrate using, a conductive metal thin film covered over the metal interface layer and defining an electroplating space within each through hole of the substrate and the corresponding conducting groove of one bare chip diode and a conducting medium coated in each electroplating space to form an electrode pin and a bond pad.

Abstract: A microelectronic assembly may include a microelectronic element having a surface and a plurality of contacts at the surface; a first element consisting essentially of at least one of semiconductor or dielectric material, the first element having a surface facing the surface of the microelectronic element and a plurality of first element contacts at the surface of the first element; electrically conductive masses each joining a contact of the plurality of contacts of the microelectronic element with a respective first element contact of the plurality of first element contacts; a thermally and electrically conductive material layer between the surface of the microelectronic element and the surface of the first element and adjacent conductive masses of the conductive masses; and an electrically insulating coating electrically insulating the conductive masses and the surfaces of the microelectronic element and the first element from the thermally and electrically conductive material layer.

Abstract: An electrical contact for a detector, the electrical component, comprising a cadmium tellurium component, a first layer formed onto the cadmium tellurium component, wherein the first layer comprises indium and a contact agent being bonded directly or indirectly to the first layer to be in electrical contact with the first layer. The contact agent may be a stud bump or a conductive adhesive interconnect being bonded indirectly to the first layer via noble metal shielding layer.

Abstract: Sidewall protection processes are provided for Cu pillar bump technology, in which a protection structure on the sidewalls of the Cu pillar bump is formed of at least one of non-metal material layers, for example a dielectric material layer, a polymer material layer, or combinations thereof.

Abstract: A method of fabricating a semiconductor device is disclosed. A photosensitive material is coated over the device. A plurality of masks for a chip layout are obtained. The plurality of masks are exposed to encompass a chip area of the device using at least one reticle repeatedly. The at least one reticle is of a set of reticles. The chip area has a resultant dimension greater than a dimension of the at least one reticle. A developer is used to remove soluble portions of the photosensitive material forming a resist pattern in the chip area.

Abstract: A photonic device comprises a substrate and a dielectric material including two or more openings that expose a portion of the substrate, the two or more openings each having an aspect ratio of at least 1. A bottom diode material comprising a compound semiconductor material that is lattice mismatched to the substrate occupies the two or more openings and is coalesced above the two or more openings to form the bottom diode region. The device further includes a top diode material and an active diode region between the top and bottom diode materials.

Abstract: Contacts for semiconductor devices and methods of making thereof are disclosed. A method comprises forming a first layer on a semiconductor, the first layer comprising one or more metals; forming a second layer on the first layer, the second layer comprising the one or more metals, nitrogen and oxygen; and heating the first and second layer such that oxygen migrates from the second layer into the first layer and the first layer comprises a sub-stoichiometric metal oxide after heating. Exemplary embodiments use transition metals such as Ti in the first layer. After heating there is a sub-stoichiometric oxide layer of about 2.5 nm thickness between a metal nitride conductor and the semiconductor. The specific contact resistivity is less than about 7×10?9 ?·cm2.

Abstract: Thermosetting resin compositions with low coefficient of thermal expansion are provided herein.

Abstract: Methods and apparatus are disclosed which reduce the stress concentration at the redistribution layers (RDLs) of a package device. A package device may comprise a seed layer above a passivation layer, covering an opening of the passivation layer, and covering and in contact with a contact pad. A RDL is formed above the passivation layer, above and in contact with the seed layer, covering the opening of the passivation layer, and electrically connected to the contact pad through the seed layer. The RDL has an end portion with a surface that is smooth without a right angle. The surface of the end portion of the RDL may have an obtuse angle, or a curved surface.

Abstract: A semiconductor device has a structure including a substrate, a first insulating film formed over a part of a principal plane of the substrate, a conductive portion formed over a surface of the first insulating film, and a second insulating film which covers the principal plane of the substrate, the first insulating film, and the conductive portion and whose moisture resistance is higher than moisture resistance of the first insulating film. The first insulating film is placed between the substrate and the conductive portion to prevent the generation of parasitic capacitance. The first insulating film is covered with the second insulating film whose moisture resistance is higher than the moisture resistance of the first insulating film. The second insulating film prevents the first insulating film from absorbing moisture.

Abstract: A surface mount semiconductor device having external contact elements exposed in a ball grid array (BGA) at its external active face for mechanical and electrical connection to an external support and a semiconductor die connected electrically internally with the external contact elements. A reinforcement layer of electrically insulating material extends between and surrounds laterally peripheral contact elements of the BGA. The reinforcement layer extends to from about thirty percent (30%) to about fifty percent (50%) of the height of the peripheral contact elements at the active face.

Abstract: An electronic module. One embodiment includes a carrier. A first transistor is attached to the carrier. A second transistor is attached to the carrier. A first connection element includes a first planar region. The first connection element electrically connects the first transistor to the carrier. A second connection element includes a second planar region. The second connection element electrically connects the second transistor to the carrier. In one embodiment, a distance between the first planar region and the second planar region is smaller than 100 ?m.

Abstract: A Fo-WLCSP has a first polymer layer formed around a semiconductor die. First conductive vias are formed through the first polymer layer around a perimeter of the semiconductor die. A first interconnect structure is formed over a first surface of the first polymer layer and electrically connected to the first conductive vias. The first interconnect structure has a second polymer layer and a plurality of second vias formed through the second polymer layer. A second interconnect structure is formed over a second surface of the first polymer layer and electrically connected to the first conductive vias. The second interconnect structure has a third polymer layer and a plurality of third vias formed through the third polymer layer. A semiconductor package can be mounted to the WLCSP in a PoP arrangement. The semiconductor package is electrically connected to the WLCSP through the first interconnect structure or second interconnect structure.

Abstract: A method of forming an oxide layer on an exposed surface of a semiconductor device which contains a p-n junction is disclosed, the method comprising: immersing the exposed surface of the semiconductor device in an electrolyte; producing an electric field in the semiconductor device such that the p-n junction is forward-biased and the exposed surface is anodic; and electrochemically oxidising the exposed surface to form an oxide layer.

Abstract: A bump for a semiconductor package includes: a first bump formed on a semiconductor chip and having at least two land parts and a connection part which connects the land parts and has a line width smaller than the land parts; and a second bump formed on the first bump and projecting on the land parts of the first bump in shapes of a hemisphere.

Abstract: A method of attaching an IC wafer having a plurality of copper pillars (“CuP's) projecting from one face thereof to a substrate having a plurality of contact pads on one face thereof including applying a film having a substantial amount of filler particles therein to the one face of the wafer; applying an a-stage resin having substantially no filler particles therein to the one face of the substrate; and interfacing the film with the a-stage resin.

Abstract: There are provided an electrode foil which has all the functions of a supporting base material, an electrode and a reflective layer and also has a superior thermal conductivity; and an organic device using the same. The electrode foil comprises a metal foil, wherein the electrode foil has at least one outermost surface which is an ultra-smooth surface having an arithmetic average roughness Ra of 10.0 nm or less as measured in accordance with JIS B 0601-2001.

Abstract: In a semiconductor device in which a plurality of semiconductor chips are stacked, performance is enhanced without deteriorating productivity. The semiconductor device has a plurality of elements, an interlayer insulating film, a pad, and a bump electrode electrically connected with the pad sequentially formed on a main surface of a silicon substrate and has a back-surface electrode formed on a back surface of the silicon substrate and electrically connected with the bump electrode. The bump electrode has a protruding portion penetrating through the pad and protruding toward the silicon substrate side. The back-surface electrode is formed so as to reach the protruding portion of the bump electrode from the back surface side of the silicon substrate toward the main surface side and to cover the inside of a back-surface electrode hole portion which does not reach the pad, so that the back-surface electrode is electrically connected with the bump electrode.

Abstract: A semiconductor device including a semiconductor substrate, an interface layer formed on the semiconductor substrate including at least 1×1020 atoms/cm3 of S (Sulfur), a metal-semiconductor compound layer formed on the interface layer, the metal-semiconductor compound layer including at least 1×1020 atoms/cm3 of S in the its whole depth, and a metal electrode formed on the metal-semiconductor compound layer.

Abstract: The present invention provides a film adhesive that can prevent a thermal effect to a semiconductor wafer and that can suppress warping of the semiconductor wafer; a dicing tape with a film adhesive; and a method of manufacturing a semiconductor device. The present invention relates to a film adhesive comprising a thermoplastic resin and electrically conductive particles, the film adhesive having an adhesion strength measured at 25° C. after the film adhesive is pasted to a mirror silicon wafer at 40° C. of 0.5 N/10 mm or more.

Abstract: A flip chip interconnect has a tapering interconnect structure, and the area of contact of the interconnect structure with the site on the substrate metallization is less than the area of contact of the interconnect structure with the die pad. Also, a bond-on-lead or bond-on-narrow pad or bond on a small area of a contact pad interconnection includes such tapering flip chip interconnects. Also, methods for making the interconnect structure include providing a die having interconnect pads, providing a substrate having interconnect sites on a patterned conductive layer, providing a bump on a die pad, providing a fusible electrically conductive material either at the interconnect site or on the bump, mating the bump to the interconnect site, and heating to melt the fusible material.

Abstract: A MEMS integrated circuit including a plurality of layers where a portion includes one or more electronic elements on a semiconductor material substrate. The circuit includes a structure of interconnection layers having a bottom layer of conductor material and a top layer of conductor material where the layers are separated by at least one layer of dielectric material. The bottom layer may be formed above and in contact with an Inter Dielectric Layer. The circuit also includes a hollow space within the structure of interconnection layers and a MEMS device in communication with the structure of interconnection layers.

Abstract: Atomic layer deposition (ALD) techniques typically involve briefly exposing the surface of a substrate to a precursor within an atomic layer deposition chamber, and purging the chamber with a purge gas, such as nitrogen, before exposing the substrate to a second precursor. A series of such cycles results in the deposition of microscopically thin film layers on the substrate surface that are further processed to generate a semiconductor component. In order to reduce unintended oxygen deposition, the chamber is typically evacuated to a vacuum level of 10e?06 torr-liters/second, which is suitable for the related techniques of chemical vapor deposition. However, atomic layer deposition is demonstrably more sensitive to oxygen contamination, due to the exposure of each layer to residual oxygen within the chamber. Tighter process control is achievable by performing atomic layer deposition at a higher vacuum level, not exceeding approximately 10e?06 torr-liters/second, in order to reduce oxygen contamination.

Abstract: Semiconductor devices, and methods of fabricating the same, include first conductive lines on a substrate, and a first molding layer covering the first conductive lines. The first conductive lines have air gaps between adjacent first conductive lines. Sidewalls of the first conductive lines and a bottom surface of the first molding layer collectively define a first gap region of each of the air gaps. The sidewalls of the first conductive lines and a top surface of the first molding layer collectively define a second air gap region of each of the air gaps.

Abstract: A semiconductor device includes a semiconductor substrate, a surface electrode formed on the semiconductor substrate, an ineffective region formed to surround the surface electrode, and an ID-indicating portion made of a different material than the surface electrode and formed on the surface electrode to indicate an ID. The area of the ineffective region is smaller than the area of the surface electrode.

Abstract: A device includes a semiconductor chip including a first main face and a second main face, the second main face being the backside of the semiconductor chip. The second main face includes a first region and a second region, the second region being a peripheral region of the second main face. The device further includes a dielectric material arranged over the second region and an electrically conductive material arranged over the first region.

Abstract: A semiconductor device includes: a package; an input matching circuit and an output matching circuit in the package; and transistor chips between the input matching circuit and the output matching circuit in the package. Each transistor chip includes a semiconductor substrate having long sides and short sides that are shorter than the long sides, and a gate electrode, a drain electrode and a source electrode on the semiconductor substrate. The gate electrode has gate fingers arranged along the long sides of the semiconductor substrate and a gate pad commonly connected to the gate fingers and connected to the input matching circuit via a first wire. The drain electrode is connected to the output matching circuit via a second wire. The long sides of the semiconductor substrates of the transistor chips are oblique with respect to an input/output direction extending from the input matching circuit to the output matching circuit.

Abstract: In a CSP type semiconductor device, the invention prevents a second wiring from forming a narrowed portion on a lower surface of a step portion at the time of forming the second wiring that is connected to the back surface of a first wiring formed near a side surface portion of a semiconductor die on the front surface and extends onto the back surface of the semiconductor die over the step portion of a window that is formed from the back surface side of the semiconductor die so as to expose the back surface of the first wiring. A glass substrate is bonded on a semiconductor substrate on which a first wiring is formed on the front surface near a dicing line with an adhesive resin being interposed therebetween. The semiconductor substrate is then etched from the back surface to form a window having step portions with inclined sidewalls around the dicing line as a center.

Abstract: A semiconductor module is provided which is capable of lowering surges caused when switching elements are switched on and off. The module has a plurality of lead frames, switching elements, electronic components, and a sealing member. The switching elements are electrically connected to the lead frames respectively. Part of the lead frames, the switching elements, and the electronic components are sealed by the sealing member. The electronic components are mounted on primary surfaces of the lead frames respectively.

Abstract: Provided is a conductive paste, an electrode for a semiconductor device manufactured by using the conductive paste, a semiconductor device and a method for manufacturing the semiconductor device. The conductive paste includes conductive powder made of a plurality of conductive particles and silver powder made of a plurality of silver particles. The conductive particles includes a base material made of ceramics and a conductive layer configured to cover at least a part of an outer surface of the base material. The ratio of the mass of the conductive layer relative to the total mass of the conductive particles is 10% or more by mass, and the ratio of the mass of the conductive powder relative to the total mass of the conductive powder and the silver powder is 25% or less by mass.

Abstract: An apparatus for a semiconductor-package includes a semiconductor device having a radio frequency (RF) input or output, an antenna pad, and a package structured to house the semiconductor device and the antenna pad. The antenna pad may be coupled to the radio frequency (RF) input or output, and the antenna pad is structured to reduce the inductance of the package. The antenna pad may include a pad disposed above the semiconductor device, a pad disposed to a side of the semiconductor device, or an antenna chip. An antenna may be coupled to the antenna pad. The antenna may include a trace antenna, a staggered antenna, or a helical antenna.

Abstract: A semiconductor device includes a substrate, a surface electrode of aluminum-containing material formed on the substrate, a metal film of solderable material formed on the surface electrode, and an end-securing film securing an end of the metal film and having a portion on the surface electrode and also having an overlapping portion which is formed integrally with the portion on the surface electrode and which overlaps the end of the metal film.

Abstract: A pattern-forming method includes forming a silicon-containing film on a substrate, the silicon-containing film having a mass ratio of silicon atoms to carbon atoms of 2 to 12. A shape transfer target layer is formed on the silicon-containing film. A fine pattern is transferred to the shape transfer target layer using a stamper that has a fine pattern to form a resist pattern. The silicon-containing film and the substrate are dry-etched using the resist pattern as a mask to form a pattern on the substrate in nanoimprint lithography. According to another aspect of the invention, a silicon-containing film includes silicon atoms and carbon atoms. A mass ratio of silicon atoms to carbon atoms is 2 to 12. The silicon-containing film is used for a pattern-forming method employed in nanoimprint lithography.

Abstract: The present invention provides an aluminum nitride substrate and an aluminum nitride circuit board having excellent insulation characteristics and heat dissipation properties and having high strength, a semiconductor apparatus, and a method for manufacturing an aluminum nitride substrate.