Abstract: A dielectric material incorporating a graded carbon adhesion layer whereby the content of C increases with layer thickness and a multiphase ultra low k dielectric comprising a porous SiCOH dielectric material having a k less than 2.7 and a modulus of elasticity greater than 7 GPa is described. A semiconductor integrated circuit incorporating the above dielectric material in interconnect wiring is described and a semiconductor integrated circuit incorporating the above multiphase ultra low k dielectric in a gate stack spacer of a FET is described.

Abstract: An electrically conductive paste providing low alpha particle emission is provided. A resin and conductive particles are mixed, and a curing agent is added. A solvent is subsequently added. The electrically conductive paste including a resin compound is formed by mixing the mixture in a high shear mixer. The electrically conductive paste can be applied to a surface of an article to form a coating, or can be molded into an article. The solvent is evaporated, and the electrically conductive paste is cured to provide a graphite-containing resin compound. The graphite-containing resin compound is electrically conductive, and provides low alpha particle emission at a level suitable for a low alpha particle emissivity coating.

Abstract: A semiconductor wafer, includes: a plurality of element regions; a surface electrode that is disposed in each of the plurality of element regions; an insulating layer that is disposed in each of the plurality of element regions and of which height from a front side surface of the semiconductor wafer is higher than that of the surface electrode in a periphery of the surface electrode; and a dicing line groove that is formed in a front side surface of the semiconductor wafer, that surrounds the surface electrode with the insulating layer therebetween, of which height from the front side surface of the semiconductor wafer is lower than that of the insulating layer, and that extends to a perimeter of the semiconductor wafer; in which the insulating layer is formed with a communication passage that extends from a side of the surface electrode to the dicing line groove.

Abstract: An electrically conductive paste providing low alpha particle emission is provided. A resin and conductive particles are mixed, and a curing agent is added. A solvent is subsequently added. The electrically conductive paste including a resin compound is formed by mixing the mixture in a high shear mixer. The electrically conductive paste can be applied to a surface of an article to form a coating, or can be molded into an article. The solvent is evaporated, and the electrically conductive paste is cured to provide a graphite-containing resin compound. The graphite-containing resin compound is electrically conductive, and provides low alpha particle emission at a level suitable for a low alpha particle emissivity coating.

Abstract: A semiconductor device is manufactured by, first, providing a wafer, designated with a saw street guide, and having a bond pad formed on an active surface of the wafer. The wafer is taped with a dicing tape. The wafer is singulated along the saw street guide into a plurality of dies having a plurality of gaps between each of the plurality of dies. The dicing tape is stretched to expand the plurality of gaps to a predetermined distance. An organic material is deposited into each of the plurality of gaps. A top surface of the organic material is substantially coplanar with a top surface of a first die of the plurality of dies. A redistribution layer is patterned over a portion of the organic material. An under bump metallization (UBM) is deposited over the organic material in electrical communication, through the redistribution layer, with the bond pad.

Abstract: A method of growing a thin film comprises growing a thin film by conformally forming at least one layer over a substrate having structures extending from a surface of the substrate, whereby the or each layer is formed over the surface of the substrate and over the structures extending from the surface. The thickness of the conformal layer, or the sum of the thicknesses of the conformal layers, is at least half the average spacing of the structures, and; at least one of the height of the structures, the average spacing of the structures and the size of the smallest dimension of the structures is set so as to provide an enhanced growth rate for the or each conformal layer (compared to the growth rate over a planar substrate).

Abstract: The mechanisms for forming a multi-chip package described enable chips with different bump sizes being packaged to a common substrate. A chip with larger bumps can be bonded with two or more smaller bumps on a substrate. Conversely, two or more small bumps on a chip may be bonded with a large bump on a substrate. By allowing bumps with different sizes to be bonded together, chips with different bump sizes can be packaged together to form a multi-chip package.

Abstract: A device includes a bottom chip and an active top die bonded to the bottom chip. A dummy die is attached to the bottom chip. The dummy die is electrically insulated from the bottom chip.

Abstract: A 3D stacking semiconductor device and a manufacturing method thereof are provided. The manufacturing method includes the following steps. N layers of stacking structures are provided. Each stacking structure includes a conductive layer and an insulating layer. A first photoresister layer is provided. The stacking structures are etched P?1 times by using the first photoresister layer as a mask. A second photoresister layer is provided. The stacking structures are etched Q?1 times by using the second photoresister layer as a mask. The first photoresister layer is trimmed along a first direction. The second photoresister layer is trimmed along a second direction. The first direction is different from the second direction. A plurality of contact points are arranged along the first and the second directions in a matrix. The included angle between the first direction and the second direction is an acute angle.

Abstract: A semiconductor device is disclosed. The semiconductor device includes a substrate comprises a plurality of metal layers. The semiconductor device also includes dielectric posts disposed in the metal layers. The density of the dielectric posts in the metal layers is equal to about 15-25%.

Abstract: A semiconductor device includes a substrate in which a cell region and a contact region are defined, a pad structure including a plurality of first conductive layers and a plurality of first insulating layers formed alternately with each other in the contact region of the substrate, wherein an end of the pad structure is patterned stepwise, portions of the first conductive layers exposed at the end of the pad structure are defined as a plurality of pad portions, and the plurality of pad portions have a greater thickness than unexposed portions of the plurality of first conductive layers.

Abstract: A semiconductor device includes: leads (5) in each of which a cutout (5a) is formed; a die pad (11); a power element (1) held on the die pad (11); and a package (6) made of a resin material, and configured to encapsulate inner end portions of the leads (5), and the die pad (11) including the power element (1). The cutout (5a) is located in a region of each of the leads (5) including a portion of the lead (5) located at a boundary between the lead (5) and the package (6), and is filled with a resin material.

Abstract: In a high frequency module, electronic components are mounted on a mounting surface of a collective substrate including a plurality of unit substrates that include a via conductor electrically conducted to a ground potential in a peripheral portion thereof, and the mounting surface and the electronic components are encapsulated with an encapsulation layer. The collective substrate is cut on the encapsulation layer side, thereby forming a half-cut groove penetrating through the encapsulation layer and extending halfway along the collective substrate in a thickness direction such that the via conductor is exposed only at a bottom surface of the half-cut groove. A conductive shield layer is formed to cover the encapsulation layer and is electrically conducted to the exposed via conductor. The collective substrate is then cut into individual unit substrates each including the conductive shield layer electrically conducted to the ground potential through the via conductor.

Abstract: A fabrication method of a semiconductor package is provided, which includes the steps of: providing a carrier having an adhesive layer and at least a semiconductor element having a protection layer; disposing the semiconductor element on the adhesive layer of the carrier through the protection layer; forming an encapsulant on the adhesive layer of the carrier for encapsulating the semiconductor element; removing the carrier and the adhesive layer to expose the protection layer from the encapsulant; and removing the protection layer to expose the semiconductor element from the encapsulant. Since the semiconductor element is protected by the protection layer against damage during the process of removing the adhesive layer, the product yield is improved.

Abstract: Methods of manufacturing semiconductor integrated circuits having a compressive nitride layer are disclosed. In one example, a method of fabricating an integrated circuit includes depositing an aluminum layer over a semiconductor substrate, depositing a tensile silicon nitride layer or a neutral silicon nitride layer over the aluminum layer, and depositing a compressive silicon nitride layer over the tensile silicon nitride layer or the neutral silicon nitride layer. The compressive silicon nitride layer is deposited at a thickness that is at least about twice a thickness of the tensile silicon nitride layer or the neutral silicon nitride layer. Further, there is no delamination present at an interface between the aluminum layer and the tensile silicon nitride layer or the neutral silicon nitride layer, or at an interface between tensile silicon nitride layer or the neutral silicon nitride layer and the compressive nitride layer.

Abstract: This semiconductor device, which has electronic components provided in a cavity of a module having a cavity structure, can be prevented from being increased in size. In the device, the module having the cavity structure is provided with a plurality of components, for instance, an IC (3) and chip components (6a, 6b), on one surface facing a motherboard (9), said one surface being on the cavity side. The motherboard (9) is provided with the chip components (6c, 6d) on parts of one surface facing the module having the cavity structure, said parts not having the components provided on the module surface having the components provided thereon.

Abstract: A semiconductor power module according to the present invention includes a base member, a semiconductor power device having a surface and a rear surface with the rear surface bonded to the base member, a metal block, having a surface and a rear surface with the rear surface bonded to the surface of the semiconductor power device, uprighted from the surface of the semiconductor power device in a direction separating from the base member and employed as a wiring member for the semiconductor power device, and an external terminal bonded to the surface of the metal block for supplying power to the semiconductor power device through the metal block.

Abstract: Solder on slot connections in package on package structures. An apparatus includes a substrate having a front side surface and a back side surface; a first passivation layer disposed over at least one of the front side and back side surfaces; at least one via opening formed in the first passivation layer; a conductor layer disposed over the first passivation layer, coupled to the at least one via and forming a conductive trace on the surface of the first passivation layer; a second passivation layer formed over the conductor layer; and at least one slot opening formed in the second passivation layer and exposing a portion of the conductive trace for receiving a solder connector. In additional embodiments the substrate may be a semiconductor wafer. Methods for forming the structures are disclosed.

Abstract: A method for manufacturing a metal pad structure of a die is provided, the method including: forming a metal pad between encapsulation material of the die, wherein the metal pad and the encapsulation material are separated from each other by a gap; and forming additional material in the gap to narrow at least a part of the gap.

Abstract: A method of forming a metal interconnect structure includes forming a copper line within an interlevel dielectric (ILD) layer; directly doping a top surface of the copper line with a copper alloy material; and forming a dielectric layer over the ILD layer and the copper alloy material; wherein the copper alloy material serves an adhesion interface layer between the copper line and the dielectric layer.

Abstract: Electronic assemblies and solders used in electronic assemblies are described. One embodiment includes a die and a substrate, with a solder material positioned between the die and the substrate, the solder comprising at least 91 weight percent Sn, 0.4 to 1.0 weight percent Cu and at least one dopant selected from the group consisting of Ag, Bi, P, and Co. Other embodiments are described and claimed.

Abstract: To provide a surface coating method, which contains applying a surface coating material to a layered structure so as to cover at least a surface of an insulating film of the layered structure, to form a coating on the surface of the insulating film, wherein the surface coating material contains a water-soluble resin, an organic solvent, and water, and wherein the layered structure contains the insulating film exposed to an outer surface, and a patterned metal wiring exposed to an outer surface.

Abstract: A system and a method of self-cooling a semiconductor package are described. A cell is formed, which contains a thermally conductive and electrically insulative material, sandwiched between a first thermally conductive plate and a second thermally conductive plate. A plurality of integrated circuits are formed by combinatorial processing. The plurality of integrated circuits are interconnected into a semiconductor integrated circuit package. The cell is thermally bonded to the semiconductor integrated circuit package. The first thermally conductive plate is electrically connected to the semiconductor integrated circuit package. A current is supplied to the second thermally conductive plate by an electrical lead from a supply voltage. Power is provided in series to the semiconductor integrated circuit package and through the cell.

Abstract: Embodiments of the present disclosure are directed to techniques and configurations for an integrated circuit (IC) package having one or more dies connected to an integrated circuit substrate by an interface layer. In one embodiment, the interface layer may include an anisotropic portion configured to conduct electrical signals in the out-of-plane direction between one or more components, such as a die and an integrated circuit substrate. In another embodiment, the interface layer may be a dielectric or electrically insulating layer. In yet another embodiment, the interface layer may include an anisotropic portion that serves as an interconnect between two components, a dielectric or insulating portion, and one or more interconnect structures that are surrounded by the dielectric or insulating portion and serve as interconnects between the same or other components. Other embodiments may be described and/or claimed.

Abstract: A semiconductor device and a method of forming the same are disclosed, which forms a low-dielectric-constant oxide film only at a peripheral part of a bit line conductive material, resulting in reduction in parasitic capacitance of the bit line. The semiconductor device includes a bit line formed over a semiconductor substrate, a first spacer formed over sidewalls of the bit line, and a second spacer formed over sidewalls of the first spacer, configured to have a dielectric constant lower than that of the first spacer.

Abstract: An interconnect structure and fabrication method are provided. A substrate can include a semiconductor device disposed therein. A porous dielectric layer can be formed on the substrate. A surface treatment can be performed to the porous dielectric layer to form an isolation layer on the porous dielectric layer to prevent moisture absorption of the porous dielectric layer. An interconnect can be formed at least through the isolation layer and the porous dielectric layer to provide electrical connection to the semiconductor device disposed in the substrate.

Abstract: A method of fabricating a semiconductor device is disclosed. A first contact layer of the semiconductor device is fabricated. An electrical connection is formed between a carbon nanotube and the first contact layer by electrically coupling of the carbon nanotube and a second contact layer. The first contact layer and second contact layer may be electrically coupled.

Abstract: An article of manufacture includes a semiconductor die (110) having an integrated circuit (105) on a first side of the die (110), a diffusion barrier (125) on a second side of the die (110) opposite the first side, a mat of carbon nanotubes (112) rooted to the diffusion barrier (125), a die attach adhesive (115) forming an integral mass with the mat (112) of the carbon nanotubes, and a die pad (120) adhering to the die attach adhesive and (115) and the mat (112) of carbon nanotubes for at least some thermal transfer between the die (110) and the die pad (120) via the carbon nanotubes (112). Other articles, integrated circuit devices, structures, and processes of manufacture, and assembly processes are also disclosed.

Abstract: A semiconductor device connected by an anisotropic conductive film, the film having a storage modulus of 100 MPa to 300 MPa at 40° C. after curing of the film, and a peak point of 80° C. to 90° C. in a DSC (Differential Scanning calorimeter) profile of the film.

Abstract: Fabricating conductive lines in an integrated circuit includes patterning a layer of a transition metal to form the conductive lines and depositing a protective cap on at least some of the one or more conductive lines. Alternatively, fabricating conductive lines in an integrated circuit includes patterning a layer of a transition metal to form the conductive lines, wherein the conductive lines have sub-eighty nanometer pitches, and depositing a protective cap on at least some of the conductive lines, wherein the protective cap has a thickness between approximately five and fifteen nanometers. Alternatively, fabricating conductive lines in an integrated circuit includes patterning a layer of a transition metal to form the conductive lines, wherein the conductive lines have sub-eighty nanometer line widths, and depositing a protective cap on at least some of the conductive lines, wherein the protective cap has a thickness between approximately five and fifteen nanometers.

Abstract: The present disclosure provides a method of fabricating a semiconductor device, a semiconductor device fabricated by such a method, and a chemical mechanical polishing (CMP) tool for performing such a method. In one embodiment, a method of fabricating a semiconductor device includes providing an integrated circuit (IC) wafer including a metal conductor in a trench of a dielectric layer over a substrate, and performing a chemical mechanical polishing (CMP) process to planarize the metal conductor and the dielectric layer. The method further includes cleaning the planarized metal conductor and dielectric layer to remove residue from the CMP process, rinsing the cleaned metal conductor and dielectric layer with an alcohol, and drying the rinsed metal conductor and dielectric layer in an inert gas environment.

Abstract: Discussed generally herein are devices that include high density interconnects between dice and techniques for making and using those devices. In one or more embodiments a device can include a bumpless buildup layer (BBUL) substrate including a first die at least partially embedded in the BBUL substrate, the first die including a first plurality of high density interconnect pads. A second die can be at least partially embedded in the BBUL substrate, the second die including a second plurality of high density interconnect pads. A high density interconnect element can be embedded in the BBUL substrate, the high density interconnect element including a third plurality of high density interconnect pads electrically coupled to the first and second plurality of high density interconnect pads.

Abstract: A semiconductor device includes a semiconductor element in the form of a flat plate that has opposed first and second surfaces, an insulating layer that covers control wiring located on the first surface side of the semiconductor element, a metal block that is bonded to the first surface side of the semiconductor element via a solder layer, and a protective film that is formed between the metal block and the insulating layer, the protective film having a hardness equal to or greater than a hardness of the metal block. When viewed from the first surface side, the protective film is formed in an area at least including a position where an edge portion of the metal block and the control wiring cross each other.

Abstract: A structure and method for air cavity packaging, the structure comprises a carrier having plural die pads and leads, plural dies, plural wires, plural walls, and a lid. The dies are mounted on the die pads. The wires electrically connect the dies to the leads. The plural walls are disposed on the carrier and form plural cavities in a way that each cavity contains at least one die pad and plural leads, and each wall is provided with at least one air vent for exhausting air to the outside. The lid is attached on the plural walls via an adhesive agent to seal the plural air cavities, so that the plural connected air cavity packages are formed.

Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes providing a substrate. A patterned dielectric layer with a plurality of openings is formed on the substrate. A barrier layer is deposited in the openings by a first tool and a sacrificing protection layer is deposited on the barrier layer by the first tool. The sacrificing layer is removed and a metal layer is deposited on the barrier layer by a second tool.

Abstract: The present invention provides an electric circuit device in which it is possible to achieve simultaneously the improvement of cooling performance and reduction in operating loss due to line inductance. The above object can be attained by constructing multiple plate-like conductors so that each of these conductors electrically connected to multiple semiconductor chips is also thermally connected to both chip surfaces of each such semiconductor chip to release heat from the chip surfaces of each semiconductor chip, and so that among the above conductors, a DC positive-polarity plate-like conductor and a DC negative-polarity plate-like conductor are opposed to each other at the respective conductor surfaces.

Abstract: Semiconductor devices are described that have a through-substrate via formed therein. In one or more implementations, the semiconductor devices include a top wafer and a bottom wafer bonded together with a patterned adhesive material. The top wafer and the bottom wafer include one or more integrated circuits formed therein. The integrated circuits are connected to one or more conductive layers deployed over the surfaces of the top and bottom wafers. A via is formed through the top wafer and the patterned adhesive material so that an electrical interconnection can be formed between the integrated circuits formed in the top wafer and the integrated circuits formed in the bottom wafer. The via includes a conductive material that furnishes the electrical interconnection between the top and bottom wafers.

Abstract: An MCM includes a two-dimensional array of facing chips, including island chips and bridge chips that communicate with each other using overlapping connectors. In order to maintain the relative vertical spacing of these connectors, compressible structures are in cavities in a substrate, which house the bridge chips, provide a compressive force on back surfaces of the bridge chips. These compressible structures include a compliant material with shape and volume compression. In this way, the MCM may ensure that facing surfaces of the island chips and the bridge chips, as well as connectors on these surfaces, are approximately coplanar without bending the bridge chips.

Abstract: A diode arrangement includes a diode and two electrodes. Each electrode is connected to the diode in an electrically conductive manner via a soldered connection on one of two oppositely arranged contact surfaces of the diode. The contact surfaces of the diode are formed substantially by the surfaces of a lower side and an upper side of the diode and are contacted with the contact extensions of the electrodes via the soldered connection. The contact extensions forming counter contact surfaces are substantially congruent with the contact surfaces of the diode.

Abstract: A component and a method for producing a component are disclosed. The component comprises an integrated circuit, a housing body, a wiring device overlapping the integrated circuit and the housing body, and one or more external contact devices in communication with the wiring device.

Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes forming a first functional region of an integrated circuit over a workpiece, and forming a second functional region of the integrated circuit over the workpiece. The method includes forming a guard ring around the first functional region of the integrated circuit. The guard ring is formed in a material layer disposed over the first functional region and the second functional region.

Abstract: A semiconductor wafer includes a first main face and a second main face opposite to the first main face and a number of semiconductor chip regions. The wafer is diced along dicing streets to separate the semiconductor chip regions from each other. At least one metal layer is formed on the first main face of each one of the semiconductor chip regions.

Abstract: A germanium semiconductor radiation detector contact made of yttrium metal. A thin (˜1000 ?) deposited layer of yttrium metal forms a thin hole-barrier and/or electron-barrier contact on both p- and n-type germanium semiconductor radiation detectors. Yttrium contacts provide a sufficiently high hole barrier to prevent measurable contact leakage current below ˜120 K. The yttrium contacts can be conveniently segmented into multiple electrically independent electrodes having inter-electrode resistances greater than 10 G?. Germanium semiconductor radiation detector diodes fabricated with yttrium contacts provide good gamma-ray spectroscopy data.

Abstract: A semiconductor device having a polymer layer and a method of fabricating the same is provided. A two-step plasma treatment for a surface of the polymer layer includes a first plasma process to roughen the surface of the polymer layer and loosen contaminants, and a second plasma process to make the polymer layer smoother or make the polymer layer less rough. An etch process may be used between the first plasma process and the second plasma process to remove the contaminants loosened by the first plasma process. In an embodiment, the polymer layer exhibits a surface roughness between about 1% and about 8% as measured by Atomic Force Microscopy (AFM) with the index of surface area difference percentage (SADP) and/or has surface contaminants of less than about 1% of Ti, less than about 1% of F, less than about 1.5% Sn, and less than about 0.4% of Pb.

Abstract: In a semiconductor integrated circuit sandwiched between a pair of a first impact resistance layer and a second impact resistance layer, an impact diffusion layer is provided between the semiconductor integrated circuit and the second impact resistance layer. By provision of the impact resistance layer against the external stress and the impact diffusion layer for diffusing the impact, force applied to the semiconductor integrated circuit per unit area is reduced, so that the semiconductor integrated circuit is protected. The impact diffusion layer preferably has a low modulus of elasticity and high breaking modulus.

Abstract: A method of manufacturing a composite module prevents a connection electrode electrically coupled to a functional element from separating from a first principal surface of an element substrate. A transmission filter element, a reception filter element, connection electrodes electrically coupled to the transmission filter element and the reception filter element, and an insulating layer surrounding the transmission filter element, the reception filter element, and the connection electrodes are disposed on a first principal surface of an element substrate. The insulating layer covers at least a portion of the surface of each of the connection electrodes. Because the portion of the surface of each of the connection electrodes in an exposed state is covered with the insulating layer, the connection electrodes electrically coupled to the transmission filter element and the reception filter element are prevented from separating from the first principal surface of the element substrate.

Abstract: In-package fly-by signaling can be provided in a multi-chip microelectronic package having address lines on a package substrate configured to carry address information to a first connection region on the substrate having a first delay from terminals of the package, and the address lines being configured to carry the address information beyond the first connection region to at least to a second connection region having a second delay from the terminals that is greater than the first delay. Address inputs of a first microelectronic element, e.g., semiconductor chip, can be coupled with each of the address lines at the first connection region, and address inputs of a second microelectronic element can be coupled with each of the address lines at the second connection region.

Abstract: A semiconductor substrate is provided having a first metal layer formed over a first insulating layer. A second insulating layer is formed having a first damascene opening, the first opening having a second insulating layer portion formed therein. A resist layer is deposited to fill the first opening and the resist layer is thereafter patterned to form an etching mask for etching a second damascene opening. The second opening is etched into a portion of the second insulating layer, the second opening exposing a portion of the first metal layer. A second metal layer is formed to include filling the first and second damascene openings embedding the second insulating layer portion in the second metal layer. The second metal layer is planarized and a passivation layer is formed above the second insulating layer and the second metal layer, wherein the passivation layer partially covers the second metal layer.

Abstract: A semiconductor wafer is made by forming a first conductive layer over a sacrificial substrate, mounting a semiconductor die to the sacrificial substrate, depositing an insulating layer over the semiconductor die and first conductive layer, exposing the first conductive layer and contact pad on the semiconductor die, forming a second conductive layer over the insulating layer between the first conductive layer and contact pad, forming solder bumps on the second conductive layer, depositing an encapsulant over the semiconductor die, first conductive layer, and interconnect structure, and removing the sacrificial substrate after forming the encapsulant to expose the conductive layer and semiconductor die. A portion of the encapsulant is removed to expose a portion of the solder bumps. The solder bumps are sized so that each extends the same outside the encapsulant. The semiconductor die are stacked by electrically connecting the solder bumps.

Abstract: A method of metal sputtering, comprising the following steps. A wafer holder and inner walls of a chamber are coated with a seasoning layer comprised of: a) a material etchable in a metal barrier layer etch process; or b) an insulating or non-conductive material. A wafer having two or more wafer conductive structures is placed upon the seasoning layer coated wafer holder. The wafer is cleaned wherein a portion of the seasoning layer is re-deposited upon the wafer over and between adjacent wafer conductive structures. A metal barrier layer is formed over the wafer. The wafer is removed from the chamber and at least two adjacent upper metal structures are formed over at least one portion of the metal barrier layer.