Abstract: Methods of forming integrated circuit devices include forming an interlayer insulating layer having a trench therein, on a substrate and forming an electrical interconnect (e.g., Cu damascene interconnect) in the trench. An upper surface of the interlayer insulating layer is recessed to expose sidewalls of the electrical interconnect. An electrically insulating first capping pattern is formed on the recessed upper surface of the interlayer insulating layer and on the exposed sidewalls of the electrical interconnect, but is removed from an upper surface of the electrical interconnect. A metal diffusion barrier layer is formed on an upper surface of the electrical interconnect, however, the first capping pattern is used to block formation of the metal diffusion barrier layer on the sidewalls of the electrical interconnect. This metal diffusion barrier layer may be formed using an electroless plating technique.

Abstract: When letters are written with a ballpoint pen, pen pressure is greater than or equal to 10 MPa. The IC tag embedded in the paper base material is required to withstand such pen pressure. An integrated circuit including a functional circuit which transmits and receive, performs arithmetic of, and stores information is thinned, and also, when the integrated circuit and a structural body provided with an antenna or a wiring are attached, a second structural body formed of ceramics or the like is also attached to at the same time. When the second structural body formed of ceramics or the like is used, resistance to pressing pressure or bending stress applied externally can be realized. Further, a part of passive elements included in the integrated circuit can be transferred to the second structural body, which leads to reduction in area of the semiconductor device.

Abstract: An interconnect structure including a lower interconnect level with a first dielectric layer having a first conductive material embedded therein; a dielectric capping layer located on the first dielectric layer and some portions of the first conductive material; an upper interconnect level including a second dielectric layer having at least one via opening filled with a second conductive material and at least one overlying line opening filled with the second conductive material disposed therein, wherein the at least one via opening is in contact with the first conductive material in the lower interconnect level by a via gouging feature; a dielectric liner on sidewalls of the at least one via opening; and a first diffusion barrier layer on sidewalls and a bottom of both the at least one via opening and the at least one overlying line opening. A method of forming the interconnect structure is also provided.

Abstract: Two substrates are brought together and placed in a plating bath. In one embodiment, a conductive material is plated in microscopic cavities present at the interface between a first metal pad and a second metal pad to form at least one interfacial plated metal liner portion that adheres to a surface of the first metal pad and a surface of the second metal pad. In another embodiment, at least one metal pad is recessed relative to a dielectric surface before being brought together. The two substrates are placed in a plating bath and a conductive material is plated in the cavity between the first metal pad and the second metal pad to form a contiguous plated metal liner layer that adheres to a surface of the first metal pad and a surface of the second metal pad.

Abstract: The semiconductor device includes an interlayer insulating film, a wiring provided in the interlayer insulating film, and a SiN film provided over the interlayer insulating film and over the wiring. The peak positions of Si—N bonds of the SiN film, which are measured by FTIR, are within the range of 845 cm?1 to 860 cm?1. This makes it possible to inhibit current leakage in a silicon nitride film, which is a barrier insulating film for preventing the diffusion of wiring metal.

Abstract: A system and method for a distributed metal routing is disclosed. An embodiment comprises a metal_0 layer with a metal_1 layer overlying the metal_0 layer. The metal_1 layer comprises separate parallel lines, with lines having different signals being distributed across the metal_1 layer. Such a layout decreases the parasitic resistance within the metal_0 layer as it decreases the distance current travels. Additionally, the distributed layout in metal_1 allows connections to be made to a metal_2 layer without the need for a hammer head connection of vias.

Abstract: A three-dimensional stacked IC device has a stack of contact levels at an interconnect region. According to some examples of the present invention, it only requires a set of N etch masks to create up to and including 2N levels of interconnect contact regions at the stack of contact levels. According to some examples, 2x?1 contact levels are etched for each mask sequence number x, x being a sequence number for the masks so that for one mask x=1, for another mask x=2, and so forth through x=N. Methods create the interconnect contact regions aligned with landing areas at the contact levels.

Abstract: An interconnect structure for integrated circuits incorporates manganese silicate and manganese silicon nitride layers that completely surrounds copper wires in integrated circuits and methods for making the same are provided. The manganese silicate forms a barrier against copper diffusing out of the wires, thereby protecting the insulator from premature breakdown, and protecting transistors from degradation by copper. The manganese silicate and manganese silicon nitride also promote strong adhesion between copper and insulators, thus preserving the mechanical integrity of the devices during manufacture and use. The strong adhesion at the copper-manganese silicate and manganese silicon nitride interfaces also protect against failure by electromigration of the copper during use of the devices. The manganese-containing sheath also protects the copper from corrosion by oxygen or water from its surroundings.

Abstract: A semiconductor device includes a lower semiconductor layer with first conductive regions and including at least one dummy first conductive region, an upper semiconductor layer with second conductive regions on the lower semiconductor layer and including at least one dummy second conductive region, a penetration hole in the upper semiconductor layer and penetrating the dummy second conductive region and the upper semiconductor layer under the dummy second conductive region, a lower conductive line on the lower semiconductor layer and electrically connected to the first conductive regions, an upper conductive line on the upper semiconductor layer and electrically connected to the second conductive regions, and a first conductive plug in the penetration hole between the lower conductive line and the upper conductive line, the first conductive plug electrically connecting the lower and upper conductive lines and being spaced apart from sidewalls of the penetration hole.

Abstract: A fabrication method of a wafer structure includes: providing a substrate having a plurality of die regions and an edge region surrounding the die regions defined thereon; then, forming a dielectric layer, a plurality of MEMS devices, a plurality of metal-interconnect structures and a plurality bonding pads on the substrate in the die regions; next, removing the dielectric layer disposed on the substrate of the edge region to expose the substrate; and thereafter, forming a passivation layer to cover the substrate and the dielectric layer.

Abstract: Embodiments are directed to the formation of multi-layer three-dimensional structures by forming and attaching a plurality of layers where each of the plurality of layers comprises at least one structural material forming a pattern and where at least one of the plurality of layers comprises at least one sacrificial material. In one embodiment, the formation of a multi-layer three-dimensional structure comprises (1) forming a plurality of individual layers and (2) attaching at least the formed plurality of individual layers together. In another embodiment, the formation of a multi-layer three-dimensional structure comprises (1) attaching an individual layer onto a substrate or onto a previously formed layer; (2) processing the attached individual layer to form a new layer comprising at least one material forming a pattern; and (3) repeating the steps of (1) and (2) one or more times.

Abstract: Fabrication methods for semiconductor device structures are provided. One method for fabricating a semiconductor device structure that includes a gate structure overlying a semiconductor substrate and a doped region formed in the semiconductor substrate adjacent to the gate structure involves the steps of forming a first layer of dielectric material overlying the gate structure and the doped region, isotropically etching the first layer of dielectric material, forming a second layer of dielectric material overlying the first layer of dielectric material after isotropically etching the first layer, and forming a conductive contact that is electrically connected to the doped region within the first layer and the second layer.

Abstract: A method for forming conductive contacts and interconnects in a semiconductor structure, and the resulting conductive components are provided. In particular, the method is used to fabricate single or dual damascene copper contacts and interconnects in integrated circuits such as memory devices and microprocessor.

Abstract: A metal wiring layer and a method of fabricating the metal wiring layer are provided. The method includes forming a dielectric layer on a substrate, forming a plurality of dielectric layer patterns and holes therein on the substrate by etching part of the dielectric layer, with a cross sectional area of the holes in the dielectric layer patterns decreasing with increasing distance away from the substrate and the holes exposing the substrate, forming a trench by etching a portion of the substrate exposed through the holes in the dielectric layer patterns, and forming a metal layer which fills the trench and the holes in the dielectric layer patterns. Thus, it is possible to prevent the occurrence of an edge build-up phenomenon by forming a metal layer in a plurality of holes in the dielectric layer patterns having a cross sectional area decreasing with increasing distance away from the substrate.

Abstract: A multi-level integrated circuit comprising a superposition of a first stack and a second stack of layers, and including: a first row of electronic devices produced in the first stack, extending parallel to a first direction and fitting into a first volume with a substantially parallelepiped rectangle shape and having edges perpendicular to the first direction and with dimension H1; a second row of electronic devices produced in the second stack, extending parallel to the first direction and fitting into a second volume with a substantially parallelepiped rectangle shape and having edges perpendicular to the first direction and with dimension H2<H1; a plurality of electrical connection elements passing through the second stack of layers, each connection element fitting into a third volume arranged on the first volume and next to the second volume.

Abstract: The present invention provides a semiconductor device and manufacturing method of the semiconductor device which can prevent breaks in an interlayer insulation film (12) and electrode (13) that arise with bonding while maintaining bonding strength. A semiconductor element (1) mounted on a semiconductor device including an interlayer insulation film (12) which has an aperture part (123) having an opening shape which is defined by an extension part (121) which covers the gate electrode (116) and extends in the first direction, a connection part (122), the extension part (121) and the connection part (122) which connects at fixed intervals in the first direction a pair of extension parts (121) which are adjacent to the second direction, and which exposes a main surface of a base region (112) and a main surface of an emitter region (113).

Abstract: A system and method are provided for fabricating a low electric resistance ohmic contact, or interface, between a Carbon Nanotube (CNT) and a desired node on a substrate. In one embodiment, the CNT is a Multiwalled, or Multiwall, Carbon Nanotube (MWCNT), and the interface provides a low electric resistance ohmic contact between all conduction shells, or at least a majority of conduction shells, of the MWCNT and the desired node on the substrate. In one embodiment, a Focused Electron Beam Chemical Vapor Deposition (FEB-CVD) process is used to deposit an interface material near an exposed end of the MWCNT in such a manner that surface diffusion of precursor molecules used in the FEB-CVD process induces lateral spread of the deposited interface material into the exposed end of the MWCNT, thereby providing a contact to all conduction shells, or at least a majority of the conduction shells, of the MWCNT.

Abstract: A through substrate via having a low stress is provided. The through substrate via is positioned in a substrate. The through substrate via includes: an outer tube penetrating the substrate; at least one inner tube disposed within the outer tube; a dielectric layer lining on a side wall of the outer tube, and a side wall of the inner tube; a strength-enhanced material filling the inner tube; and a conductive layer filling the outer tube.

Abstract: A stack package includes an upper semiconductor chip having a plurality of first bonding pads which are formed on an upper surface of the upper semiconductor chip and via-holes which are defined in the upper semiconductor chip under the respective first bonding pads; and a lower semiconductor chip attached to a lower surface of the upper semiconductor chip and having a plurality of second bonding pads which are formed on an upper surface of the lower semiconductor chip and bumps which are formed on the respective second bonding pads and are inserted into the respective via-holes to be come into the respective first bonding pads.

Abstract: An integrated circuit includes a conductive pad and a substrate. The conductive pad is used to transfer a first signal. The substrate blocks a second signal from a first region of the substrate to the conductive pad. A second region of the substrate insulates a third region of the substrate from the first region. The first and third regions include a first type of semiconductor and the second region includes a second type of semiconductor. In addition, a first shadow obtained by perpendicularly projecting the third region onto a surface of the substrate overlaps with a second shadow obtained by perpendicularly projecting the conductive pad onto the surface.

Abstract: An integrated circuit chip includes a substrate die and integrated circuits and a layer incorporating a front electrical interconnect network formed on a front face of the substrate die. A local electrical connection via made of an electrically conductive material is formed in a hole of the substrate die. The via is linked to a connection portion of the electrical interconnect network. An electrical connection pillar made of an electrically conductive material is formed on a rear part of the electrical connection via. A local external protection layer at least partly covers the electrical connection via and the electrical connection pillar.

Abstract: A low thermal pathway is provided from the top surface of a silicon substrate to the bottom surface of the silicon substrate by first forming aluminum plugs in the bottom surface of the silicon substrate that contact the silicon substrate and extend up towards the top surface, and then heating the aluminum plugs to a temperature for a period of time sufficient to cause spikes to grow from the sides of the aluminum plugs.

Abstract: A method of forming a compressible contact structure on a semi-conductor chip which comprises bonding a compressible polymer layer to the chip's surface, forming a plurality of openings within the layer, depositing electrically conductive material within the openings to form electrical connections with the chip's contacts, forming a plurality of electrically conductive line elements on the polymer layer extending from a respective opening and each including an end portion, and forming a plurality of contact members each on a respective one of the line segment end portions. The compressible polymer layer allows the contact members to deflect toward (compress) the chip when the contact members are engaged by an external force or forces. A semi-conductor chip including such a compressible contact structure is also provided.

Abstract: A semiconductor device and systems and methods for forming a semiconductor device are provided. A method of manufacturing a semiconductor device can include patterning a first conductive element on a first layer of a semiconductor device, patterning a second conductive element on a second layer of a semiconductor device, and forming an electrical connection in a third layer of the semiconductor device at a predetermined location between the first and the second conductive elements, the connection between the first and the second conducting elements having a geometry that is larger in at least one dimension relative to the corresponding dimension of the second conductive element at the predetermined location.

Abstract: When a bump electrode is formed on an opening formed in a semiconductor substrate, the invention prevents a void that is caused by gas trapped in the opening. A method of manufacturing a semiconductor device of the invention includes forming a first wiring on a main surface of a semiconductor substrate, forming an opening in the semiconductor substrate from the back surface to the main surface so as to expose the back surface of the first wiring, forming a second wiring connected to the back surface of the first wiring and extending from inside the opening onto the back surface of the semiconductor substrate, forming a solder layer connected to part of the second wiring on the bottom of the opening and extending from inside the opening onto the back surface of the semiconductor substrate, and forming a bump electrode on the opening by reflowing the solder layer.

Abstract: A semiconductor device includes an embedding layer in which one or more semiconductor element(s) is embedded and one or more interconnect layers as well as one or more insulation layers on one or both sides of the embedding layer. The embedding layer includes a woven cloth formed by reinforcement fibers. The woven cloth has an opening on its site embedding the semiconductor element. The opening is arranged so that direction of the reinforcement fibers will have a preset angle with respect to a direction of a side of or a tangent to at least a portion of the opening, the preset angle being other than a square angle or a zero angle (parallelism).

Abstract: Presented are methods of fabricating three-dimensional integrated circuits that include post-contact back end of line through-hole via integration for the three-dimensional integrated circuits. Another aspect of the present invention includes three-dimensional integrated circuits fabricated according to methods of the present invention.

Abstract: A method of manufacturing a non-volatile memory device providing a semiconductor layer in which a cell region and a peripheral region are defined, sequentially forming a first insulating layer, a first conductive layer, a second insulating layer, and a second conductive layer on the cell region and the peripheral region, forming a trench for exposing a portion of the first conductive layer of the peripheral region, wherein the trench is formed by removing portions of the second conductive layer and the second insulating layer in the peripheral region, performing a trimming operation for removing portions of the second conductive layer and the second insulating layer of the cell region, forming a spacer on a side surface of the trench, and forming a silicide layer that is electrically connected to the first conductive layer, wherein the silicide layer is formed by performing a silicidation process on the spacer.

Abstract: A manufacturing method of a circuit structure is provided as follows. Firstly, a base conductive layer is formed on the carrier board and a first patterned plating-resistant layer having at least one trench for exposing a part of the base conductive layer is formed on the base conductive layer. A first patterned conductive layer is then formed in the trench and a second patterned plating-resistant layer is formed which covers a part of the first patterned conductive layer and a part of the first patterned plating-resistant layer. A second patterned conductive layer is formed on the exposed first patterned conductive layer. The first and the second patterned plating-resistant layers and the base conductive layer exposed by the first patterned conductive layer are removed. Then, a patterned solder mask is formed for covering a part of the first patterned conductive layer.

Abstract: A Cu-CMP step applied to processes for 130 nm, 90 nm, and 65 nm technical nodes or the like mainly employs slurry to which an anticorrosive agent is added for preventing corrosion of Cu wiring. The inventors of the present application have studied and clearly found that in the Cu-CMP step using the slurry with the anticorrosive agent added thereto, the anticorrosive agent often forms complexes with Cu, which remain as foreign matter on a wafer in large quantity, leading to a reduction in yield, and in reliability of TDDB characteristics of the Cu wiring. In the invention of the present application, a post-CMP cleaning process involves applying wet cleaning to a wafer by supplying a cleaning solution, such as a chemical solution or pure water, to a device surface of the wafer substantially in a vertical direction with respect to the horizontal device surface, while rotating the wafer substantially about its center in the horizontal plane.

Abstract: A circuit board having an electrically connecting structure and a method for fabricating the same are provided. A circuit board body having inner-layer circuits is provided. A circuit layer is formed on at least an outermost surface of circuit board body, and including electrically connecting pads and circuits. The electrically connecting pads are partially electrically connected to the circuits, and are partially electrically connected to the inner-layer circuits via conductive vias. An insulating protective layer is disposed on the circuit board body and is formed with openings therein for exposing the electrically connecting pads. Conductive posts are formed on the electrically connecting pads. Standalone metal pads are formed on the insulating protective layer but are not used for electrical connection.

Abstract: A printed wiring board and a method for manufacturing the same are provided. The printed wiring board includes a resin insulation layer having a first surface and a second surface opposite the first surface, and includes an opening for a first via conductor. An electronic-component mounting pad is formed on the first surface of the resin insulation layer. The electronic-component mounting pad includes a portion embedded in the resin insulation layer and a portion protruding from the resin insulation layer. The protruding portion covers the embedded portion and a portion of the first surface of the resin insulation layer that surrounds the embedded portion. A first conductive circuit is formed on the second surface of the resin insulation layer. A first via conductor is formed in the opening of the resin insulation layer and connects the electronic-component mounting pad and the first conductive circuit.

Abstract: A method includes dividing a semiconductor wafer into a plurality of dies areas, generating a map of the semiconductor wafer, scanning each of the plurality of die areas of the semiconductor wafer with a laser, and adjusting a parameter of the laser during the scanning based on a value of the die areas identified by the map of the semiconductor wafer. The map characterizing the die areas based on a first measurement of each individual die area.

Abstract: Methods and a structure. A method of forming contact structure includes depositing a silicide layer onto a substrate; depositing an electrically insulating layer over a first surface of the silicide layer; forming a via through the insulating layer extending to the first surface; depositing an electrically conductive layer covering a bottom and at least one vertical wall of the via; removing the conductive layer from the bottom; and filling the via with aluminum directly contacting the silicide layer. A structure includes: a silicide layer disposed on a substrate; an electrically insulating layer disposed over the silicide layer; an aluminum plug extending through the insulating layer and directly contacting the silicide layer; and an electrically conductive layer disposed between the plug and the insulating layer. Also included is a method where an aluminum layer grows selectively from a silicide layer and at least one sidewall of a trench.

Abstract: A manufacturing method for a buried circuit structure includes providing a substrate having at least a trench therein, forming a conductive layer having a top lower than an opening of the trench in the trench, performing a selective metal chemical vapor deposition (CVD) to form a metal layer having a top lower than the substrate in the trench, and forming a protecting layer filling the trench on the metal layer.

Abstract: To reduce connection defects between a circuit substrate provided on a core substrate and a circuit to be mounted thereon, thereby improving reliability as a multilayered device mounting substrate. The device mounting substrate includes: a first circuit substrate composed of a substrate, an insulating layer formed on this substrate, and a first conductive layer (including conductive parts) formed on this insulating layer; and a second circuit substrate mounted on the first circuit substrate, being composed of a base, a second conductive layer (including conductive parts) formed on the bottom of the base, and a third conductive layer (including conductive parts) formed on the top of the base. Here, the first and second circuit substrates are bonded by pressure so that the first and second conductive parts are laminated and embedded together into the insulating layer.

Abstract: A method of fabricating a thin film device having conductive front and backside electrodes or contacts. Top-side cavities are first formed on a first dielectric layer, followed by the deposition of a metal layer on the first dielectric layer to fill the cavities. Defined metal structures are etched from the metal layer to include the cavity-filled metal, followed by depositing a second dielectric layer over the metal structures. Additional levels of defined metal structures may be formed in a similar manner with vias connecting metal structures between levels. After a final dielectric layer is deposited, a top surface of a metal structure of an uppermost metal layer is exposed through the final dielectric layer to form a front-side electrode, and a bottom surface of a cavity-filled portion of a metal structure of a lowermost metal layer is also exposed through the first dielectric layer to form a back-side electrode.

Abstract: In an embodiment, an integrated circuit is provided. The integrated circuit may include an active area extending along a first direction corresponding to a current flow direction through the active area, a contact structure having an elongate structure. The contact structure may be electrically coupled with the active area. Furthermore, the contact structure may be arranged such that the length direction of the contact structure forms a non-zero angle with the first direction of the active area.

Abstract: The present invention relates to a method for forming a recess array device structure in a semiconductor substrate. The method includes the steps of: providing a base material including a semiconductor substrate and a first material; forming a plurality of second recesses on the semiconductor substrate; forming a second material in the second recesses; forming a metal layer on the second material and the base material, wherein the metal layer includes a first portion and a second portion; removing the second portion to form a plurality of metal layer openings; to and etching the base material according to the metal layer openings so as to form a plurality of third recesses. Accordingly, the metal layer can overcome the non-selectivity issue during the etching process.

Abstract: A manufacturing method of a semiconductor device comprises: providing a first insulating film whose relative dielectric constant is at most a predetermined value above a substrate; providing a second insulating film whose relative dielectric constant is greater than the predetermined value on a surface of the first insulating film; forming a recess for a wire through the second insulating film and extending into the first insulating film, and also forming a recess for a dummy wire through the second insulating film and extending into the first insulating film spaced from a formed area of the recess for the wire; providing a conductive material inside the recess for the wire and the recess for the dummy wire; and providing a wire inside the recess for the wire and providing a dummy wire inside the recess for the dummy wire by polishing and removing the conductive material.

Abstract: Stability of an underlying dielectric diffusion barrier during deposition and ultraviolet (UV) processing of an overlying dielectric layer is critical for successful integration. UV-resistant diffusion barrier layers are formed by depositing the layer in a hydrogen-starved environment. Diffusion barrier layers can be made more resistant to UV radiation by thermal, plasma, or UV treatment during or after deposition. Lowering the modulus of the diffusion barrier layer can also improve the resistance to UV radiation.

Abstract: An apparatus is provided that includes a plurality of array dies and at least two die interconnects. The first die interconnect is in electrical communication with a data port of a first array die and a data port of a second array die and not in electrical communication with data ports of a third array die. The second die interconnect is in electrical communication with a data port of the third array die and not in electrical communication with data ports of the first array die and the second array die. The apparatus includes a control die that includes a first data conduit configured to transmit a data signal to the first die interconnect and not to the second die interconnect, and at least a second data conduit configured to transmit the data signal to the second die interconnect and not to the first die interconnect.

Abstract: Techniques described herein generally relate to laminated semiconductor structures. In some examples, method of forming a polyimide film are described. An example method may include forming a through hole in a laminated semiconductor structure that includes multiple stacked semiconductor layers. An inner wall of the laminated semiconductor structure can define the through hole. The inner wall can be exposed to a solution including a salt of polyamic acid and/or a polyamic acid that can be precipitated on the inner wall. The precipitated polyamic acid on the inner wall can be transformed into a polyimide film substantially coating the inner wall.

Abstract: An improved interconnect structure including a dielectric layer having a conductive feature embedded therein, the conductive feature having a first top surface that is substantially coplanar with a second top surface of the dielectric layer; a metal cap layer located directly on the first top surface, wherein the metal cap layer does not substantially extend onto the second top surface; a first dielectric cap layer located directly on the second top surface, wherein the first dielectric cap layer does not substantially extend onto the first top surface and the first dielectric cap layer is thicker than the metal cap layer; and a second dielectric cap layer on the metal cap layer and the first dielectric cap layer. A method of forming the interconnect structure is also provided.

Abstract: A first low dielectric constant (low-k) dielectric material layer is lithographically patterned to form a recessed region having expose substantially vertical sidewalls, which are subsequently damaged to de-carbonize a surface portion at the sidewalls having a sublithographic width. A second low-k dielectric material layer is deposited to fill the recessed region and planarized to exposed top surfaces of the damaged low-k dielectric material portion. The damaged low-k dielectric material portion is removed selective to the first and second low-k dielectric material layers to form a trench with a sublithographic width. A portion of the pattern of the sublithographic-width trench is transferred into a metallic layer and optionally to an underlying dielectric masking material layer to define a trench with a sublithographic width, which can be employed as a template to confine the widths of via holes and line trenches to be subsequently formed in an interconnect-level dielectric material layer.

Abstract: Methods of making interconnect structures are provided. In one aspect of the innovation, when forming a trench or via in a dielectric layer, the sidewall surface of another via and/or trench is covered with a metal oxide layer. The metal oxide layer can prevent and/or mitigate surface erosion of the sidewall surface. As a result, the methods can improve the controllability of critical dimensions of the via and trench.

Abstract: A one transistor DRAM device includes: a substrate with an insulating layer, a first semiconductor layer provided on the insulating layer and including a first source region and a first region which are in contact with the insulating layer and a first floating body between the first source region and the first drain region, a first gate pattern to cover the first floating body, a first interlayer dielectric to cover the first gate pattern, a second semiconductor layer provided on the first interlayer dielectric and including a second source region and a second drain region which are in contact with the first interlayer dielectric and a second floating body between the second source region and the second drain region, and a second gate pattern to cover the second floating body.

Abstract: A semiconductor device is made with a conductive via formed through a top-side of the substrate. The conductive via extends vertically through less than a thickness of the substrate. An integrated passive device (IPD) is formed over the substrate. A plurality of first conductive pillars is formed over the first IPD. A first semiconductor die is mounted over the substrate. An encapsulant is formed around the first conductive pillars and first semiconductor die. A second IPD is formed over the encapsulant. An interconnect structure is formed over the second IPD. The interconnect structure operates as a heat sink. A portion of a back-side of the substrate is removed to expose the first conductive via. A second semiconductor die is mounted to the back-side of the substrate. The second semiconductor die is electrically connected to the first IPD and first semiconductor die through the conductive via.

Abstract: A semiconductor device may include a substrate and a dielectric layer may be formed on the substrate. A multi-layered interconnection structure may be embedded in the dielectric layer. A plurality of bonding pads, which may be connected to an uppermost interconnection layer of the multi-layered interconnection structure, may be spaced apart in a first direction. A passivation layer may have a plurality of bonding pad openings that may be defined by a plurality of slits and respectively expose the bonding pads. The slits may overlap isolations of the bonding pads. Each of the slits may have an edge width that may be larger than a center width thereof.

Abstract: A system and method is disclosed for providing a redistribution metal layer in an integrated circuit. The redistribution metal layer is formed from the last metal layer in the integrated circuit during manufacture of the integrated circuit before final passivation is applied. The last metal layer provides sites for solder bump pads used in flip chip interconnection. The redistribution metal layer can be (1) a flat layer deposited over the next to last metal layer through an opening in a dielectric layer, or (2) deposited over an array of vias connected to the next to last metal layer. Space between the solder bump pads is deposited with narrower traces for connecting active circuit areas below. A final passivation layer is deposited to ensure product reliability.